Patent Application
20250182820
The present disclosure relates to a semiconductor memory device and, in particular, to a static random access memory (SRAM).
Conventionally, a technique of decreasing the voltage by pulling down the voltage of a word line in an active state is known as a technique of improving the static noise margin (SNM) in SRAM.
In SRAM, when the voltage of a word line in an active state is decreased to improve the SNM, the capability to write to a memory cell and the capability to read out from the memory cell (hereinafter, also referred to as read and write capability) are decreased.
In view of this, the present disclosure aims to provide a semiconductor memory device that achieves a voltage drop of a word line to improve the SNM, the voltage drop being such that the read and write capability can be suppressed from decreasing.
A semiconductor memory device according to one aspect of the present disclosure includes: a first pull-down n-channel metal-oxide-semiconductor (MOS) transistor that includes: a drain connected to a first word line connected to one or more first memory cells; a source connected to a ground line that supplies a ground voltage; and a gate connected to a first node; a first series connection n-channel MOS transistor that includes: a drain connected to a power supply line that supplies a power supply voltage; and a source connected to the first node; and a second series connection n-channel MOS transistor that includes: a drain connected to the first node; and a source connected to the ground line, in which the inverse-logic signal of a signal to be input to the gate of the second series connection n-channel MOS transistor is input to the gate of the first series connection n-channel MOS transistor.
A semiconductor memory device according to another aspect of the present disclosure includes: a first pull-down n-channel metal-oxide-semiconductor (MOS) transistor that includes: a drain connected to a first word line connected to one or more first memory cells; a source connected to a ground line that supplies a ground voltage; and a gate connected to a first node; a first p-channel MOS transistor that includes: a source connected to a power supply line that supplies a power supply voltage; and a drain connected to a second node; a first series connection n-channel MOS transistor that includes: a drain connected to the second node; a source connected to the first node; and a gate connected to a first control signal input terminal to which a first control signal is to be input; and a second series connection n-channel MOS transistor that includes: a drain connected to the first node; and a source connected to the ground line, in which a signal with the same logic as a signal to be input to the gate of the second series connection n-channel MOS transistor is input to the gate of the first p-channel MOS transistor.
A semiconductor memory device according to one aspect of the present disclosure is a semiconductor memory device that achieves a voltage drop of the word line to improve the SNM, the voltage drop being such that the read and write capability can be suppressed from decreasing.
These and other advantages and features will become apparent from the following description thereof taken in conjunction with the accompanying Drawings, by way of non-limiting examples of embodiments disclosed herein.
Generally, the SNM is low when a temperature condition is a high-temperature condition and when a process variation condition is that an n-channel metal-oxide-semiconductor (MOS) transistor is fast (the threshold voltage of the n-channel MOS transistor is low).
Moreover, generally, the read and write capability decreases when the temperature condition is a low-temperature condition and when the process variation condition is that the n-channel MOS transistor is slow (the threshold voltage of the n-channel MOS transistor is high).
From the above, with regard to SRAM, the inventors considered that it may be possible to suppress the read and write capability from decreasing without reducing the SNM, if it is possible to control the voltage drop of a word line in the following manner: the voltage drop of the word line in an active state is smaller when the temperature condition is the low-temperature condition than when the temperature condition is the high-temperature condition, and the voltage drop of the word line in an active state is smaller when the process variation condition is that an n-channel MOS transistor is slow than when the process variation condition is that the n-channel MOS transistor is fast.
Thus, on the basis of the above thoughts, the inventors diligently repeated experiments and analysis with regard to a semiconductor memory device that achieves a voltage drop of a word line to improve the SNM, the voltage drop being such that the read and write capability can be suppressed from decreasing.
As a result, the inventors arrived at the following semiconductor memory devices according to the present disclosure.
A semiconductor memory device according to one aspect of the present disclosure includes: a first pull-down n-channel metal-oxide-semiconductor (MOS) transistor that includes: a drain connected to a first word line connected to one or more first memory cells; a source connected to a ground line that supplies a ground voltage; and a gate connected to a first node; a first series connection n-channel MOS transistor that includes: a drain connected to a power supply line that supplies a power supply voltage; and a source connected to the first node; and a second series connection n-channel MOS transistor that includes: a drain connected to the first node; and a source connected to the ground line, in which the inverse-logic signal of a signal to be input to the gate of the second series connection n-channel MOS transistor is input to the gate of the first series connection n-channel MOS transistor.
In the semiconductor memory device configured as above, the voltage of the first node, that is, the gate voltage of the first pull-down n-channel MOS transistor is a voltage (VDD-Vtn) that is lower by the threshold voltage (hereinafter, also referred to as Vtn) of the n-channel MOS transistor than the power supply voltage (hereinafter, also referred to as VDD).
Generally, Vtn is larger under the low-temperature condition than under the high-temperature condition, and is larger under the condition that the n-channel MOS transistor is slow than under the condition that the n-channel MOS transistor is fast.
Thus, the gate voltage of the first pull-down n-channel MOS transistor is lower when the temperature condition is the low-temperature condition than when the temperature condition is the high-temperature condition, and is lower when the process variation condition is that the n-channel MOS transistor is slow than when the process variation condition is that the n-channel MOS transistor is fast.
In the semiconductor memory device configured as above, the first pull-down n-channel MOS transistor pulls down, according to the gate voltage thereof, the voltage of the first word line in an active state such that the lower the gate voltage, the smaller the pull-down voltage of the first word line in an active state.
Accordingly, in the semiconductor memory device configured as above, the voltage drop of the first word line in an active state is controlled such that the voltage drop of the first word line is smaller when the temperature condition is the low-temperature condition than when the temperature condition is the high-temperature condition and such that the voltage drop of the first word line is smaller when the process variation condition is that the n-channel MOS transistor is slow than when the process variation condition is that the n-channel MOS transistor is fast.
In this way, the semiconductor memory device configured as above is a semiconductor memory device that achieves a voltage drop of a word line to improve the SNM, the voltage drop being such that the read and write capability can be suppressed from decreasing.
The semiconductor memory device may further include: a first p-channel MOS transistor that includes: a drain connected to the drain of the first series connection n-channel MOS transistor; a source connected to the power supply line; and a gate connected to a first control signal input terminal to which a first control signal is to be input, in which the drain of the first series connection n-channel MOS transistor may be connected to the power supply line via the first p-channel MOS transistor.
In this way, by controlling the first control signal, it is possible to perform control as to whether to pull down the voltage of the first word line by using the first pull-down n-channel MOS transistor.
The semiconductor memory device may further include: a second pull-down n-channel MOS transistor that includes: a drain connected to a second word line connected to one or more second memory cells; a source connected to the ground line; and a gate connected to a second node; a third series connection n-channel MOS transistor that includes: a drain connected to the drain of the first p-channel MOS transistor; and a source connected to the second node; and a fourth series connection n-channel MOS transistor that includes: a drain connected to the second node; and a source connected to the ground line, in which the inverse-logic signal of a signal to be input to the gate of the fourth series connection n-channel MOS transistor may be input to the gate of the third series connection n-channel MOS transistor.
In the semiconductor memory device configured as above, a p-channel MOS transistor positioned in the current path between the power supply line and the first node and a p-channel MOS transistor positioned in the current path between the power supply line and the second node can made as the common transistor, the first p-channel MOS transistor.
In this way, it is possible to reduce the area for making the p-channel MOS transistor, in comparison with the case where the p-channel MOS transistor positioned in the current path between the power supply line and the first node and the p-channel MOS transistor positioned in the current path between the power supply line and the second node are made as separate transistors.
The semiconductor memory device may further include: a second pull-down n-channel MOS transistor that includes: a drain connected to a second word line connected to one or more second memory cells; a source connected to the ground line; and a gate connected to the first node; a third pull-down n-channel MOS transistor that includes: a drain connected to a third word line connected to one or more third memory cells; a source connected to the ground line; and a gate connected to a second node; a fourth pull-down n-channel MOS transistor that includes: a drain connected to a fourth word line connected to one or more fourth memory cells; a source connected to the ground line; and a gate connected to the second node; a third series connection n-channel MOS transistor that includes: a drain connected to the drain of the first p-channel MOS transistor; and a source connected to the second node; and a fourth series connection n-channel MOS transistor that includes: a drain connected to the second node; and a source connected to the ground line, in which when at least one of the first word line or the second word line is active, the inverse-logic signal of a signal to be input to the gate of the second series connection n-channel MOS transistor may be input to the gate of the first series connection n-channel MOS transistor, and when at least one of the third word line or the fourth word line is active, the inverse-logic signal of a signal to be input to the gate of the fourth series connection n-channel MOS transistor may be input to the gate of the third series connection n-channel MOS transistor.
In the semiconductor memory device configured as above, a p-channel MOS transistor positioned in the current path between the power supply line and the first node and a p-channel MOS transistor positioned in the current path between the power supply line and the second node can made as the common transistor, the first p-channel MOS transistor.
In this way, it is possible to reduce the area for making the p-channel MOS transistor, in comparison with the case where the p-channel MOS transistor positioned in the current path between the power supply line and the first node and the p-channel MOS transistor positioned in the current path between the power supply line and the second node are made as separate transistors.
Furthermore, in the semiconductor memory device configured as above, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of the first pull-down n-channel MOS transistor and an n-channel MOS transistor positioned in the current path between the power supply line and the gate of the second pull-down n-channel MOS transistor can be made as the common transistor, the first series connection n-channel MOS transistor. In addition, an n-channel MOS transistor positioned in the current path between the ground line and the gate of the first pull-down n-channel MOS transistor and an n-channel MOS transistor positioned in the current path between the ground line and the gate of the second pull-down n-channel MOS transistor can be made as the common transistor, the second series connection n-channel MOS transistor.
In this way, it is possible to reduce the area for making the n-channel MOS transistor(s), in comparison with the case where the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the first pull-down n-channel MOS transistor and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the second pull-down n-channel MOS transistor are made as separate transistors, and/or the case where the n-channel MOS transistor positioned in the current path between the ground line and the gate of the first pull-down n-channel MOS transistor and the n-channel MOS transistor positioned in the current path between the ground line and the gate of the second pull-down n-channel MOS transistor are made as separate transistors.
Furthermore, in the semiconductor memory device configured as above, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of the third pull-down n-channel MOS transistor and an n-channel MOS transistor positioned in the current path between the power supply line and the gate of the fourth pull-down n-channel MOS transistor can be made as the common transistor, the third series connection n-channel MOS transistor. In addition, an n-channel MOS transistor positioned in the current path between the ground line and the gate of the third pull-down n-channel MOS transistor and an n-channel MOS transistor positioned in the current path between the ground line and the gate of the fourth pull-down n-channel MOS transistor can be made as the common transistor, the fourth series connection n-channel MOS transistor.
In this way, it is possible to reduce the area for making the n-channel MOS transistor(s), in comparison with the case where the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the third pull-down n-channel MOS transistor and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the fourth pull-down n-channel MOS transistor are made as separate transistors, and/or the case where the n-channel MOS transistor positioned in the current path between the ground line and the gate of third pull-down n-channel MOS transistor and the n-channel MOS transistor positioned in the current path between the ground line and the gate of the fourth pull-down n-channel MOS transistor are made as separate transistors.
The semiconductor memory device may further include: a second pull-down n-channel MOS transistor that includes: a drain connected to the first word line; a source connected to the ground line; and a gate connected to a second node; a second p-channel MOS transistor that includes: a drain connected to a third node; a source connected to the power supply line; and a gate connected to a second control signal input terminal to which a second control signal is to be input; a third series connection n-channel MOS transistor that includes: a drain connected to the third node; and a source connected to the second node; and a fourth series connection n-channel MOS transistor that includes: a drain connected to the second node; and a source connected to the ground line, in which a signal with the same logic as a signal to be input to the gate of the third series connection n-channel MOS transistor may be input to the gate of the first series connection n-channel MOS transistor, and a signal with the same logic as a signal to be input to the gate of the fourth series connection n-channel MOS transistor may be input to the gate of the second series connection n-channel MOS transistor.
In this way, it is possible to select from among the choices: (1) pulling down the first word line by using the first pull-down n-channel MOS transistor, (2) pulling down the first word line by using the second pull-down n-channel MOS transistor, (3) pulling down the first word line by using the first pull-down n-channel MOS transistor and the second pull-down n-channel MOS transistor, and (4) not pulling down the first word line.
A semiconductor memory device according to another aspect of the present disclosure includes: a first pull-down n-channel metal-oxide-semiconductor (MOS) transistor that includes: a drain connected to a first word line connected to one or more first memory cells; a source connected to a ground line that supplies a ground voltage; and a gate connected to a first node; a first p-channel MOS transistor that includes: a source connected to a power supply line that supplies a power supply voltage; and a drain connected to a second node; a first series connection n-channel MOS transistor that includes: a drain connected to the second node; a source connected to the first node; and a gate connected to a first control signal input terminal to which a first control signal is to be input; and a second series connection n-channel MOS transistor that includes: a drain connected to the first node; and a source connected to the ground line, in which a signal with the same logic as a signal to be input to the gate of the second series connection n-channel MOS transistor is input to the gate of the first p-channel MOS transistor.
In the semiconductor memory device configured as above, the voltage of the first node when the first p-channel MOS transistor is conductive, that is, the gate voltage of the first pull-down n-channel MOS transistor when the first p-channel MOS transistor is conductive is changed to VDD-Vtn.
Generally, Vtn is larger under the low-temperature condition than under the high-temperature condition, and is larger under the condition that the n-channel MOS transistor is slow than under the condition that the n-channel MOS transistor is fast.
Thus, the gate voltage of the first pull-down n-channel MOS transistor is lower when the temperature condition is the low-temperature condition than when the temperature condition is the high-temperature condition, and is lower when the process variation condition is that the n-channel MOS transistor is slow than when the process variation condition is that the n-channel MOS transistor is fast.
In the semiconductor memory device configured as above, the first pull-down n-channel MOS transistor pulls down, according to the gate voltage thereof, the voltage of the first word line in an active state such that the lower the gate voltage, the smaller the pull-down voltage of the first word line in an active state.
Accordingly, in the semiconductor memory device configured as above, the voltage drop of the first word line in an active state is controlled such that the voltage drop of the first word line is smaller when the temperature condition is the low-temperature condition than when the temperature condition is the high-temperature condition and such that the voltage drop of the first word line is smaller when the process variation condition is that the n-channel MOS transistor is slow than when the process variation condition is that the n-channel MOS transistor is fast.
In this way, the semiconductor memory device configured as above is a semiconductor memory device that achieves a voltage drop of a word line to improve the SNM, the voltage drop being such that the read and write capability can be suppressed from decreasing.
Furthermore, by controlling the first control signal, the semiconductor memory device configured as above can perform control as to whether to pull down the voltage of the first word line by using the first pull-down n-channel MOS transistor.
The semiconductor memory device may further include: a second pull-down n-channel MOS transistor that includes: a drain connected to a second word line connected to one or more second memory cells; a source connected to the ground line; and a gate connected to the first node.
In the semiconductor memory device configured as above, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the first pull-down n-channel MOS transistor and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the second pull-down n-channel MOS transistor can be made as the common transistor, the first series connection n-channel MOS transistor. In addition, the n-channel MOS transistor positioned in the current path between the ground line and the gate of the first pull-down n-channel MOS transistor and the n-channel MOS transistor positioned in the current path between the ground line and the gate of the second pull-down n-channel MOS transistor can be made as the common transistor, the second series connection n-channel MOS transistor.
Thus, it is possible to increase the size of the first series connection n-channel MOS transistor, in comparison with the case where the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the first pull-down n-channel MOS transistor and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of the second pull-down n-channel MOS transistor are made as separate transistors.
In this way, it is possible to suppress variations in Vtn of the first series connection n-channel MOS transistor.
The semiconductor memory device may further include: a second pull-down n-channel MOS transistor that includes: a drain connected to the first word line; a source connected to the ground line; and a gate connected to the power supply line.
In the semiconductor memory device configured as above, the voltage of the first word line is pulled down by the first pull-down n-channel MOS transistor whose gate voltage is VDD-Vtn and the second pull-down n-channel MOS transistor whose gate voltage is VDD.
In this way, it is possible to control the voltage drop of the first word line more sensitively.
Moreover, the threshold of the first series connection n-channel MOS transistor may be lower than the threshold of the first pull-down n-channel MOS transistor and the threshold of the second series connection n-channel MOS transistor.
In the semiconductor memory device configured as above, when the power supply voltage is set to a low voltage, the gate voltage of the first pull-down n-channel MOS transistor will be lower than the threshold voltage of the first pull-down n-channel MOS transistor. As a result, an occurrence of inconvenience of the first pull-down n-channel MOS transistor not being able to pull down the first word line is suppressed.
Thus, it is possible to expand a low-voltage operation area for the pull-down operation of the first word line.
The semiconductor memory device may further include: a second pull-down n-channel MOS transistor that includes: a drain connected to the first word line; a source connected to the ground line; and a gate connected to a third node; a second p-channel MOS transistor that includes: a source connected to the power supply line; and a drain connected to a fourth node; a third series connection n-channel MOS transistor that includes: a drain connected to the fourth node; a source connected to the third node; and a gate connected to a second control signal input terminal to which a second control signal is to be input; and a fourth series connection n-channel MOS transistor that includes: a drain connected to the third node; and a source connected to the ground line, in which a signal with the same logic as a signal to be input to the gate of the second series connection n-channel MOS transistor may be input to the gate of the second p-channel MOS transistor and the gate of the fourth series connection n-channel MOS transistor.
In this way, it is possible to select from among the choices: (1) pulling down the first word line by using the first pull-down n-channel MOS transistor, (2) pulling down the first word line by using the second pull-down n-channel MOS transistor, (3) pulling down the first word line by using the first pull-down n-channel MOS transistor and the second pull-down n-channel MOS transistor, and (4) not pulling down the first word line.
Hereinafter, specific examples of semiconductor memory devices according to aspects of the present disclosure are described with reference to the figures. Each of the embodiments described herein indicates a specific example of the present disclosure. Accordingly, the numerical values, shapes, constituent elements, arrangement and connection of the constituent elements, as well as steps (processes), orders of the steps, and other details indicated in the following embodiments are merely examples, and do not intend to limit the present disclosure. Moreover, the figures are schematic illustrations and are not necessarily precise depictions. In the figures, substantially the same elements are assigned the same reference signs, and overlapping explanations are omitted or simplified.
Hereinafter, a semiconductor memory device according to Embodiment 1 is described. The semiconductor memory device according to Embodiment 1 is SRAM including a word line, and pulls down and decreases the voltage of the word line in an active state to improve the SNM.
As illustrated in
Memory cell array 50 includes a plurality of memory cells 40 arranged in a matrix.
The plurality of memory cells 40 constituting memory cell array 50 are connected, for each row, to common word line 20. That is, semiconductor memory device 1 includes word lines 20 equal in number to the number of rows of memory cell array 50.
Memory cell array 50 further includes, for each column, a set of bit line 28 and inverted bit line 29. Then, the plurality of memory cells 40 constituting memory cell array 50 are connected, for each column, to a common set of bit line 28 and inverted bit line 29. That is, memory cell array 50 includes sets of bit line 28 and inverted bit line 29 equal in number to the number of columns of memory cell array 50.
As illustrated in
We will return to
Each of the plurality of word lines 20 is connected to one or more memory cells 40 constituting one row of memory cell array 50.
Row decoder 60 selects a row of memory cell array 50. More specifically, row decoder 60 includes a plurality of word line drivers 30 that drive the plurality of word lines 20 in a one-to-one manner. One of the plurality of word line drivers 30 drives one of the plurality of word lines 20 and turns the word line into an active state, thereby selecting the row made up of one or more memory cells 40 connected to one word line 20 turned into an active state.
I/O circuit 70 writes data to memory cell array 50 and reads out data held by memory cell array 50.
Controller 80 controls memory cell array 50, row decoder 60, I/O circuit 70, and the plurality of assist circuits 10.
Assist circuit 10 pulls down and decreases the voltage of word line 20 in an active state.
The plurality of assist circuits 10 are connected to the plurality of word lines 20 in a one-to-one correspondence. That is, semiconductor memory device 1 includes assist circuits 10 equal in number to the number of word lines 20.
As illustrated in
Assist circuit 10 further includes inverter 24 connected in order to input, to the gate of first series connection n-channel MOS transistor 22, the inverse-logic signal of a signal to be input to the gate of second series connection n-channel MOS transistor 23.
In assist circuit 10, when a logic value of 0 is input to terminal c0, that is, when the voltage of terminal c0 is changed to the VSS, first series connection n-channel MOS transistor 22 becomes conductive, and second series connection n-channel MOS transistor 23 becomes non-conductive.
In this way, the voltage of first node 91, that is, the gate voltage of first pull-down n-channel MOS transistor 21 is changed to VDD-Vtn.
Generally, Vtn is larger under the low-temperature condition than under the high-temperature condition, and is larger under the condition that the n-channel MOS transistor is slow than under the condition that the n-channel MOS transistor is fast.
Thus, as illustrated in
In assist circuit 10, first pull-down n-channel MOS transistor 21 pulls down, according to the gate voltage thereof, the voltage of word line 20 in an active state such that the lower the gate voltage, the smaller pull-down voltage Vpd of word line 20 in an active state.
Accordingly, as illustrated in
In this way, semiconductor memory device 1 configured as above can achieve a voltage drop of a word line to improve the SNM, the voltage drop being such that the read and write capability can be suppressed from decreasing.
Hereinafter, a semiconductor memory device according to Embodiment 2 is described which is configured by changing a part of the configuration of semiconductor memory device 1 according to Embodiment 1.
Here, constituent elements in the semiconductor memory device according to Embodiment 2 that are similar to those of semiconductor memory device 1 are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1.
As illustrated in
First control signal input terminal CNT0 is a terminal to which a first control signal is to be input from outside of semiconductor memory device 1A. First control signal input terminal CNT0 is connected to all the gates of first p-channel MOS transistors 25 (see
As illustrated in
Moreover, the gate of first p-channel MOS transistor 25 is connected to first control signal input terminal CNT0 via terminal sel0.
In assist circuit 10A configured as above, the drain of first series connection n-channel MOS transistor 22 is connected to the power supply line via first p-channel MOS transistor 25.
Thus, when a first control signal with a logic value of 0 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, first p-channel MOS transistor 25 becomes conductive. As such, as with assist circuit 10 according to Embodiment 1, in assist circuit 10A, when a logic value of 0 is input to terminal c0, that is, the voltage of terminal c0 is changed to VSS, first series connection n-channel MOS transistor 22 becomes conductive, and second series connection n-channel MOS transistor 23 becomes non-conductive.
In this way, the voltage of first node 91, that is, the gate voltage of first pull-down n-channel MOS transistor 21 is changed to VDD-Vtn.
Meanwhile, when the first control signal with a logic value of 1 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, first p-channel MOS transistor 25 becomes non-conductive.
Thus, in assist circuit 10A, once a logic value of 1 is input to terminal c0, that is, once the voltage of terminal c0 is changed to VDD, second series connection n-channel MOS transistor 23 becomes conductive, and the voltage of first node 91 is reset (changed to VSS). After that, the voltage of first node 91 will not be higher than VSS, that is, first pull-down n-channel MOS transistor 21 will not pull down the voltage of word line 20 in an active state to decrease the voltage.
As such, by controlling the first control signal, semiconductor memory device 1A configured as above can perform control as to whether to enable the function of decreasing the voltage of word line 20 in an active state (hereinafter, also referred to as an assist function).
This enables a user of semiconductor memory device 1A to evaluate the characteristics of memory cell 40 in a state in which the assist function is not enabled.
Moreover, this can make the user of semiconductor memory device 1A not enable the assist function when using semiconductor memory device 1A in a state of having relatively high read and write capability, such as when semiconductor memory device 1A is used with a relatively high power supply voltage.
Moreover, this makes it possible to relatively readily perform power supply cutoff control to suppress a leakage current.
Hereinafter, a semiconductor memory device according to Embodiment 3 is described which is configured by changing a part of the configuration of semiconductor memory device 1A according to Embodiment 2.
Here, constituent elements in the semiconductor memory device according to Embodiment 3 that are similar to those of semiconductor memory device 1A are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1A.
As illustrated in
Here, first control signal input terminal CNT0 is connected to all the gates of first series connection n-channel MOS transistor 22B (see
As illustrated in
A signal with the same logic (here, the same signal) as a signal to be input to the gate of second series connection n-channel MOS transistor 23 is input to the gate of first series connection n-channel MOS transistor 22B.
Moreover, the gate of first series connection n-channel MOS transistor 22B is connected to first control signal input terminal CNT0 via terminal sel0.
In assist circuit 10B configured as above, the drain of first series connection n-channel MOS transistor 22B (that is, second node 92B) is connected to a power supply line via first p-channel MOS transistor 25B.
Thus, when a first control signal with a logic value of 1 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, first series connection n-channel MOS transistor 22B becomes conductive. As such, in assist circuit 10B, when a logic value of 0 is input to terminal c0, that is, the voltage of terminal c0 is changed to VSS, first p-channel MOS transistor 25B becomes conductive, and second series connection n-channel MOS transistor 23 becomes non-conductive.
In this way, the voltage of first node 91, that is, the gate voltage of first pull-down n-channel MOS transistor 21 is changed to VDD-Vtn.
Meanwhile, when the first control signal with a logic value of 0 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, first series connection n-channel MOS transistor 22B becomes non-conductive.
Thus, in assist circuit 10B, once a logic value of 1 is input to terminal c0, that is, once the voltage of terminal c0 is changed to VDD, second series connection n-channel MOS transistor 23 becomes conductive, and the voltage of first node 91 is reset (changed to VSS). After that, the voltage of first node 91 will not be higher than VSS, that is, first pull-down n-channel MOS transistor 21 will not pull down the voltage of word line 20 in an active state to decrease the voltage.
As such, as with semiconductor memory device 1A according to Embodiment 2, semiconductor memory device 1B configured as above can perform control as to whether to enable the assist function, by controlling the first control signal.
Hereinafter, a semiconductor memory device according to Embodiment 4 is described which is configured by changing a part of the configuration of semiconductor memory device 1A according to Embodiment 2.
Here, constituent elements in the semiconductor memory device according to Embodiment 4 that are similar to those of semiconductor memory device 1A are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1A.
As illustrated in
That is, each of a plurality of assist circuits 10C is connected to two word lines 20. Thus, semiconductor memory device 1C includes assist circuits 10C whose number is half the number of word lines 20.
Here, first control signal input terminal CNT0 is connected to all the gates of first p-channel MOS transistors 25 (see
As illustrated in
Assist circuit 10C is configured by further adding, to assist circuit 10A, inverter 24C connected in order to input, to the gate of third series connection n-channel MOS transistor 22C, the inverse-logic signal of a signal to be input to the gate of fourth series connection n-channel MOS transistor 23C.
In assist circuit 10C configured as above, the drain of third series connection n-channel MOS transistor 22C is connected to a power supply line via first p-channel MOS transistors 25.
Thus, when a first control signal with a logic value of 0 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, first p-channel MOS transistor 25 becomes conductive. As such, in assist circuit 10C, when a logic value of 0 is input to terminal c1, that is, the voltage of terminal c1 is changed to VSS, third series connection n-channel MOS transistor 22C becomes conductive, and fourth series connection n-channel MOS transistor 23C becomes non-conductive.
In this way, the voltage of second node 91C, that is, the gate voltage of second pull-down n-channel MOS transistor 21C is changed to VDD-Vtn.
Meanwhile, when the first control signal with a logic value of 1 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, first p-channel MOS transistor 25 becomes non-conductive.
Thus, in assist circuit 10C, once a logic value of 1 is input to terminal c1, that is, once the voltage of terminal c1 is changed to VDD, fourth series connection n-channel MOS transistor 23C becomes conductive, and the voltage of second node 91C is reset (changed to VSS). After that, the voltage of second node 91C will not be higher than VSS, that is, second pull-down n-channel MOS transistor 21C will not pull down the voltage of word line 20WL1 in an active state to decrease the voltage.
As such, by controlling the first control signal, semiconductor memory device 1C configured as above can perform control as to whether to enable the assist function of word line 20 in an active state.
In assist circuit 10C configured as above, a p-channel MOS transistor positioned in the current path between the power supply line and first node 91 and a p-channel MOS transistor positioned in the current path between the power supply line and second node 91C can made as the common transistor, first p-channel MOS transistor 25.
In this way, it is possible to reduce the area for making the p-channel MOS transistor, in comparison with the case where the p-channel MOS transistor positioned in the current path between the power supply line and first node 91 and the p-channel MOS transistor positioned in the current path between the power supply line and second node 91C are made as separate transistors.
It should be noted that according to the descriptions in Embodiment 4, assist circuit 10C is configured by, for example, adding, to assist circuit 10A according to Embodiment 2, another circuit group of second pull-down n-channel MOS transistor 21C, third series connection n-channel MOS transistor 22C, fourth series connection n-channel MOS transistor 23C, and inverter 24C, and can perform control as to whether to enable the assist functions of two word lines 20 (word line 20WL0 and word line 20WL1) in an active state.
By contrast, as another configuration example, assist circuit 10C may be configured by adding, to assist circuit 10A according to Embodiment 2, N circuit groups each of which is the above-mentioned circuit group (where N is an integer greater than or equal to two), and assist circuit 10C may be able to perform control as to whether to enable the assist functions of at least N+1 word lines 20 in an active state.
In this case, semiconductor memory device 1C includes assist circuits 10C whose number is one/(N+1)th the number of word lines 20.
Hereinafter, a semiconductor memory device according to Embodiment 5 is described which is configured by changing a part of the configuration of semiconductor memory device 1A according to Embodiment 2.
Here, constituent elements in the semiconductor memory device according to Embodiment 5 that are similar to those of semiconductor memory device 1A are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1A.
As illustrated in
That is, each of a plurality of assist circuits 10D is connected to eight word lines 20. Thus, semiconductor memory device 1D includes assist circuits 10D whose number is one-eighth the number of word lines 20.
Here, first control signal input terminal CNT0 is connected to all the gates of first p-channel MOS transistors 25 (see
As illustrated in
Assist circuit 10D is configured by further making the following changes to assist circuit 10A: inverter 24 has been removed, and NAND circuit 26 and NAND circuit 26D have been added. NAND circuit 26 is connected in order to input, to the gate of first series connection n-channel MOS transistor 22, the inverse-logic signal of a signal to be input to the gate of second series connection n-channel MOS transistor 23 when word line 20WL0, word line 20WL1, word line 20WL2, and/or word line WL3 is active (here, when signal with a logic value of 1 is input to terminal Rdec0). NAND circuit 26D is connected in order to input, to the gate of third series connection n-channel MOS transistor 22D, the inverse-logic signal of a signal to be input to the gate of fourth series connection n-channel MOS transistor 23D when word line 20WL4, word line 20WL5, word line 20WL6, and/or word line WL7 is active (here, when a signal with a logic value of 1 is input to terminal Rdec1).
In assist circuit 10D configured as above, the drain of first series connection n-channel MOS transistor 22 is connected to a power supply line via first p-channel MOS transistor 25.
Thus, in a state where a signal with a logic value of 0 has been input by terminal Rdec0, that is, in a state where the voltage of terminal Rdec0 is VSS, when a first control signal with a logic value of 0 is input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, first p-channel MOS transistor 25 becomes conductive. As such, in assist circuit 10D, when a logic value of 0 is input to terminal c0, that is, when the voltage of terminal c0 is changed to VSS, first series connection n-channel MOS transistor 22 becomes conductive, and second series connection n-channel MOS transistor 23 becomes non-conductive.
In this way, the voltage of first node 91, that is, the gate voltages of first pull-down n-channel MOS transistor 21, second pull-down n-channel MOS transistor 21D1, third pull-down n-channel MOS transistor 21D2, and fourth pull-down n-channel MOS transistor 21D3 are changed to VDD-Vtn.
Meanwhile, when the first control signal with a logic value of 1 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, first p-channel MOS transistor 25 becomes non-conductive.
Thus, in assist circuit 10D, once a logic value of 1 is input to terminal c0, that is, once the voltage of terminal c0 is changed to VDD, second series connection n-channel MOS transistor 23 becomes conductive, and the voltage of first node 91 is reset (changed to VSS). After that, the voltage of first node 91 will not be higher than VSS, that is, each of first pull-down n-channel MOS transistor 21, second pull-down n-channel MOS transistor 21D1, third pull-down n-channel MOS transistor 21D2, and fourth pull-down n-channel MOS transistor 21D3 will not pull down the voltage of a corresponding one of word line 20WL0, word line 20WL1, word line 20WL2, and word line 20WL3 in an active state to decrease the voltage.
Moreover, in a state where a signal with a logic value of 0 has been input by terminal Rdec1, that is, in a state where the voltage of terminal Rdec1 is VSS, when the first control signal with a logic value of 0 is input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, first p-channel MOS transistor 25 becomes conductive. As such, in assist circuit 10D, when a logic value of 0 is input to terminal c0, that is, when the voltage of terminal c0 is changed to VSS, third series connection n-channel MOS transistor 22D becomes conductive, and fourth series connection n-channel MOS transistor 23D becomes non-conductive.
In this way, the voltage of second node 91D, that is, the gate voltages of fifth pull-down n-channel MOS transistor 21D4, sixth pull-down n-channel MOS transistor 21D5, seventh pull-down n-channel MOS transistor 21D6, and eighth pull-down n-channel MOS transistor 21D7 are changed to VDD-Vtn.
Meanwhile, when the first control signal with a logic value of 1 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, first p-channel MOS transistor 25 becomes non-conductive.
Thus, in assist circuit 10D, once a logic value of 1 is input to terminal c0, that is, once the voltage of terminal c0 is changed to VDD, fourth series connection n-channel MOS transistor 23D becomes conductive, and the voltage of second node 91D is reset (changed to VSS). After that, the voltage of second node 91D will not be higher than VSS, that is, each of fifth pull-down n-channel MOS transistor 21D4, sixth pull-down n-channel MOS transistor 21D5, seventh pull-down n-channel MOS transistor 21D6, and eighth pull-down n-channel MOS transistor 21D7 will not pull down the voltage of a corresponding one of word line 20WL4, word line 20WL5, word line 20WL6, and word line 20WL7 in an active state to decrease the voltage.
As such, by controlling the first control signal, semiconductor memory device 1D configured as above can perform control as to whether to enable the assist function of word line 20 in an active state.
In assist circuit 10D configured as above, a p-channel MOS transistor positioned in the current path between the power supply line and first node 91 and a p-channel MOS transistor positioned in the current path between the power supply line and second node 91D can made as the common transistor, first p-channel MOS transistor 25.
In this way, it is possible to reduce the area for making the p-channel MOS transistor, in comparison with the case where the p-channel MOS transistor positioned in the current path between the power supply line and first node 91 and the p-channel MOS transistor positioned in the current path between the power supply line and second node 91D are made as separate transistors.
Furthermore, in assist circuit 10D configured as above, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of first pull-down n-channel MOS transistor 21, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of second pull-down n-channel MOS transistor 21D1, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of third pull-down n-channel MOS transistor 21D2, and an n-channel MOS transistor positioned in the current path between the power supply line and the gate of fourth pull-down n-channel MOS transistor 21D3 can be made as the common transistor, first series connection n-channel MOS transistor 22. In addition, an n-channel MOS transistor positioned in the current path between ground line and the gate of first pull-down n-channel MOS transistor 21, an n-channel MOS transistor positioned in the current path between the ground line and the gate of second pull-down n-channel MOS transistor 21D1, an n-channel MOS transistor positioned in the current path between the ground line and the gate of third pull-down n-channel MOS transistor 21D2, and an n-channel MOS transistor positioned in the current path between the ground line and the gate of fourth pull-down n-channel MOS transistor 21D3 can be made as the common transistor, second series connection n-channel MOS transistor 23.
In this way, it is possible to reduce the area for making the n-channel MOS transistor(s), in comparison with the case where the n-channel MOS transistor positioned in the current path between the power supply line and the gate of first pull-down n-channel MOS transistor 21, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of second pull-down n-channel MOS transistor 21D1, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of third pull-down n-channel MOS transistor 21D2, and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of fourth pull-down n-channel MOS transistor 21D3 are made as separate transistors and/or the case where the n-channel MOS transistor positioned in the current path between the ground line and the gate of first pull-down n-channel MOS transistor 21, the n-channel MOS transistor positioned in the current path between the ground line and the gate of second pull-down n-channel MOS transistor 21D1, the n-channel MOS transistor positioned in the current path between the ground line and the gate of third pull-down n-channel MOS transistor 21D2, and the n-channel MOS transistor positioned in the current path between the ground line and the gate of fourth pull-down n-channel MOS transistor 21D3 are made as separate transistors.
Furthermore, in assist circuit 10D configured as above, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of fifth pull-down n-channel MOS transistor 21D4, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of sixth pull-down n-channel MOS transistor 21D5, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of seventh pull-down n-channel MOS transistor 21D6, and an n-channel MOS transistor positioned in the current path between the power supply line and the gate of eighth pull-down n-channel MOS transistor 21D7 can be made as the common transistor, third series connection n-channel MOS transistor 22D. In addition, an n-channel MOS transistor positioned in the current path between the ground line and the gate of fifth pull-down n-channel MOS transistor 21D4, an n-channel MOS transistor positioned in the current path between the ground line and the gate of sixth pull-down n-channel MOS transistor 21D5, an n-channel MOS transistor positioned in the current path between the ground line and the gate of seventh pull-down n-channel MOS transistor 21D6, and an n-channel MOS transistor positioned in the current path between the ground line and the gate of eighth pull-down n-channel MOS transistor 21D7 can be made as the common transistor, fourth series connection n-channel MOS transistor 23D.
In this way, it is possible to reduce the area for making the n-channel MOS transistor(s), in comparison with the case where the n-channel MOS transistor positioned in the current path between the power supply line and the gate of fifth pull-down n-channel MOS transistor 21D4, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of sixth pull-down n-channel MOS transistor 21D5, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of seventh pull-down n-channel MOS transistor 21D6, and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of eighth pull-down n-channel MOS transistor 21D7 are made as separate transistors and/or the case where the n-channel MOS transistor positioned in the current path between the ground line and the gate of fifth pull-down n-channel MOS transistor 21D4, the n-channel MOS transistor positioned in the current path between the ground line and the gate of sixth pull-down n-channel MOS transistor 21D5, the n-channel MOS transistor positioned in the current path between the ground line and the gate of seventh pull-down n-channel MOS transistor 21D6, and the n-channel MOS transistor positioned in the current path between the ground line and the gate of eighth pull-down n-channel MOS transistor 21D7 are made as separate transistors.
It should be noted that according to the descriptions in Embodiment 5, regarding assist circuit 10D, a number of M that is the number of pull-down n-channel MOS transistors whose gates are connected to first node 91 is four, and a number of M that is the number of n-channel MOS transistors connected to second node 91D is four.
By contrast, in another configuration example, M may be an integer greater than or equal to two except for four.
In this case, semiconductor memory device 1D includes assist circuits 10D whose number is one-2Mth the number of word lines 20.
Hereinafter, a semiconductor memory device according to Embodiment 6 is described which is configured by changing a part of the configuration of semiconductor memory device 1A according to Embodiment 2.
Here, constituent elements in the semiconductor memory device according to Embodiment 6 that are similar to those of semiconductor memory device 1A are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1A.
As illustrated in
That is, each of a plurality of assist circuits 10E is connected to four word lines 20. Thus, semiconductor memory device 1E includes assist circuits 10E whose number is one-fourth the number of word lines 20.
Here, first control signal input terminal CNT0 is connected to all the gates of first p-channel MOS transistors 25 (see
As illustrated in
In assist circuit 10E configured as above, the drain of first series connection n-channel MOS transistor 22 is connected to a power supply line via first p-channel MOS transistor 25.
Thus, when a first control signal with a logic value of 0 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, first p-channel MOS transistor 25 becomes conductive. As such, in assist circuit 10E, when a logic value of 0 is input to terminal c0, that is, the voltage of terminal c0 is changed to VSS, first series connection n-channel MOS transistor 22 becomes conductive, and second series connection n-channel MOS transistor 23 becomes non-conductive.
In this way, the voltage of first node 91, that is, the gate voltages of first pull-down n-channel MOS transistor 21, second pull-down n-channel MOS transistor 21E1, third pull-down n-channel MOS transistor 21E2, and fourth pull-down n-channel MOS transistor 21E3 are changed to VDD-Vtn.
Meanwhile, when the first control signal with a logic value of 1 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, first p-channel MOS transistor 25 becomes non-conductive.
Thus, in assist circuit 10E, once a logic value of 1 is input to terminal c0, that is, once the voltage of terminal c0 is changed to VDD, second series connection n-channel MOS transistor 23 becomes conductive, and the voltage of first node 91 is reset (changed to VSS). After that, the voltage of first node 91 will not be higher than VSS, that is, each of first pull-down n-channel MOS transistor 21, second pull-down n-channel MOS transistor 21E1, third pull-down n-channel MOS transistor 21E2, and fourth pull-down n-channel MOS transistor 21E3 will not pull down the voltage of a corresponding one of word line 20WL0, word line 20WL1, word line 20WL2, and word line 20WL3 in an active state to decrease the voltage.
As such, by controlling the first control signal, semiconductor memory device 1E configured as above can perform control as to whether to enable the assist function of word line 20 in an active state.
In assist circuit 10E configured as above, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of first pull-down n-channel MOS transistor 21, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of second pull-down n-channel MOS transistor 21E1, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of third pull-down n-channel MOS transistor 21E2, and an n-channel MOS transistor positioned in the current path between the power supply line and the gate of fourth pull-down n-channel MOS transistor 21E3 can be made as the common transistor, first series connection n-channel MOS transistor 22. In addition, an n-channel MOS transistor positioned in the current path between the ground line and the gate of first pull-down n-channel MOS transistor 21, an n-channel MOS transistor positioned in the current path between the ground line and the gate of second pull-down n-channel MOS transistor 21E1, an n-channel MOS transistor positioned in the current path between the ground line and the gate of third pull-down n-channel MOS transistor 21E2, and an n-channel MOS transistor positioned in the current path between the ground line and the gate of fourth pull-down n-channel MOS transistor 21E3 can be made as the common transistor, second series connection n-channel MOS transistor 23.
Thus, it is possible to increase the size of first series connection n-channel MOS transistor 22, in comparison with the case where the n-channel MOS transistor positioned in the current path between the power supply line and the gate of first pull-down n-channel MOS transistor 21, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of second pull-down n-channel MOS transistor 21E1, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of third pull-down n-channel MOS transistor 21E2, and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of fourth pull-down n-channel MOS transistor 21E3 are made as separate transistors.
In this way, it is possible to suppress variations in Vtn of first series connection n-channel MOS transistor 22.
It should be noted that according to the descriptions in Embodiment 6, regarding assist circuit 10E, a number of M that is the number of pull-down n-channel MOS transistors whose gates are connected to first node 91 is four.
By contrast, in another configuration example, M may be an integer greater than or equal to two except for four.
In this case, semiconductor memory device 1E includes assist circuits 10E whose number is one-Mth the number of word lines 20.
Hereinafter, a semiconductor memory device according to Embodiment 7 is described which is configured by changing a part of the configuration of semiconductor memory device 1A according to Embodiment 2.
Here, constituent elements in the semiconductor memory device according to Embodiment 7 that are similar to those of semiconductor memory device 1A are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1A.
As illustrated in
Here, first control signal input terminal CNT0 is connected to all the gates of first p-channel MOS transistors 25 (see
As illustrated in
In assist circuit 10F configured as above, the voltage of word line 20 is pulled down by first pull-down n-channel MOS transistor 21 whose gate voltage is VDD-Vtn and second pull-down n-channel MOS transistor 21F whose gate voltage is VDD.
In
As illustrated in
As such, semiconductor memory device 1F configured as above can control the voltage drop of word line 20 more sensitively.
Hereinafter, a semiconductor memory device according to Embodiment 8 is described which is configured by changing a part of the configuration of semiconductor memory device 1A according to Embodiment 2.
Here, constituent elements in the semiconductor memory device according to Embodiment 8 that are similar to those of semiconductor memory device 1A are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1A.
As illustrated in
Here, first control signal input terminal CNT0 is connected to all the gates of first p-channel MOS transistors 25 (see
As illustrated in
Here, the threshold of first series connection n-channel MOS transistor 22G is lower than the threshold of first pull-down n-channel MOS transistor 21 and the threshold of second series connection n-channel MOS transistor 23.
In semiconductor memory device 1G configured as above, when a power supply voltage is set to a low voltage, the gate voltage of first pull-down n-channel MOS transistor 21 will be lower than the threshold voltage of first pull-down n-channel MOS transistor 21. As a result, an occurrence of inconvenience of first pull-down n-channel MOS transistor 21 not being able to pull down word line 20 can be suppressed.
Thus, in semiconductor memory device 1G configured as above, it is possible to expand a low-voltage operation area for the pull-down operation of word line 20.
Hereinafter, a semiconductor memory device according to Embodiment 9 is described which is configured by changing a part of the configuration of semiconductor memory device 1A according to Embodiment 2.
Here, constituent elements in the semiconductor memory device according to Embodiment 9 that are similar to those of semiconductor memory device 1A are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1A.
As illustrated in
Here, first control signal input terminal CNT0 is connected to all the gates of first p-channel MOS transistors 25 (see
As illustrated in
Moreover, the gate of second p-channel MOS transistors 25H is connected to second control signal input terminal CNT1 via terminal sell.
By controlling a first control signal, semiconductor memory device 1H configured as above can perform control as to whether to enable an assist function using first pull-down n-channel MOS transistor 21. By controlling a second control signal, semiconductor memory device 1H configured as above can perform control as to whether to enable an assist function using second pull-down n-channel MOS transistor 21H.
In this way, semiconductor memory device 1H configured as above can select from among the choices: (1) pulling down word line 20 by using first pull-down n-channel MOS transistor 21, (2) pulling down word line 20 by using second pull-down n-channel MOS transistor 21H, (3) pulling down word line 20 by using first pull-down n-channel MOS transistor 21 and second pull-down n-channel MOS transistor 21H, and (4) not pulling down word line 20.
Hereinafter, a semiconductor memory device according to Embodiment 10 is described which is configured by changing a part of the configuration of semiconductor memory device 1B according to Embodiment 3.
Here, constituent elements in the semiconductor memory device according to Embodiment 10 that are similar to those of semiconductor memory device 1B are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1B.
As illustrated in
That is, each of a plurality of assist circuits 10J is connected to four word lines 20. Thus, semiconductor memory device 1J includes assist circuits 10J whose number is one-fourth the number of word lines 20.
Here, first control signal input terminal CNT0 is connected to all the gates of first series connection n-channel MOS transistor 22B (see
As illustrated in
In assist circuit 10J configured as above, the drain of first series connection n-channel MOS transistor 22B (that is, second node 92B) is connected to a power supply line via first p-channel MOS transistor 25B.
Thus, when a first control signal with a logic value of 1 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VDD, first series connection n-channel MOS transistor 22B becomes conductive. As such, in assist circuit 10J, when a logic value of 0 is input to terminal c0, that is, the voltage of terminal c0 is changed to VSS, first p-channel MOS transistor 25B becomes conductive, and second series connection n-channel MOS transistor 23 becomes non-conductive.
In this way, the voltage of first node 91, that is, the gate voltage of first pull-down n-channel MOS transistor 21 is changed to VDD-Vtn.
Meanwhile, when the first control signal with a logic value of 0 has been input by first control signal input terminal CNT0, that is, when the voltage of terminal sel0 is VSS, first series connection n-channel MOS transistor 22B becomes non-conductive.
Thus, in assist circuit 10J, once a logic value of 1 is input to terminal c0, that is, once the voltage of terminal c0 is changed to VDD, second series connection n-channel MOS transistor 23 becomes conductive, and the voltage of first node 91 is reset (changed to VSS). After that, the voltage of first node 91 will not be higher than VSS, that is, each of first pull-down n-channel MOS transistor 21, second pull-down n-channel MOS transistor 21J1, third pull-down n-channel MOS transistor 21J2, and fourth pull-down n-channel MOS transistor 21J3 will not pull down the voltage of a corresponding one of word line 20WL0, word line 20WL1, word line 20WL2, and word line 20WL3 in an active state to decrease the voltage.
As such, by controlling the first control signal, semiconductor memory device 1J configured as above can perform control as to whether to enable the assist function of word line 20 in an active state.
In assist circuit 10J configured as above, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of first pull-down n-channel MOS transistor 21, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of second pull-down n-channel MOS transistor 21J1, an n-channel MOS transistor positioned in the current path between the power supply line and the gate of third pull-down n-channel MOS transistor 21J2, and an n-channel MOS transistor positioned in the current path between the power supply line and the gate of fourth pull-down n-channel MOS transistor 21J3 can be made as the common transistor, first series connection n-channel MOS transistor 22B. In addition, an n-channel MOS transistor positioned in the current path between the ground line and the gate of first pull-down n-channel MOS transistor 21, an n-channel MOS transistor positioned in the current path between the ground line and the gate of second pull-down n-channel MOS transistor 21J1, an n-channel MOS transistor positioned in the current path between the ground line and the gate of third pull-down n-channel MOS transistor 21J2, and an n-channel MOS transistor positioned in the current path between the ground line and the gate of fourth pull-down n-channel MOS transistor 21J3 can be made as the common transistor, second series connection n-channel MOS transistor 23.
Thus, it is possible to increase the size of first series connection n-channel MOS transistor 22B, in comparison with the case where the n-channel MOS transistor positioned in the current path between the power supply line and the gate of first pull-down n-channel MOS transistor 21, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of second pull-down n-channel MOS transistor 21J1, the n-channel MOS transistor positioned in the current path between the power supply line and the gate of third pull-down n-channel MOS transistor 21J2, and the n-channel MOS transistor positioned in the current path between the power supply line and the gate of fourth pull-down n-channel MOS transistor 21J3 are made as separate transistors.
Thus, it is possible to suppress variations in Vtn of first series connection n-channel MOS transistor 22B.
It should be noted that according to the descriptions in Embodiment 10, regarding assist circuit 10J, a number of M that is the number of pull-down n-channel MOS transistors whose gates are connected to first node 91 is four.
By contrast, in another configuration example, M may be an integer greater than or equal to two except for four.
In this case, semiconductor memory device 1J includes assist circuits 10J whose number is one-Mth the number of word lines 20.
Hereinafter, a semiconductor memory device according to Embodiment 11 is described which is configured by changing a part of the configuration of semiconductor memory device 1B according to Embodiment 3.
Here, constituent elements in the semiconductor memory device according to Embodiment 11 that are similar to those of semiconductor memory device 1B are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1B.
As illustrated in
Here, first control signal input terminal CNT0 is connected to all the gates of first series connection n-channel MOS transistor 22B (see
As illustrated in
In assist circuit 10K configured as above, the voltage of word line 20 is pulled down by first pull-down n-channel MOS transistor 21 whose gate voltage is VDD-Vtn and second pull-down n-channel MOS transistor 21K whose gate voltage is VDD.
In
As illustrated in
As such, semiconductor memory device 1K configured as above can control the voltage drop of word line 20 more sensitively.
Hereinafter, a semiconductor memory device according to Embodiment 12 is described which is configured by changing a part of the configuration of semiconductor memory device 1B according to Embodiment 3.
Here, constituent elements in the semiconductor memory device according to Embodiment 12 that are similar to those of semiconductor memory device 1B are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1B.
As illustrated in
Here, first control signal input terminal CNT0 is connected to all the gates of first series connection n-channel MOS transistor 22L (see
As illustrated in
Here, the threshold of first series connection n-channel MOS transistor 22L is lower than the threshold of first pull-down n-channel MOS transistor 21 and the threshold of second series connection n-channel MOS transistor 23.
In semiconductor memory device 1L configured as above, when a power supply voltage is set to a low voltage, the gate voltage of first pull-down n-channel MOS transistor 21 will be lower than the threshold voltage of first pull-down n-channel MOS transistor 21. As a result, an occurrence of inconvenience of first pull-down n-channel MOS transistor 21 not being able to pull down word line 20 is suppressed.
Thus, in semiconductor memory device 1L configured as above, it is possible to expand a low-voltage operation area for the pull-down operation of word line 20.
Hereinafter, a semiconductor memory device according to Embodiment 13 is described which is configured by changing a part of the configuration of semiconductor memory device 1B according to Embodiment 3.
Here, constituent elements in the semiconductor memory device according to Embodiment 13 that are similar to those of semiconductor memory device 1B are assigned the same reference signs as those already described, and detailed descriptions thereof will be omitted, with the descriptions focusing on the differences from semiconductor memory device 1B.
As illustrated in
Here, first control signal input terminal CNT0 is connected to all the gates of first series connection n-channel MOS transistor 22B (see
As illustrated in
Moreover, the gate of third series connection n-channel MOS transistor 22M is connected to second control signal input terminal CNT1 via terminal sell.
By controlling a first control signal, semiconductor memory device 1M configured as above can perform control as to whether to enable an assist function using first pull-down n-channel MOS transistor 21. By controlling a second control signal, semiconductor memory device 1M configured as above can perform control as to whether to enable an assist function using second pull-down n-channel MOS transistor 21M.
In this way, semiconductor memory device 1M configured as above can select from among the choices: (1) pulling down word line 20 by using first pull-down n-channel MOS transistor 21, (2) pulling down word line 20 by using second pull-down n-channel MOS transistor 21M, (3) pulling down word line 20 by using first pull-down n-channel MOS transistor 21 and second pull-down n-channel MOS transistor 21M, and (4) not pulling down word line 20.
As described above, exemplifications of the techniques disclosed in the present application are described on the basis of Embodiments 1 to 13. However, the present disclosure is not limited to the embodiments. The scope of one or more aspects of the present disclosure may also encompass embodiments obtained by adding, to the embodiment, various modifications envisioned by those skilled in the art, and embodiments obtained by combining elements in different embodiments or variations, as long as the resultant embodiments do not depart from the scope of the present disclosure.
Although only some exemplary embodiments of the present disclosure have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure.
The present disclosure is widely applicable to semiconductor memory devices.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-148483 | Sep 2022 | JP | national |
This is a continuation application of PCT International Application No. PCT/JP2023/031714 filed on Aug. 31, 2023, designating the United States of America, which is based on and claims priority of Japanese Patent Application No. 2022-148483 filed on Sep. 16, 2022. The entire disclosures of the above-identified applications, including the specifications, drawings and claims are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/031714 | Aug 2023 | WO |
| Child | 19050828 | US |
