Address circuits

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G11C11/418

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GPHYSICS G11Information storage G11CSTATIC STORES G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

Current Industry

G11C11/418Address circuits

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Column multiplexer circuitry
- Patent number 12,230,317
- Issue date Feb 18, 2025
- ARM Limited
- Lalit Gupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Modular memory architecture with more significant bit sub-array wor...
- Patent number 12,210,754
- Issue date Jan 28, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing control circuit of memory device with tracking word line and...
- Patent number 12,198,754
- Issue date Jan 14, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Xiu-Li Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with signal edge sharpener circuitry
- Patent number 12,190,944
- Issue date Jan 7, 2025
- Taiwain Semiconductor Manufacturing Company, Ltd.
- Atul Katoch
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 12,193,206
- Issue date Jan 7, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Xiu-Li Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM power-up random number generator
- Patent number 12,190,945
- Issue date Jan 7, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jui-Che Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared decoder circuit and method
- Patent number 12,183,432
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- XiuLi Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed multi-port memory supporting collision
- Patent number 12,183,393
- Issue date Dec 31, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive body bias management for an in-memory compute operation wh...
- Patent number 12,176,025
- Issue date Dec 24, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
PUF generators based on SRAM bit cells
- Patent number 12,177,370
- Issue date Dec 24, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Cormac Michael O'Connell
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry for power management assertion
- Patent number 12,170,108
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic bistable circuit with third voltage to retain memory data
- Patent number 12,165,697
- Issue date Dec 10, 2024
- Japan Science and Technology Agency
- Satoshi Sugahara
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM power savings and write assist
- Patent number 12,165,700
- Issue date Dec 10, 2024
- Advanced Micro Devices, Inc.
- Russell J. Schreiber
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with fast, controlled peak current, power efficient array rese...
- Patent number 12,159,689
- Issue date Dec 3, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Praveen Kumar Verma
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared bit lines for memory cells
- Patent number 12,160,985
- Issue date Dec 3, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ping-Wei Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Current leakage management controller for reading from memory cells
- Patent number 12,148,464
- Issue date Nov 19, 2024
- Xilinx, Inc.
- Michael Tsivyan
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed synchronous write-through operation for testing two-port m...
- Patent number 12,148,490
- Issue date Nov 19, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Device signature based on trim and redundancy information
- Patent number 12,149,643
- Issue date Nov 19, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Katherine H. Chiang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with selective precharging
- Patent number 12,142,346
- Issue date Nov 12, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ed McCombs
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having a comparator circuit
- Patent number 12,136,454
- Issue date Nov 5, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Jaspal Singh Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic device for configuring neural network
- Patent number 12,125,524
- Issue date Oct 22, 2024
- Samsung Electronics Co., Ltd.
- Jinseok Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method of operating the same
- Patent number 12,125,525
- Issue date Oct 22, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Tsung-Hsien Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable delay word line enable
- Patent number 12,119,050
- Issue date Oct 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hyunsung Hong
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage memory device
- Patent number 12,119,052
- Issue date Oct 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahmut Sinangil
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and word line driver
- Patent number 12,112,796
- Issue date Oct 8, 2024
- Taiwan Semiconductor Manufacturing Company Ltd.
- Zhi-Hao Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device including predecoder and operating method thereof
- Patent number 12,112,795
- Issue date Oct 8, 2024
- Samsung Electronics Co., Ltd.
- Kyu Won Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive word line control circuit
- Patent number 12,106,800
- Issue date Oct 1, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chien-Chen Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Reconfigurable data processing and storage unit for deep neural net...
- Patent number 12,094,527
- Issue date Sep 17, 2024
- International Business Machines Corporation
- Rajiv Joshi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with double redundancy
- Patent number 12,094,528
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Dhvani Sheth
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial word line actuation with linked source voltage supply modula...
- Patent number 12,087,356
- Issue date Sep 10, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Circuitry for Power Management Assertion
- Publication number 20250061941
- Publication date Feb 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sanjeev Kumar Jain
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICOND...
- Publication number 20250056813
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Seulji Song
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...
- Publication number 20250054529
- Publication date Feb 13, 2025
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...
- Publication number 20250054528
- Publication date Feb 13, 2025
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
PULSE GENERATOR AND MEMORY DEVICE COMPRISING THE SAME
- Publication number 20250046366
- Publication date Feb 6, 2025
- Samsung Electronics Co., Ltd.
- Kiryong KIM
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC CIRCUIT
- Publication number 20250046365
- Publication date Feb 6, 2025
- Japan Science and Technology Agency
- Satoshi Sugahara
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE FOR CONFIGURING NEURAL NETWORK
- Publication number 20250014638
- Publication date Jan 9, 2025
- Samsung Electronics Co., Ltd.
- Jinseok KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF M...
- Publication number 20250014614
- Publication date Jan 9, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Hsin Nien
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT AND METHOD OF OPERATING SAME
- Publication number 20250006255
- Publication date Jan 2, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Luping KONG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD OF OPERATING THE SAME
- Publication number 20250006256
- Publication date Jan 2, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tsung-Hsien Huang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20240420760
- Publication date Dec 19, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Lien Linus LU
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-CHARGE SYSTEM FOR PERFORMING TIME-DIVISION PRE-CHARGE UPON BIT-...
- Publication number 20240412779
- Publication date Dec 12, 2024
- MEDIATEK INC.
- Yi-Te Chiu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE INCLUDING BOOSTER CIRCUIT FOR TRACKING WORD LINE
- Publication number 20240395318
- Publication date Nov 28, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hyunsung Hong
- G11 - INFORMATION STORAGE
Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20240395319
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE SIGNATURE BASED ON TRIM AND REDUNDANCY INFORMATION
- Publication number 20240396749
- Publication date Nov 28, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Katherine H. CHIANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND MANUFACTURING THEREOF
- Publication number 20240397695
- Publication date Nov 28, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jhon Jhy LIAW
- G11 - INFORMATION STORAGE
Information Patent Application
WORD LINE BOOSTER CELL AND MEMORY ARRAY
- Publication number 20240395317
- Publication date Nov 28, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hyunsung HONG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH DOUBLE REDUNDANCY
- Publication number 20240395320
- Publication date Nov 28, 2024
- QUALCOMM Incorporated
- Dhvani SHETH
- G11 - INFORMATION STORAGE
Information Patent Application
EMBEDDED MEMORY DEVICE AND OPERATING METHOD THEREOF
- Publication number 20240386946
- Publication date Nov 21, 2024
- Samsung Electronics Co., Ltd.
- Hyunjun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING A COMPARATOR CIRCUIT
- Publication number 20240386948
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaspal Singh SHAH
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WORD LINE CONTROL CIRCUIT
- Publication number 20240386947
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chien-Chen Lin
- G11 - INFORMATION STORAGE
Information Patent Application
TRACKING WORST CASE MEMORY CELLS BY SUPPRESSING TRACKING WORDLINE V...
- Publication number 20240379154
- Publication date Nov 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yumito Aoyagi
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT AND WORD LINE DRIVER
- Publication number 20240371435
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- ZHI-HAO CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ARRAY AND METHOD OF OPERATING SAME
- Publication number 20240371853
- Publication date Nov 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shih-Lien Linus LU
- G11 - INFORMATION STORAGE
Information Patent Application
LOW CONTENTION CURRENT CIRCUITS
- Publication number 20240356552
- Publication date Oct 24, 2024
- Intel Corporation
- Steven Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT CELL BASED WRITE SELF-TIME DELAY PATH
- Publication number 20240331767
- Publication date Oct 3, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM
- Publication number 20240331768
- Publication date Oct 3, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNIN...
- Publication number 20240312493
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- Youngrok PARK
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY
- Publication number 20240296883
- Publication date Sep 5, 2024
- FLASHSILICON INCORPORATION
- Lee Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Circuitry for Memory Applications
- Publication number 20240290363
- Publication date Aug 29, 2024
- ARM Limited
- Rahul Mathur
- G11 - INFORMATION STORAGE

Address circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Column multiplexer circuitry

Modular memory architecture with more significant bit sub-array wor...

Timing control circuit of memory device with tracking word line and...

Memory device with signal edge sharpener circuitry

Memory device

SRAM power-up random number generator

Shared decoder circuit and method

High-speed multi-port memory supporting collision

Adaptive body bias management for an in-memory compute operation wh...

PUF generators based on SRAM bit cells

Circuitry for power management assertion

Electronic bistable circuit with third voltage to retain memory data

SRAM power savings and write assist

SRAM with fast, controlled peak current, power efficient array rese...

Shared bit lines for memory cells

Current leakage management controller for reading from memory cells

At-speed synchronous write-through operation for testing two-port m...

Device signature based on trim and redundancy information

Memory device with selective precharging

Memory device having a comparator circuit

Electronic device for configuring neural network

Memory device and method of operating the same

Variable delay word line enable

Low voltage memory device

Memory circuit and word line driver

Memory device including predecoder and operating method thereof

Adaptive word line control circuit

Reconfigurable data processing and storage unit for deep neural net...

Memory with double redundancy

Serial word line actuation with linked source voltage supply modula...

Patents Applicationslast 30 patents

Circuitry for Power Management Assertion

SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICOND...

SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...

SRAM WITH FAST, CONTROLLED PEAK CURRENT, POWER EFFICIENT ARRAY RESE...

PULSE GENERATOR AND MEMORY DEVICE COMPRISING THE SAME

ELECTRONIC CIRCUIT

ELECTRONIC DEVICE FOR CONFIGURING NEURAL NETWORK

SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF M...

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

MEMORY DEVICE

PRE-CHARGE SYSTEM FOR PERFORMING TIME-DIVISION PRE-CHARGE UPON BIT-...

MEMORY DEVICE INCLUDING BOOSTER CIRCUIT FOR TRACKING WORD LINE

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

DEVICE SIGNATURE BASED ON TRIM AND REDUNDANCY INFORMATION

MEMORY DEVICE AND MANUFACTURING THEREOF

WORD LINE BOOSTER CELL AND MEMORY ARRAY

MEMORY WITH DOUBLE REDUNDANCY

EMBEDDED MEMORY DEVICE AND OPERATING METHOD THEREOF

MEMORY DEVICE HAVING A COMPARATOR CIRCUIT

ADAPTIVE WORD LINE CONTROL CIRCUIT

TRACKING WORST CASE MEMORY CELLS BY SUPPRESSING TRACKING WORDLINE V...

MEMORY CIRCUIT AND WORD LINE DRIVER

MEMORY CELL ARRAY AND METHOD OF OPERATING SAME

LOW CONTENTION CURRENT CIRCUITS

BIT CELL BASED WRITE SELF-TIME DELAY PATH

BITCELL PROCESS COMPENSATED READ ASSIST SCHEME FOR SRAM

INTEGRATED CIRCUIT INCLUDING BACKSIDE WIRING AND METHOD OF DESIGNIN...

OPERATION SCHEME FOR FOUR TRANSISTOR STATIC RANDOM ACCESS MEMORY

Clock Circuitry for Memory Applications