Semiconductor memory device

Abstract

Included are first and second inverters 1L, 1R, a first selection transistor N1 controlling a connection of an output terminal of the first inverter 1L to a bit line 11, and a second selection transistor N2 controlling a connection of an output terminal of the second inverter 1R to a bit line 12, wherein the first inverter 1L having a first load transistor P1 and a first drive transistor N3 and the second inverter 1R having a second load transistor P2 and a second drive transistor N4, function as a memory cell 1, and a ratio of a driving current quantity that can be outputted in an ON-state of the first drive transistor N3 to a driving current quantity that can be outputted in an ON-state of the first selection transistor N1, is larger than a first predetermined value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a configuration of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram of a layout of the cell array of the semiconductor memory device according to a second embodiment of the present invention;

FIG. 3A is a diagram showing a relationship between conventional row selection and column selection;

FIG. 3B is a diagram showing arrangement of the memory cells for reducing data inversion when reading;

FIG. 4 is a diagram of a configuration of the semiconductor memory device according to a third embodiment of the present invention.

Claims

1. A semiconductor memory device including a memory cell comprising: first and second inverters each having an output terminal that is mutually connected to an input terminal of said other first or second inverter;a first selection transistor controlling a connection of the output terminal of said first inverter to a bit line; anda second selection transistor controlling a connection of the output terminal of said second inverter to another bit line;wherein said first inverter includes a first load transistor connected to a power source and a first drive transistor connected to the power source via said first load transistor and switched over in its ON/OFF-states,wherein a common terminal between said first load transistor and said first drive transistor forms the output terminal of said first inverter, and a connection terminal connecting a gate of said first load transistor to a gate of said first drive transistor forms the input terminal of said first inverter,wherein said second inverter includes a second load transistor connected to the power source and a second drive transistor connected to the power source via said second load transistor and switched over in its ON/OFF-states,wherein a common terminal between said second load transistor and said second drive transistor forms the output terminal of said second inverter, and a connection terminal connecting a gate of said second load transistor to a gate of said second drive transistor forms the input terminal of said second inverter,wherein when said first inverter is switched ON, said second inverter is switched OFF, and, when said second inverter is switched ON, said first inverter is switched OFF, thus functioning as said memory cell,wherein when writing data to said memory cell, said first selection transistor and said second selection transistor are switched ON thereby to input the data to said second inverter as well as to said first inverter, and, when reading the data from said memory cell, said first selection transistor is switched ON, the data is read from said first inverter while said second selection transistor is switched OFF, andwherein a ratio of a driving current quantity that can be outputted in the ON-state of said first drive transistor to a driving current quantity that can be outputted in the ON-state of said first selection transistor, is larger than a first predetermined value.

2. A semiconductor memory device according to claim 1, wherein a ratio of a driving current quantity by which said second drive transistor can be driven in the ON-state thereof to a driving current quantity by which said second selection transistor can be driven in the ON-state thereof, is smaller than a second predetermined value.

3. A semiconductor memory device according to claim 1, said memory cells being accessed with row addresses and with column addresses and arrayed two-dimensionally, further comprising: a row selection circuit controlling said first selection transistor of said plurality of memory cells corresponding to any one of the row addresses; anda column selection circuit capable of selecting all of said memory cells selected by said row selection circuit among said memory cells corresponding to the respective column addresses.

4. A semiconductor memory device according to claim 1, wherein when said first inverter is provided with said first selection transistor by one, the first predetermined value is approximately “2”.

5. A semiconductor memory device according to claim 1, wherein when said first inverter is provided with said first selection transistors by two, the first predetermined value is approximately “4”.