Claims
- 1. A semiconductor memory comprising:a plurality of bit lines; a plurality of word lines; a plurality of memory cells; a row address decoder; a column address decoder including a pre-decoder and a shift register which uses an output signal of said pre-decoder as an initial value thereof; and a selector which selects one or more of said plurality of bit lines on the basis of output signals of said shift register, wherein said shift register forms a first continuous select signal corresponding to a sequential action and a second continuous select signal corresponding to an interleave action.
- 2. A synchronous dynamic memory comprising:a plurality of bit lines; a plurality of word lines; a plurality of memory cells; a row address decoder; a column address decoder including a pre-decoder and a shift register which receives an output signal of said pre-decoder; a selector which selects one or more of said plurality of bit lines on the basis of output signals of said shift register; and a mode register; wherein said shift register forms a first continuous select signal corresponding to a sequential action and a second continuous select signal corresponding to an interleave action, and wherein one of said sequential action and said interleave action is designated by said mode register.
- 3. A double data rate synchronous dynamic memory comprising:a plurality of bit lines; a plurality of word lines; a plurality of memory cells; a row address decoder; a column address decoder including a pre-decoder and a circuit which receives an output signal of said pre-decoder; a selector which selects one or more of said plurality of bit lines on the basis of output signals of said shift register; a mode register; and an address register which stores an address signal used for a write operation; wherein said circuit forms a first continuous select signal corresponding to a sequential action and a second continuous select signal corresponding to an interleave action, wherein one of said sequential action and said interleave action is designated by said mode register, and wherein said address signal, delayed by said address register, is supplied to said pre-decoder.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2000-046889 |
Feb 2000 |
JP |
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Parent Case Info
This is a continuation of parent application Ser. No. 09/789,753, filed Feb. 22, 2001, now U.S. Pat. No. 6,385,100, the entire disclosure of which is hereby incorporated by reference.
US Referenced Citations (8)
Foreign Referenced Citations (2)
Number |
Date |
Country |
6-275073 |
Sep 1994 |
JP |
9-320269 |
Dec 1997 |
JP |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/789753 |
Feb 2001 |
US |
Child |
10/097564 |
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US |