Claims
- 1. A semiconductor device, comprising: at least a lower interconnection layer containing diffusion layers formed at the surface of a Si substrate, an upper interconnection layer formed above said Si substrate through the intermediation of an interlayer dielectric layer, contact holes extending from said upper interconnection layer to said lower interconnection layer, and a conductor layer filling said contact holes,
- said upper interconnection layer consisting of an Al-involved interconnection layer,
- said conductor layer being made of an alloy consisting essentially of Al, Si and Ge, said alloy having a eutectic point lower than the eutectic point of Al-Si alloy.
- 2. A semiconductor device according to claim 1 wherein said Al-involved interconnection layer is made of an Al alloy having a eutectic point higher than the eutectic point of said Al alloy of which said conductor layer is made.
- 3. A semiconductor device according to claim 1, wherein the top face of said interlayer dielectric layer is substantially flat.
- 4. A semiconductor device according to claim 1, wherein said interlayer dielectric layer is substantially flat, and
- said Al-involved interconnection layer is made of said Al alloy of which said conductor layer is made.
- 5. A semiconductor device according to claim 1, wherein a conducting barrier film is provided at least in each region in the top face of said lower interconnection layer exposed through said contact holes.
- 6. A semiconductor device according to claim 5, wherein silicide layers are provided at least on the entire top faces of said diffusion layers.
- 7. A semiconductor device according to claim 6 wherein said barrier film is provided at least on the side faces of said interlayer dielectric layer exposed through said contact holes.
Priority Claims (2)
Number |
Date |
Country |
Kind |
2-328346 |
Nov 1990 |
JPX |
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2-328348 |
Nov 1990 |
JPX |
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BACKGROUND OF THE INVENTION
This application is a division of prior application Ser. No. 07/798,960, filed Nov. 27, 1991.
US Referenced Citations (5)
Foreign Referenced Citations (1)
Number |
Date |
Country |
54-41871 |
Dec 1979 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Planarized Aluminum Metallization for Sub-0.5 .mu.m CMOS Technology, 1990 IEEE, IEDM 90, pp. 51-54, by F. S. Chen, et al. |
Divisions (1)
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Number |
Date |
Country |
Parent |
798960 |
Nov 1991 |
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