Patent Application
20230360911
The present invention relates to a semiconductor laminate structure formed of a nitride semiconductor, a method of manufacturing the same, and a method of manufacturing a semiconductor device.
A heterojunction field effect transistor (HFET) and a high electron mobility transistor (HEMT) are transistors that perform ON/OFF by changing a carrier density of a channel layer by an electric field generated by a gate voltage. When GaN is used, a 2-dimensional electron gas (2DEG) formed by collecting electrons at an interface to compensate for a difference in magnitude of polarization between AlGaN and GaN at the time of lamination of AlGaN/GaN is used in many cases. In a general HEMT using GaN of a Ga polarity (Group III polarity), a gate electrode is formed on an AlGaN layer of about several nm to several tens of nm, and a 2DEG concentration at an AlGaN/GaN interface is controlled.
In the HEMT using GaN, a high frequency device is applied utilizing the high mobility of 2DEG. Here, in the HEMT of Ga polarity, AlGaN with a large band gap is disposed on a device surface. Therefore, this type of transistor has a problem that, first, contact resistance is high and, second, an AlGaN layer cannot be thinned for maintaining carrier density, which leads to a short channel effect.
This problem hinders an improvement in high frequency characteristics of an HEMT in which a nitride semiconductor such as GaN is used. In order to solve the above-described problem, techniques of, firstly, in order to reduce the contact resistance, the region directly under an ohmic electrode being regrown, and secondly, in order to inhibit a short channel effect, increasing an Al composition and thinning an AlGaN layer have been examined. However, there is a limitation on a reduction in the ohmic contact resistance.
The GaN layer of which a main surface has N polarity (Group V polarity) is a crystal layer obtained by inverting the GaN layer of which the main surface has Ga polarity and has the following three advantages when the HEMT is formed. First, an AlGaN layer, which requires a high Al composition and a thickness of about 20 nm to supply carriers and has high resistance, is located below the GaN channel layer and is not disposed between an electrode and a channel. Therefore, the contact resistance can be reduced.
Second, since the thickness of the GaN layer on the surface does not have a great influence on the carrier density, it is possible to reduce the thickness and inhibit the short channel effect.
Third, the AlGaN layer immediately below the channel serves as a back barrier, and thus the short channel effect can be inhibited.
From the viewpoint of these advantages, by producing an HEMT using an N-polar GaN layer, an improvement in high frequency characteristics of the HEMT can be expected (see Non Patent Literature 1).
As described above, it could be understood that an improvement in the high frequency characteristics of the HEMT can be expected by using a nitride semiconductor layer of which a main surface has N polarity (an N-polar nitride semiconductor layer), but the N-polar nitride semiconductor layer has a problem in crystal-growth.
It is known that the N-polar nitride semiconductor layer has a problem such as lower surface flatness and higher dislocation density than in a Ga-polar nitride semiconductor layer (see Non Patent Literature 2). There is also an example in which the foregoing problems have been solved to some extent by performing crystal-growth on a substrate with a large off angle to produce a transistor. In this case, however, it is known that a sheet resistance varies depending on a relationship between a direction of an off angle and a direction of a current flowing through a channel (see Non Patent Literature 3). Thus, a limitation is imposed on production of a device.
In order to avoid such a problem of crystal-growth in an N-polar nitride semiconductor, a technology in which a nitride semiconductor grown with Ga polarity is inverted and bonded to another substrate to expose an N-polar surface to produce a device has been examined (Non Patent Literature 4). In this technology, since a Group III nitride semiconductor that has a device structure with Ga polarity is grown, it can be expected that qualities specific to crystals such as dislocation density and anisotropy of sheet resistance will be equivalent to those of existing Ga polarity transistors.
Further, by using substrate transfer, it is possible to produce an HEMT formed of a high-quality N-polar nitride semiconductor on a substrate on which it is difficult to grow an N-polar nitride semiconductor. For example, it is difficult to realize crystal-growth of GaN on a Si substrate that has a main surface plane orientation as (100), which is used for CMOS production, but it is possible to form an N-polar GaN layer on a Si substrate by using the above-described substrate transfer technology. Accordingly, an HEMT and a CMOS that have excellent high-frequency characteristics can be integrated on the same substrate.
As described above, by forming an N-polar nitride layer on a Si substrate that has a plane orientation of the main surface as (100), production of a device in a CMOS process line in which a large-diameter Si substrate is used, integration with a CMOS circuit on the same substrate, and the like can be realized. For example, in a report, a resin or an oxide is used as an adhesive layer for bonding in substrate transfer. However, these adhesive layers cannot sufficiently draw out the characteristics of the device because of the characteristics of constituent materials.
For example, in Non Patent Literature 4, a Si substrate and a Group III nitride semiconductor epitaxial wafer are bonded by hydrogen silsesquioxane (HSQ). However, since HSQ only has heat resistance up to about 900° C., HSQ can withstand annealing of an ohmic electrode (about 850° C.), but a process exceeding 1000° C. cannot be performed after a bonding step. As a process in which a temperature exceeds 1000° C., for example, regrowth of GaN or etching in accordance with a selective thermal decomposition method can be considered. The regrowth of GaN is an important step of reducing contact resistance of a HEMT using an N-polar GaN layer, and a high temperature is necessary for high quality of the GaN crystal that is regrown. The selective thermal decomposition method is a method of etching GaN at high selectivity and is a step necessary for etching a thin film with good controllability.
In order to be able to carry out a high-temperature step, first, it is conceivable to perform direct bonding. In order to enable the high temperature process, second, a method of using an adhesive layer that can withstand higher temperatures is considered.
When direct bonding is used, inclusion of Ga in a nitride semiconductor layer in contact with a Si substrate may cause a problem at high temperatures. Ga and Si react at a high temperature, and GaN is etched by meltback etching. Accordingly, the nitride semiconductor layer containing Ga is likely to be peeled off from the Si substrate. When a device that includes the nitride semiconductor layer containing Ga is close to a substrate, it is conceivable that a layer in which the device is formed is etched and characteristics of the device considerably deteriorate.
On the other hand, there is a report that SiO2 is used as an adhesive layer that can withstand higher temperatures (Non Patent Literature 5). However, since SiO2 has a low thermal conductivity, heat dissipation of the device is greatly reduced, which is a limitation when high frequency characteristics of the HEMT need to be brought out.
As described above, the technology of the related art has a problem that a device that uses a nitride semiconductor containing Ga and has good characteristics cannot be formed on a Si layer of which a plane orientation of the main surface is (100).
Embodiments of the present invention have been made to solve the foregoing problems and an embodiment of the present invention is to enable to form a device that uses a nitride semiconductor containing Ga and has good characteristics on a Si layer having a plane orientation of a main surface as (100).
A method of manufacturing a semiconductor laminate structure according to embodiments of the present invention includes: a bonding step of bonding a substrate that has a main surface formed as a (100) plane of Si and another substrate that has a nitride semiconductor layer formed through crystal-growth of a nitride semiconductor containing Ga to each other in a +c-axis direction, in a state where a surface of the other substrate on which the nitride semiconductor layer is formed is on a side of the substrate; an adhesive layer forming step of forming an adhesive layer formed of AlN, on at least one of a surface of the substrate on a side bonded to the other substrate and a surface of the nitride semiconductor layer on a side bonded to the substrate, before the bonding step; and a removing step of removing the other substrate from the nitride semiconductor layer after the bonding step.
A method of manufacturing a semiconductor device according to embodiments of the present invention includes: a bonding step of bonding a substrate that has a main surface formed as a (100) plane of Si and another substrate that has a nitride semiconductor layer formed through crystal-growth of a nitride semiconductor containing Ga to each other in a +c-axis direction, in a state where a surface of the other substrate on which the nitride semiconductor layer is formed is on a side of the substrate; an adhesive layer forming step of forming an adhesive layer formed of AlN, on at least one of a surface of the substrate on a side bonded to the other substrate and a surface of the nitride semiconductor layer on a side bonded to the substrate, before the bonding step; a removing step of removing the other substrate from the nitride semiconductor layer after the bonding step; a first element forming step of forming a recess on the surface of the nitride semiconductor layer after the removing step; a second element forming step of selectively regrowing n-type GaN in the recess to form an n-GaN layer; and a third element forming step of forming an electrode in ohmic contact with the n-GaN layer.
A method of manufacturing a semiconductor device according to embodiments of the present invention includes: a bonding step of bonding a substrate that has a main surface formed as a (100) plane of Si and another substrate that has a nitride semiconductor layer formed through crystal-growth of a nitride semiconductor containing Ga to each other in a +c-axis direction, in a state where a surface of the other substrate on which the nitride semiconductor layer is formed is on a side of the substrate; an adhesive layer forming step of forming an adhesive layer formed of AlN, on at least one of a surface of the substrate on a side bonded to the other substrate and a surface of the nitride semiconductor layer on a side bonded to the substrate, before the bonding step; a first element forming step of forming an element formation layer through crystal-growth of a nitride semiconductor containing Ga in the +c-axis direction on the other substrate, forming an etching stop layer through crystal-growth of a nitride semiconductor containing Al and having a higher thermal decomposition temperature than that of GaN in the +c-axis direction on the element formation layer, subsequently forming a buffer layer through crystal-growth of a nitride semiconductor containing Ga on the etching stop layer, and forming the nitride semiconductor layer including the element formation layer, the etching stop layer, and the buffer layer, before the adhesive layer forming step before the bonding step; a removing step of removing the other substrate from the nitride semiconductor layer after the bonding step; and a second element forming step of selectively thermally decomposing the buffer layer with respect to the etching stop layer by heating in a hydrogen atmosphere containing ammonia to remove the buffer layer and expose the etching stop layer, after the removing step.
A semiconductor laminate structure according to embodiments of the present invention includes a substrate that has a main surface formed as a (100) plane of Si, an adhesive layer formed of AlN and formed on the substrate, and a nitride semiconductor layer formed of a nitride semiconductor containing Ga and formed on the adhesive layer.
As described above, according to embodiments of the present invention, since the substrate that has the main surface formed as the (boo) plane of Si and the other substrate on which the nitride semiconductor layer obtained through crystal-growth of the nitride semiconductor containing Ga in the +c-axis direction is formed are bonded together via the adhesive layer formed of AlN, it is possible to form a device having good characteristics using the nitride semiconductor containing Ga on the layer of Si having the plane orientation of the main surface as (100).
First, a method of manufacturing a semiconductor laminate structure according to a first embodiment of the present invention will be described with reference to
First, as illustrated in
Next, as illustrated in
Next, as shown in
The nitride semiconductor layer 104 can be formed by epitaxially growing a target nitride semiconductor by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like. The nitride semiconductor layer 104 can have a laminate structure in which a plurality of nitride semiconductor layers is laminated. Each layer can be, for example, a layer for forming a transistor such as an HEMT. The outermost surface of the laminate structure can be, for example, a layer formed of GaN. It is preferable to form a material and a thickness of the outermost layer in consideration of chemical mechanical polishing (CMP) performed to secure surface flatness for bonding to be described below and occurrence of damage in the vicinity of a bonding interface due to pressurization in the bonding.
Next, as shown in
After the above-described bonding step, the other substrate 103 is removed from the nitride semiconductor layer 104 (a removing step). Then, as illustrated in
As described with reference to
As described above, when the adhesive layer 102a is formed on the nitride semiconductor layer 104 through crystal-growth of AlN in the +c-axis direction, for example, the adhesive layer 102a can be grown on the lower nitride semiconductor layer 104 in the same growth furnace without being exposed to the atmosphere. However, in this case, AlN can grow only about several nm from the viewpoint of a critical film thickness. When epitaxial growth is performed so that the layer is thicker, the adhesive layer 102a is cracked, for example, which affects the nitride semiconductor layer 104 which is a lower layer on which the device is formed. Thus, it is preferable to use a growth method such as 3-dimensional growth at a low temperature for thick film growth of the adhesive layer 102a. Alternatively, the adhesive layer 102a formed of AlN can be formed by a sputtering method or the like.
Further, as described above, as illustrated in
As described with reference to
The semiconductor laminate structure manufactured by the method of manufacturing the semiconductor laminate structure, as described above, includes the substrate 101 that has a main surface formed as a (boo) plane of Si, the adhesive layer 102 formed of AlN on the substrate, and the nitride semiconductor layer 104 formed of a nitride semiconductor containing Ga on the adhesive layer 102. The main surface of the nitride semiconductor layer 104 has N polarity. The nitride semiconductor layer 104 is bonded to the adhesive layer 102. Further, the adhesive layer 102 can be bonded to the substrate 101.
The semiconductor laminate structure obtained by the above-described method of manufacturing the semiconductor laminate structure can be a template substrate used for manufacturing a semiconductor device using a nitride semiconductor. The nitride semiconductor layer 104 can be used as a template substrate even in a state where the other substrate 103 is removed, but the nitride semiconductor layer 104 near the other substrate 103 is generally formed of a buffer layer including a nucleation layer or the like at the initial stage of crystal (epitaxial) growth, and has low crystal quality. The buffer layer is generally formed of GaN. Therefore, a device layer included in the nitride semiconductor layer 104 for forming the device structure is preferably grown by inserting the buffer layer that has a sufficient thickness.
Further, a layer of the nitride semiconductor layer 104 near the other substrate 103 is often removed together in the removing of the other substrate 103 in accordance with a method of peeling the other substrate 103. Therefore, the above-described buffer layer also has an effect of preventing the device layer from being removed together with the substrate. When the buffer layer is inserted, a desired layer is not exposed only by removing the other substrate 103. Therefore, a step of removing a portion serving as the buffer layer by a removing technology such as CMP or dry etching and exposing a desired layer (a device layer) to the surface is necessary. When the device layer is thin, etching with high selectivity is required, and an etch stop layer may be formed in advance along with the device layer. The buffer layer formed of GaN can be removed by a well-known selective thermal decomposition method.
The template that has the above-described semiconductor laminate structure can be used to manufacture an N-polar nitride semiconductor device on a Si substrate. The template with the semiconductor laminate structure can be used as a wafer for integrating the Si device and the N-polar nitride semiconductor device on the same substrate. For example, when an N-polar GaN device integrated with a CMOS circuit is manufactured using the above-described template, an N-polar GaN layer (the nitride semiconductor layer) in a region where the Si device is formed is first removed by etching to expose Si to the surface. A Si device can then be made in the exposed region. The nitride semiconductor layer can be removed by general dry etching. The nitride semiconductor layer of which a main surface has N polarity can also be removed by wet etching with KOH or the like, unlike a case where the main surface has Group III polarity. The CMOS process on the exposed Si substrate can be performed by using a known semiconductor device manufacturing technology.
Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to
Next (after the removing step), as shown in
Next, as illustrated in
Next, as illustrated in
Thereafter, for example, a gate electrode for a Schottky junction is formed on the surface of the nitride semiconductor layer 104 between the two electrodes 107 and can serve as a field effect transistor.
For example, in the formation of the nitride semiconductor layer 104 described with reference to
In the nitride semiconductor layer 104 configured in this way, two electrodes 107 are formed, as described above. A gate electrode (not illustrated) is formed between the two electrodes 107 to serve as a field effect transistor having 2DEG generated in the barrier layer as a channel. As is well known, a nitride semiconductor has polarization in the c-axis direction. Therefore, by forming a heterojunction between the AlGaN layer and the GaN layer described above, a high-density 2DEG of about 1013 cm−3 can be spontaneously formed by the polarization effect.
Incidentally, the formation of the n+-GaN layer 106 is a general technology for reducing a contact resistance of the electrode 107, but the regrowth is performed at a high temperature equal to or greater than 1000° C., which is a general growth temperature of GaN. Therefore, when the above-described bonding is performed using an adhesive or the like that has no high heat resistance, the technology cannot be applied. On the other hand, the adhesive layer 102 has thermal resistance higher than 1000° C. and has thermal resistance higher than that of GaN. Therefore, even if the adhesive layer 102 is exposed to a high temperature in regrowth of GaN, problems such as deterioration in the adhesive layer 102 and occurrence of peeling in this portion do not occur. Since Si of the substrate 101 and Ga contained in the nitride semiconductor layer 104 are not in direct contact with each other, a reaction progresses at a bonding interface by meltback etching, and peeling or the like does not occur.
Next, a method of manufacturing a semiconductor device according to a third preferred embodiment of the present invention will be described with reference to
As described with reference to
Next, as shown in
Subsequently, a nitride semiconductor containing Ga is crystal-grown in the +c-axis direction on the etching stop layer 142 to form an element formation layer 143. The element formation layer 143 can have, for example, a laminate structure of a GaN layer serving as a channel layer or the like, an AlGaN layer serving as a barrier layer or the like, and a GaN layer serving as a protective layer. At this stage, when viewed from the other substrate 103, a GaN layer serving as a channel layer, an AlGaN layer serving as a barrier layer, and a GaN layer serving as a protective layer are laminated in this order to form the element formation layer 143. A GaN layer serving as a protective layer is disposed on the uppermost layer of the element formation layer 143. The element formation layer 143 is a layer in which a basic structure of a device (a semiconductor device) such as a transistor is formed.
In this way, the nitride semiconductor layer 104a including the buffer layer 141, the etching stop layer 142, and the element formation layer 143 is formed (a first element forming step). The nitride semiconductor layer 104a is formed before the bonding step and before the adhesive layer forming step.
Next, as illustrated in
Next, through a removing step of removing the other substrate 103 from the nitride semiconductor layer 104a to expose the buffer layer 141, as illustrated in
Next, the buffer layer 141 is selectively thermally decomposed on the etching stop layer 142 by heating in a hydrogen atmosphere containing ammonia to remove the buffer layer 141, and the etching stop layer 142 is exposed, as illustrated in
The element formation layer 143 may have a total thickness of about several 10 nm, including an AlGaN layer serving as a barrier layer or the like and a GaN layer serving as a channel layer or the like. On the other hand, the buffer layer 141 disposed on the side of the other substrate 103 in the growth can have a thickness of several hundreds of nm to several lam in order to sufficiently reduce the dislocation density generated by a lattice matching difference with the other substrate 103. Therefore, high selectivity in etching is important between the etching stop layer 142 and the buffer layer 141.
Further, by performing the selective thermal decomposition method in a hydrogen atmosphere containing ammonia, it is possible to selectively control the etching rate of the buffer layer 141. When ammonia is not used, an etching rate (an etching speed) is too fast, and it is difficult to stop etching in the etching stop layer 142 formed of AlGaN even if this layer is used. By controlling the etching rate using ammonia, it is possible to easily control etching to stop the etching in the etching stop layer 142.
In an etching process by the above-described selective thermal decomposition method, a processing temperature is as high as about 1000° C. However, since the adhesive layer 102 formed of AlN is formed, the substrate 101 and the nitride semiconductor layer 104a (the buffer layer 141) do not come into contact with each other, meltback etching due to a reaction between Ga and Si is prevented, and a bonding interface can be prevented from being rough and further from being peeled off. Since AlN has a higher thermal decomposition temperature than GaN, the adhesive layer 102 is hardly decomposed even under the condition of thermally decomposing GaN.
By removing the buffer layer 141, as described above, the main surface of the etching stop layer 142 is a surface facing the side of the other substrate 103, becomes a −c plane, and becomes N polarity (Group V polarity). When viewed from the substrate 101, the element formation layer 143 and the etching stop layer 142 are the same as layers crystal-grown in the −c-axis direction. The element formation layer 143 has a structure in which, for example, a GaN layer serving as a protective layer, an AlGaN layer serving as a barrier layer or the like, and a GaN layer serving as a channel layer or the like are laminated in this order when viewed from the substrate 101. Each layer has a surface on the upper side when viewed from the substrate 101 that has N polarity.
Thereafter (after the second element forming step), by forming an electrode (not shown) and the like on the element formation layer 143, it is possible to obtain a semiconductor device such as a transistor (a third element forming step). For example, the etching stop layer 142 on the element formation layer 143 can be used as a gate insulating layer, and a gate electrode can be formed on the gate insulating layer. After the etching stop layer 142 is removed, a gate electrode for Schottky connection can be formed in the channel layer which is the uppermost layer of the element formation layer 143. A source electrode and a drain electrode that are ohmically connected to a channel formed of 2-dimensional electron gas and formed in the vicinity of a heterointerface between a channel layer and a barrier layer of the element formation layer 143 can be formed with a gate electrode interposed therebetween.
As described above, according to embodiments of the present invention, the substrate that has the main surface formed as the (100) plane of Si and the other substrate on which the nitride semiconductor layer obtained through crystal-growth of the nitride semiconductor containing Ga in the +c-axis direction is formed are bonded together via the adhesive layer formed of AlN, and thus a device that has good characteristics using the nitride semiconductor containing Ga can be formed on the layer of Si that has the plane orientation of the main surface as (100).
The present invention is not limited to the embodiments described above, and it is obvious that many modifications and combinations can be implemented by those skilled in the art within the technical idea of the present invention.
This patent application is a national phase filing under section 371 of PCT application no. PCT/JP2020/041169, filed on Nov. 4, 2020, which application is incorporated herein by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/041169 | 11/4/2020 | WO |
