Patent Application
20100264492
The invention relates to a semiconductor on insulator (SOI) type semiconductor device, for example a double gated SOI device or a fully depleted semiconductor on insulator device (FD-SOI).
SOI technology has a number of advantages in specialized applications as has been realized for some time. More recently, it has been realized that SOI technology may also offer solutions to problems faced in more general applications of insulated gate transistors and in particular in scaling devices to achieve lower sizes.
In the SOI device illustrated in
A particularly beneficial form of SOI technology is known as fully depleted SOI (FD-SOI). In this approach, the semiconductor layer 6 is very thin so that it is fully depleted. Electron transport between source and drain occurs only in the thin channel adjacent to the gate. FD-SOI has improved electrical characteristics, allowing optimization for high temperature, low voltage and low power applications.
A major challenge for FD-SOI is the manufacturing technology which is difficult. There is a need for improved processes to manufacture such devices.
A development of SOI technology is the double gated SOI structure (DG-SOI) in which a further insulated gate is provided below the semiconductor layer 6.
Conventionally, the manufacture of FD-SOI and DG-SOI devices use conventional complementary metal oxide semiconductor (CMOS) processing steps. The source, body and drain are defined using ion implantation and activation annealing. Unfortunately, in thin SOI devices such as FD-SOI and DG-SOI, the resulting sheet resistance and contact resistance are rather high. As a consequence, the series resistance of the transistor is high leading to sub-optimal performance of the transistor.
There is thus a need for a new transistor structure with a reduced series resistance and a method of making it.
According to the invention there is provided a transistor as set out in claim 1.
The semiconductor is preferably silicon.
The use of metallic contact regions together with activated source and drain regions instead of the conventional silicided doped silicon layers leads to a dramatic reduction in series resistance, one of the major problems for thin-body semiconductor devices.
The transistor may further include lower insulated gate below the channel region below the first planar surface, i.e. the transistor may be a double gated structure.
The doping in the activated regions may be at least 1019 cm−3, preferably at least 1020 cm−3 and in particularly preferred embodiments at least 3×1020 cm−3. By providing such highly doped regions, the effect of the Schottky barrier on current flow between the metallic contact regions and the activated semiconductor regions is minimized.
Preferably, an abrupt junction is formed between activated regions and the channel for best performance.
The source and drain contact regions may be of metal.
The invention also relates to method of manufacturing such transistors. Accordingly, in an aspect, the invention relates to a method of making a transistor, comprising:
providing a semiconductor on insulator substrate having a semiconductor layer above insulator;
defining an upper insulated gate above the semiconductor layer;
implanting source and drain regions in the semiconductor layer on either side of the gate leaving a body region between the source and drain regions under the upper insulated gate;
forming insulating spacers on the sides of the upper insulated gate;
implanting an amorphizing implant into the source and drain regions to render the whole of the semiconductor layer amorphous except where protected by the gate or the spacers;
removing the amorphous part of the semiconductor layer using a selective etch; and
depositing metallic contacts onto the source and drain regions.
The spacers may preferably have a thickness of 5 nm or less.
This method delivers a transistor with deposited metal source and drain contact regions, which may have a low resistance, together with highly doped activated source and drain regions in a small region defined by the spacers that gives a good contact between the source and drain contact regions and the channel through the body.
The method is highly integrateable in a CMOS process, and can be used for both FD-SOI and DG-SOI devices.
In another aspect, there is provided a method of making a transistor, comprising:
providing a semiconductor on insulator substrate having a semiconductor layer above insulator;
defining an upper insulated gate above the semiconductor layer;
implanting an amorphizing implant and dopant into the source and drain regions to render the whole of the semiconductor layer amorphous except where protected by the gate leaving a single crystalline body region between the source and drain regions under the upper insulated gate;
annealing the structure to regrow part of the doped amorphous regions starting from the single crystalline body region;
forming metallic contacts from the source and drain regions.
The activated regions have an abrupt junction with the channel which can significantly reduce leakage in the off-state of the semiconductor device.
The process is a low temperature process and accordingly integrateable into advanced CMOS flows.
The step of forming metallic contacts from the source and drain regions may include removing the amorphous part of the semiconductor layer using a selective etch; and depositing metallic contacts onto the source and drain regions. Such metallic contacts can have a much lower resistance than prior art approaches with the top layer of a silicon silicided.
The step of forming metallic contacts from the source and drain regions may alternatively include siliciding the source and drain regions to silicide the full thickness of these region.
The complete replacement of the thin-body silicon or other semiconductor with silicide reduces series resistance. Also, the siliciding process pushes dopants in the source and drain contact regions into the activated region, increasing the doping concentration there.
The step of annealing the structure to regrow part of the doped amorphous regions starting from the single crystalline body region may be carried out at a temperature from 500° C. to 750° C.
The annealing step may be carried out for a time to regrow from 3 nm to 10 nm of single crystal semiconductor.
Experiments suggest that the optimal regrowth is Lgate/6 plus from 1 to 3 nm, where Lgate is the length of the gate.
Implanting the amorphizing implant and the dopant may include the step of implanting an amorphizing implant into the semiconductor layer followed by the step of implanting a dopant into the semiconductor layer.
The step of implanting an amorphizing implant into the semiconductor layer may be carried out at a tilt of between 5° and 30°, preferably between 7° and 30° to get sufficient effect. Preferably, the tilt angle should be such that the overlap between amorphised semiconductor and the gate is about Lgate/6.
Alternatively, a single amorphizing and doping step may be used.
For a better understanding of the invention, embodiments will now be described, purely by way of example, with reference to the accompanying drawings in which:
Note that the Figures are schematic and not to scale.
The method according to the invention starts by providing a structure with a thin layer of silicon 6 provided over insulator 4 on a substrate 2, also of silicon. An upper gate 8 is provided over the thin silicon layer insulated from it by gate insulator 10. A lower gate 20 is provided below the layer of silicon 6, likewise insulated from it by gate insulator 22, as illustrated in
A junction implant is then carried out to dope the source and drain regions 24,26. The doping should be heavy (at least 1019 cm−3) and for the full benefit of the invention the doping should be at least 1020 cm−3. The doping can be either n- or p-type depending on whether an n-type or p-type transistor is being fabricated. The dopant may be B, In etc for a P-type transistor or P, As or Sb for an N-type transistor.
An anneal step follows, which can be a high ramp-rate spike, flash rapid thermal anneal or a sub-melt low-fluence laser anneal. The anneal step ensures the high level activation of the junction and a small diffusion under the gate.
Offset spacers 28 are now fabricated on the upper gate 8, using methods known in the art, such as depositing the material of the spacer on the whole surface and then etching the material away using an anisotropic etch to remove the material from the horizontal surface leaving the material just on the sidewalls of the gate to form the spacers 28. The spacers may be of oxide and/or nitride. The width of the spacers is preferably less than 5 nm. This results in the structure of
An amorphizing implant is then performed amorphizing the full thickness of the silicon layer 6 except where protected by the spacers 28 and upper gate 8, leaving amorphous silicon regions 36 in the regions affected by the amorphizing. The implant can be of species such as Ge, As, Sb or In implanted at a dose and an energy to render the full thickness of silicon layer 6 amorphous. This step leaves activated source and drain regions 30, 32 under the spacers and a body region 34 between the two, as shown in
Next, a selective etch is performed to remove the amorphous silicon regions 36, but not the crystalline regions 30,32,34 or the spacers. Such etches are known. For example, HF may be used if nitride spacers are used, or H3PO4 may be used if oxide spacers are used
Metal is then deposited selectively to form source and drain contact regions 38,40 to replace the removed amorphous silicon as shown in
Processing then continues to finish the device as in conventional processes.
The method is easy to integrate in a CMOS flow and leads to a transistor with a highly reduced resistance. Although at first sight the Schottky barrier between the contact regions 38, 40 and the activated source and drain regions 30, 32, would seem to be highly disadvantageous, the activated regions can be highly doped and this reduces the effect of the barrier to reduce the overall resistance
A second embodiment of a method according to the invention starts with a device at the stage of
Next, an initial amorphisation step is performed to create amorphous regions 50,52. The same species may be used as in the first embodiment, for example Ge, As, Sb or In, but in the second embodiment the implantation is done at a tilt. The tilt angle is selected so that the amorphous region overlaps the gate by about ⅙ of the gate length, leaving central region 54 between the amorphous regions 50, 52.
Next, dopant is implanted into the amorphous regions 50,52. The dopant may be B, In etc for a P-type transistor or P, As or Sb for an N-type transistor. This leads to the structure shown in
In alternative embodiments a single implantation step can be used instead of the amorphisation and dopant implantation steps.
Next, a low temperature Solid Phase Epitaxy Regrowth (SPER) anneal step is performed, at a typical temperature of 500° C. to 750° C. Single crystal semiconductor now grows outwards from the central region 54, forming doped single crystal source and drain regions 56, 58. The regrowth time is tuned so that only a few nm of regrowth is obtained, typically 3-10 nm. Simulations suggest that the optimum regrowth depends on the gate length Lg, and should be of order Lg/6 plus from 1 to 3 nm.
After this step, a highly abrupt (<2 nm/decate), highly active (>3×1020 cm−3) small junction is obtained between the doped single crystal regions 56,58 and the central channel region 54.
Thin spacers 60 are then fabricated, leaving the device as shown in
In the embodiment shown, a silicidation process then takes place, by depositing metal and siliciding in separate steps or in a single step, so that the whole thickness of the remaining amorphous silicon is consumed. This results in silicide source and drain contact regions 62,64. The resulting structure is shown in
Due to the silicide process, dopants in the amorphous silicon will be pushed into the activated single crystal regions 56,58, further enhancing the doping in those regions improving device properties.
The structure can deliver great improvement of current drive due to a dramatic reduction of series resistance. The method delivers a highly abrupt junction between channel and metal thereby greatly improving the leakage current in the off-state by up to two orders of magnitude.
Alternatively, processing of the second embodiment can continue as in the first embodiment to replace the amorphous regions with metal, leading to a structure similar to that of
Although the above embodiments have been described using silicon as the semiconductor, the invention is applicable to other semiconductors such as GaAs, InP, InSb, etc., with the appropriate choice of dopants, for example Zn and Mn.
The above embodiments are double gated structures. The invention is equally applicable to FD-SOI structures only with a single gate by simply omitting the lower gate 20 and gate insulator 22 from the structures.
From reading the present disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalent and other features which are already known in the design, manufacture and use of semiconductor devices and which may be used in addition to or instead of features described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of disclosure also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to any such features and/or combinations of such features during the prosecution of the present application or of any further applications derived therefrom.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0413133.0 | Jun 2004 | GB | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/IB05/51832 | 6/6/2006 | WO | 00 | 7/9/2010 |
