This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0133266, filed on Oct. 2, 2014, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
Example embodiments of the inventive concepts relate to a semiconductor package, and in particular, to a semiconductor package including a package substrate and a semiconductor chip embedded in the package substrate.
There is an increasing demand for electronic products with light weight, small size, high speed, multi-functionality, high performance, and high reliability. A package technology is one of key technologies needed to satisfy such demand. A chip scale package (CSP) technology, one of recently developed package technologies, allows a semiconductor package to have a small size, such as the size of a semiconductor chip.
Increased capacity of the semiconductor package may also be advantageous. For example, advantages may be achieved by integrating more devices in a given area of each semiconductor chip, which typically requires a new expensive fine-patterning technology (e.g., EUV, DPT, or QPT technology). Accordingly, increasing the capacity of the semiconductor package without using such fine-patterning technology may be desired.
Example embodiments of the inventive concepts provide a semiconductor package including a package substrate and vertically-stacked semiconductor chips embedded in the package substrate.
According to example embodiments of the inventive concepts, a semiconductor package may include a package substrate with a cavity, a plurality of semiconductor chips vertically stacked in the cavity, a first insulating layer provided on a first surface of the package substrate, wherein a first interconnection layer is embedded in the first insulating layer, a second insulating layer is provided on a second surface of the package substrate opposite the first surface, wherein a second interconnection layer is embedded in the second insulating layer.
In example embodiments, the semiconductor package may further include an adhesive layer adhesively attaching the plurality of semiconductor chips to each other.
In example embodiments, the adhesive layer may include at least one of polyester, polyethylene, polyethyleneterephthalate, vinyl, polypropylene, polystyrene, polycarbonate, polyvinyl chloride, poly(methyl methacrylate), polyacetal, polyoxymethylene, polybutylene terephthalate, acrylonitrile-butadiene-styrene, or ethylene-vinylalcohol copolymer.
In example embodiments, the semiconductor package may further include a mold layer provided in the cavity to cover the plurality of semiconductor chips.
In example embodiments, the package substrate may include a core portion, a hole, and substrate wirings.
In example embodiments, the hole may be formed to penetrate the package substrate and connect the first surface to the second surface.
In example embodiments, the substrate wirings may be provided on the first and second surfaces and in the hole.
In example embodiments, the plurality of semiconductor chips may be connected to each other through the substrate wirings and the first and second interconnection layers.
In example embodiments, a total thickness of the plurality of semiconductor chips may be substantially equal to or smaller than a thickness of the package substrate.
In example embodiments, the plurality of semiconductor chips may include a first semiconductor chip and a second semiconductor chip stacked along a vertical direction. The first semiconductor chip may include a first active layer adjacent to the first surface and the second semiconductor chip may include a second active layer adjacent to the second surface.
In example embodiments, the first active layer may be connected to the first interconnection layer.
In example embodiments, the second active layer may be connected to the second interconnection layer.
In example embodiments, the semiconductor package may further include a gap-fill insulating layer provided in the cavity.
According to example embodiments of the inventive concepts, a semiconductor package may include first and second interconnection layers vertically spaced apart from each other, a semiconductor chip group between the first and second interconnection layers, a first insulating layer between the first interconnection layer and the semiconductor chip group, and a second insulating layer between the second interconnection layer and the semiconductor chip group. The semiconductor chip group may include a first semiconductor chip and a second semiconductor chip stacked along a vertical direction.
In example embodiments, the semiconductor package may further include an adhesive layer provided between the first and second semiconductor chips.
In example embodiments, the first semiconductor chip may include a first active layer positioned in a top portion thereof, and the second semiconductor chip may include a second active layer positioned at a bottom portion thereof.
In example embodiments, the first semiconductor chip may include a first electrode pad on the first active layer, and the second semiconductor chip may include a second electrode pad on the second active layer.
In example embodiments, the first electrode pad may be connected to the first interconnection layer.
In example embodiments, the second electrode pad may be connected to the second interconnection layer.
In example embodiments, the semiconductor package may further include a mold layer provided to cover the semiconductor chip group.
In example embodiments, the semiconductor package may further include a gap-fill insulating layer provided to cover the semiconductor chip group.
In example embodiments, the semiconductor package may further include a package substrate with a cavity, in which the semiconductor chip group is provided.
Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, example embodiments as described herein.
It should be noted that these figures are intended to illustrate the general characteristics of methods, structure and/or materials utilized in certain example embodiments and to supplement the written description provided below. These drawings are not, however, to scale and may not precisely reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values or properties encompassed by example embodiments. For example, the relative thicknesses and positioning of molecules, layers, regions and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numbers in the various drawings is intended to indicate the presence of a similar or identical element or feature.
Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Example embodiments of the inventive concepts may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the example embodiments to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
It will be understood that when an element is referred to as being “on,” “connected” or “coupled” to another element, it can be directly on, directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected” or “directly coupled” to another element, there are no intervening elements present. Like numbers indicate like elements throughout. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” “on” versus “directly on”). Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under or one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including,” if used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the inventive concepts belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Although corresponding plan views and/or perspective views of some cross-sectional view(s) may not be shown, the cross-sectional view(s) of device structures illustrated herein provide support for a plurality of device structures that extend along two different directions as would be illustrated in a plan view, and/or in three different directions as would be illustrated in a perspective view. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The plurality of device structures may be integrated in a same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is illustrated in a cross-sectional view, an electronic device may include a plurality of the device structures (e.g., memory cell structures or transistor structures), as would be illustrated by a plan view of the electronic device. The plurality of device structures may be arranged in an array and/or in a two-dimensional pattern.
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The core portion 102 may have the first surface 100a, the second surface 100b, and side surfaces. For example, the core portion 102 may include one of composites composed of a reinforcing element and a resin (e.g., glass fiber/epoxy resin, paper/phenolic resin, or paper/epoxy resin). The through hole 106 may be formed in the core portion 102 to penetrate the package substrate 100. For example, the through hole 106 may be formed to connect the first surface 100a to the second surface 100b.
The substrate wirings 104 may be formed on the first and second surfaces 100a and 100b of the package substrate 100 and/or in the through hole 106. The substrate wirings 104 may partially expose the core portion 102. The substrate wirings 104 may connect the first surface 100a electrically to the second surface 100b. A plurality of insulating layers (not shown) may be further provided to cover the substrate wirings 104. The substrate wirings 104 may include at least one ground line, at least one power line, and at least one signal line. The substrate wirings 104 may be formed of or include, for example, copper. As an example, the substrate wirings 104 may include copper patterns provided in the form of a copper clad laminate.
Although not illustrated in detail, the core portion 102 may include circuit patterns, and the substrate wirings 104 may be electrically connected to the circuit patterns through the internal wirings of the core portion 102. Further, the substrate wirings 104 may include portions electrically connected to each other.
A cavity 105 may be formed to vertically penetrate the package substrate 100. As will be described below, a plurality of semiconductor chips 120 and 130 may be disposed in the cavity 105. The cavity 105 may be formed to have an area larger than the area of the through hole 106.
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The first semiconductor chip 120 may include a first active layer 122 and a first electrode pad 124. The first active layer 122 may be adjacent to the first surface 100a of the package substrate 100. The first active layer 122 may include electronic devices (e.g., a transistor and so forth). The first electrode pad 124 may be on the first active layer 122. For example, the first electrode pad 124 may be formed of or include at least one of silver, palladium, platinum, silver-palladium alloy, nickel, copper, or any combination thereof.
The second semiconductor chip 130 may include a second active layer 132 and a second electrode pad 134. The second active layer 132 may be provided adjacent to the second surface 100b of the package substrate 100. The second active layer 132 may include electronic devices (e.g., a transistor and so forth). The second electrode pad 134 may be provided on the second active layer 132. The second electrode pad 134 may be in contact with the supporter 110. For example, the second electrode pad 134 may be formed of or include at least one of silver, palladium, platinum, silver-palladium alloy, nickel, copper, or any combination thereof.
An adhesive layer 140 may be provided between the first semiconductor chip 120 and the second semiconductor chip 130. For example, the adhesive layer 140 may be a film having an adhesive property. The adhesive layer 140 may be formed of or include at least one of polyester, polyethylene, polyethyleneterephthalate, vinyl, polypropylene, polystyrene, polycarbonate, polyvinyl chloride, poly(methyl methacrylate), polyacetal, polyoxymethylene, polybutylene terephthalate, acrylonitrile-butadiene-styrene, or ethylene-vinylalcohol copolymer. For example, the adhesive layer 140 may include at least one selected from the group consisting of polyester, polyethylene, polyethyleneterephthalate, vinyl, polypropylene, polystyrene, polycarbonate, polyvinyl chloride, poly(methyl methacrylate), polyacetal, polyoxymethylene, polybutylene terephthalate, acrylonitrile-butadiene-styrene, or ethylene-vinylalcohol copolymer. By using the adhesive layer 140, the first semiconductor chip 120 can be adhesively attached to the second semiconductor chip 130, which helps reduce or substantially prevent the first semiconductor chip 120 from being misaligned from the second semiconductor chip 130 in a subsequent process.
In example embodiments, the largest width d1 of the semiconductor chips 120 and 130 may be smaller than a width d2 of the cavity 105. A total thickness h1 of the semiconductor chips 120 and 130 may be smaller than or equal to a thickness h2 of the package substrate 100.
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A gap-fill insulating layer 155 may be provided in the cavity 105. The gap-fill insulating layer 155 may cover the semiconductor chips 120 and 130. The semiconductor chips 120 and 130 may be structurally fixed by the gap-fill insulating layer 155 and may be electrically insulated from each other by the gap-fill insulating layer 155. The gap-fill insulating layer 155 may be substantially the same material as the first insulating layer 150.
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The first and second interconnection layers 180 and 190 may be formed using a plating or deposition process. The first and second interconnection layers 180 and 190 may be formed of or include, for example, silver (Ag) or copper (Cu). The first interconnection layer 180 may be electrically connected to the substrate wirings 104 and the first electrode pad 124 via the first vias 172. The second interconnection layer 190 may be electrically connected to the substrate wirings 104 and the second electrode pad 134 via the second vias 174. As a result of this example configuration, the first interconnection layer 180 may be electrically connected to the first active layer 122, and the second interconnection layer 190 may be electrically connected to the second active layer 132. The first and second interconnection layers 180 and 190 may be electrically connected to the ground line, the power line and/or the signal line in the core portion 102.
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After the formation of the mold layer 200, the first insulating layer 150 may be formed on the first surface 100a. The supporter 110 may be removed to expose the second surface 100b of the package substrate 100, and then, the second insulating layer 160 may be formed on the exposed second surface 100b. The first vias 172 may be formed in the first insulating layer 150, and the second vias 174 may be formed in the second insulating layer 160. Here, the first vias 172 and the second vias 174 may be formed to expose the first and second electrode pads 124 and 134, respectively, in the mold layer 200. The subsequent steps may be performed in substantially the same or similar manner as those of the fabrication method previously described with reference to
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The controller 3100 and/or the memory 3200 may be provided in the form of a semiconductor package according to example embodiments of the inventive concepts. For example, the controller 3100 may be provided in the form of a system-in-package structure, and the memory 3200 may be provided in the form of a multi-chip-stacking package. In certain embodiments, the controller 3100 and/or the memory 3200 may be provided in the form of a stack-type package. The memory card may be used as a storage media in various portable devices. For example, the memory card may be provided in the form of a multimedia card (MMC) or a secure digital (SD) card.
According to example embodiments of the inventive concepts, a plurality of sequentially-stacked semiconductor chips may be embedded in a package substrate, and thus, it is possible to form interconnection layers on top and bottom surfaces, respectively, of the package substrate.
According to example embodiments of the inventive concepts, in a semiconductor package, the interconnection layers may be connected to the semiconductor chips, without additional connecting element, such as solder balls.
According to example embodiments of the inventive concepts, a plurality of semiconductor chips may be vertically stacked, and thus, it is possible to reduce an area of the semiconductor package.
While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.
Number | Date | Country | Kind |
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10-2014-0133266 | Oct 2014 | KR | national |