Claims
- 1. A polishing pad adapted for mounting on a belt, characterised by: a seam joint between opposed edge portions of the polishing pad, and a caulking material in the seam joint bonding to the opposed edge portions, which decreases the likelihood of stretching, bunching up, and/or delaminating of the pad from the belt.
- 2. The polishing pad according to claim 1, wherein the polishing pad has one polishing pad section with a length that corresponds to the outer circumference of the belt, and wherein the polishing pad section has the opposed edge portions.
- 3. The polishing pad according to claim 1, wherein the polishing pad has multiple polishing pad sections having the opposed edge portions.
- 4. The polishing pad according to claim 1, wherein the seam joint is provided with a channel.
- 5. The polishing pad and belt according to claim 1, wherein the opposed polishing pad edge portions have contours forming a channel.
- 6. The polishing pad according to claim 5, wherein the depth of the channel is half the thickness of the polishing pad.
- 7. The polishing pad according to claim 5, wherein the channel has a triangular shape.
- 8. The polishing pad according to claim 5, wherein the contours have angled slopes.
- 9. The polishing pad according to claim 1, wherein the caulking material is polyurethane.
- 10. The polishing pad according to claim 1, and further comprising: adhesive laminating the polishing pad to a belt, and the caulking material prevents the polishing pad from delaminating from the belt as the pad and the belt rotate over rollers in a semiconductor polishing fixture.
- 11. The polishing pad according to claim 1, wherein a polishing surface of the polishing pad includes stress relief grooves oriented transversely relative to a direction of rotation of the polishing pad in a polishing pad fixture.
- 12. A reinforced semiconductor polishing pad and belt comprising: a belt; a polishing pad in adhesive connection with the belt, wherein the polishing pad includes a polishing surface that is operative to polish and planarize a semiconductor substrate, and wherein the polishing pad includes at least one seam joint between two opposed polishing pad edge portions, and wherein each of the opposed polishing pad edge portions are cooperatively contoured in overlapping relation.
- 13. The reinforced semiconductor polishing pad and belt according to claim 12, wherein the polishing pad is comprised of one polishing pad section with a length that corresponds to the outer circumference of the belt, wherein the opposed polishing pad edge portions correspond to the ends of the one polishing pad section.
- 14. The reinforced semiconductor polishing pad and belt according to claim 12, wherein the polishing pad is comprised of at least two polishing pad sections, wherein the opposed polishing pad edge portions correspond to adjacent ends of the two polishing pad sections.
- 15. The reinforced semiconductor polishing pad and belt according to claim 12, wherein the opposed polishing pad edge portions are cooperatively beveled.
- 16. The reinforced semiconductor polishing pad and belt according to claim 12, wherein the opposed polishing pad edge portions are cooperatively dove-tailed.
- 17. The reinforced semiconductor polishing pad and belt according to claim 12, wherein the belt is comprised of a stainless steel mesh.
- 18. The reinforced semiconductor polishing pad and belt according to claim 12, wherein seam joint is orientated in a generally transverse direction with respect to the direction of rotation of the belt in a polishing pad fixture.
- 19. The reinforced semiconductor polishing pad and belt according to claim 12, wherein the polishing surface includes a plurality of parallel stress relief grooves in an upper surface of the polishing pad, wherein the parallel stress relief grooves are oriented in a generally transverse direction with respect to the direction of rotation of the belt in a polishing pad fixture.
- 20. A delamination resistant semiconductor polishing pad and belt characterised by: a belt; and a polishing pad in adhesive connection with the belt, wherein the polishing pad includes a polishing surface that is operative to polish and planarize a semiconductor substrate, wherein the polishing surface includes a plurality of parallel stress relief grooves therein.
- 21. The delamination resistant semiconductor polishing pad and belt according to claim 20, wherein the parallel stress relief grooves are oriented in a generally transverse direction with respect to the direction of rotation of the belt across at least one belt roller 16 of a polishing pad fixture.
- 22. The delamination resistant semiconductor polishing pad and belt according to claim 21, wherein the parallel stress relief grooves each have a depth of generally between 5 and 45 mils.
- 23. The delamination resistant semiconductor polishing pad and belt according to claim 22, wherein the parallel stress relief grooves each have a width of generally between 5 and 60 mils.
- 24. The delamination resistant semiconductor polishing pad and belt according to claim 23, wherein the distance between parallel stress relief grooves along the upper surface of the polishing pad is generally between 50 and 500 mils.
- 25. The delamination resistant semiconductor polishing pad and belt according to claim 21, wherein the stress relief grooves have a generally rectangular cross-sectional shape.
- 26. The delamination resistant semiconductor polishing pad and belt according to claim 20, wherein the stress relief grooves span the width of the polishing pad.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of provisional application serial No. 60/201,629 filed May 3, 2000.
Provisional Applications (1)
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Number |
Date |
Country |
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60201629 |
May 2000 |
US |