BRIEF DESCRIPTION OF THE DRAWINGS
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:
FIG. 1 is a flowchart of semiconductor process evaluation methods according to some embodiments of the present invention;
FIGS. 2A through 2F are diagrams showing a variety of shapes into which a test semiconductor substrate can be divided according to some embodiments of the present invention;
FIG. 3 is a view of electrostatic scan methods according to embodiments of the present invention;
FIG. 4 is a view of modified versions of electrostatic scan methods of FIG. 3 according to embodiments of the present invention;
FIG. 5 is a view of mechanical scan methods according to other embodiments of the present invention;
FIGS. 6A through 6C are sequential views illustrating processes for forming divided regions on a test semiconductor substrate using electrostatic scan methods of FIG. 3 or 4, or mechanical scan methods of FIG. 5, and by rotating the test semiconductor substrate according to some embodiments of the present invention;
FIGS. 7A through 7C are diagrams showing examples where metal line layers are formed on the sub-regions which are formed under the different ion implanting conditions according to some embodiments of the present invention;
FIG. 8 is a schematic flowchart of semiconductor process evaluation methods according to other embodiments of the present invention;
FIGS. 9A through 9C are diagrams showing a variety of regions into which a test semiconductor substrate can be divided and a variety of different metal line layers are formed on the divided regions according to some embodiments of the present invention; and
FIG. 10 is a table illustrating a case where unit devices are formed on a test semiconductor substrate using conditions given as examples in FIG. 7C according to methods of FIGS. 1 through 8.