Semiconductor Process Evaluation Methods Including Variable Ion Implanting Conditions

Information

  • Patent Application
  • 20070155028
  • Publication Number
    20070155028
  • Date Filed
    November 28, 2006
    18 years ago
  • Date Published
    July 05, 2007
    17 years ago
Abstract
Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:



FIG. 1 is a flowchart of semiconductor process evaluation methods according to some embodiments of the present invention;



FIGS. 2A through 2F are diagrams showing a variety of shapes into which a test semiconductor substrate can be divided according to some embodiments of the present invention;



FIG. 3 is a view of electrostatic scan methods according to embodiments of the present invention;



FIG. 4 is a view of modified versions of electrostatic scan methods of FIG. 3 according to embodiments of the present invention;



FIG. 5 is a view of mechanical scan methods according to other embodiments of the present invention;



FIGS. 6A through 6C are sequential views illustrating processes for forming divided regions on a test semiconductor substrate using electrostatic scan methods of FIG. 3 or 4, or mechanical scan methods of FIG. 5, and by rotating the test semiconductor substrate according to some embodiments of the present invention;



FIGS. 7A through 7C are diagrams showing examples where metal line layers are formed on the sub-regions which are formed under the different ion implanting conditions according to some embodiments of the present invention;



FIG. 8 is a schematic flowchart of semiconductor process evaluation methods according to other embodiments of the present invention;



FIGS. 9A through 9C are diagrams showing a variety of regions into which a test semiconductor substrate can be divided and a variety of different metal line layers are formed on the divided regions according to some embodiments of the present invention; and



FIG. 10 is a table illustrating a case where unit devices are formed on a test semiconductor substrate using conditions given as examples in FIG. 7C according to methods of FIGS. 1 through 8.


Claims
  • 1. A semiconductor process evaluation method, comprising: dividing a test semiconductor substrate into a plurality of regions;scanning the regions using ion beams under different ion implanting conditions; andmeasuring parameters of the plurality of regions of the test semiconductor substrate that were scanned using the ion beams under different ion implanting conditions, to conduct the semiconductor process evaluation.
  • 2. The method of claim 1, wherein the ion implanting conditions differ from each other by at least one process variable including ion dose, type of dopant, ion implanting energy, ion implanting angle, and/or notch orientation of the test semiconductor substrate.
  • 3. The method of claim 1, wherein the scanning of the regions is performed by an ion implanting device using an electrostatic scan method, a mechanical scan method and/or a hybrid scan method.
  • 4. The method of claim 1, wherein the ion implanting conditions are varied by varying an ion dose and, in order to vary the ion dose, the method further comprises varying a scan speed of the ion beams in a direction of the test semiconductor substrate.
  • 5. The method of claim 1, wherein a scan length of one scan of the ion beams is greater than a diameter of the test semiconductor substrate.
  • 6. The method of claim 1, wherein the scan length of one scan of the ion beams is less than a diameter of the test semiconductor substrate.
  • 7. The method of claim 1, wherein the ion implanting conditions are varied by varying an ion dose, and in order to vary the ion dose, the method further comprises moving the test semiconductor substrate at a variable speed.
  • 8. The method of claim 7, wherein the moving of the test semiconductor substrate is performed in a vertical direction.
  • 9. The method of claim 7, wherein the moving of the test semiconductor substrate is performed in a horizontal direction.
  • 10. The method of claim 1, wherein the scanning of the regions comprises: scanning the test semiconductor substrate using the ion beams while varying the ion implanting condition in a first direction of the test semiconductor substrate in a state where a notch is positioned in a first position; andscanning the test semiconductor substrate using the ion beams while varying the ion implanting condition in a second direction of the test semiconductor substrate in a state where the notch is positioned in a second position.
  • 11. The method of claim 10, wherein, in order to displace the notch from the first position to the second position, the test semiconductor substrate rotates by a predetermined angle about a rotational axis that is located at a center of the test semiconductor substrate.
  • 12. The method of claim 1, wherein the ion implanting conditions are varied by varying an ion dose and wherein the scanning of the test semiconductor substrate comprises: scanning the test semiconductor substrate using the ion beams while varying a scan speed of the ion beams in a first direction of the test semiconductor substrate in a state where a notch is positioned in a first position; andscanning the test semiconductor substrate using the ion beams while varying the scan speed of the ion beams in a second direction of the test semiconductor substrate in a state where the notch is positioned in a second position.
  • 13. The method of claim 12, wherein in order to displace the notch from the first position to the second position, the test semiconductor substrate is rotated by a predetermined angle about a rotational axis that is located at a center of the test semiconductor substrate.
  • 14. The method of claim 1, further comprising, after scanning the test semiconductor substrate, dividing at least one region of the test semiconductor substrate into a plurality of sub-regions; and forming different metal line layers on the sub-regions.
  • 15. The method of claim 14, wherein the metal line layers form word lines, bit lines, capacitor electrodes, fuses and/or conductive pads.
  • 16. The method of claim 15, wherein the metal line layers form the word lines and the word lines have different widths according to the sub-regions.
  • 17. A semiconductor process evaluation method comprising: forming a plurality of different metal line layers on respective divided regions of a test semiconductor substrate;dividing at least one of the divided regions into a plurality of sub-regions;scanning the sub-regions using ion beams under different ion implanting conditions; andmeasuring parameters of the plurality of sub-regions of the test semiconductor substrate that were scanned using the ion beams under different ion implanting conditions, to conduct the semiconductor process evaluation.
  • 18. The method of claim 17, wherein the metal line layers form gate electrode layers and the gate electrode layers of the regions have different lengths from each other.
  • 19. The method of claim 17, wherein, by performing the scanning of the sub-regions using the ion beams, ion implanting regions for controlling a threshold voltage of transistors formed by the gate electrode layers, source/drain regions, shallow ion implanting regions and/or lightly doped drain regions are formed in the test semiconductor substrate under the gate electrode layers by the scanning ion beam.
  • 20. The method of claim 17, wherein the metal line layers are doped with ion impurities by scanning the sub-regions using the ion beams.
  • 21. The method of claim 17, wherein the ion implanting conditions differ from each other by at least one process variable including ion dose, type of dopant, ion implanting energy, ion implanting angle, and/or notch orientation of the test semiconductor substrate.
  • 22. The method of claim 17, wherein the scanning of the sub-regions is performed by an ion implanting device using an electrostatic scan method, a mechanical scan method and/or a hybrid scan method.
  • 23. The method of claim 17, wherein the ion implanting conditions are varied by varying an ion dose and, in order to vary the ion dose, the method further comprises varying a scan speed of the ion beams in a direction of the test semiconductor substrate.
  • 24. The method of claim 17, wherein the scan length of one scan of the ion beams is greater than a diameter of the test semiconductor substrate.
  • 25. The method of claim 17, wherein the scan length of one scan of the ion beams is less than a diameter of the test semiconductor substrate.
  • 26. The method of claim 17, wherein the ion implanting conditions are varied by varying an ion dose, and in order to vary the ion dose, the method further comprises moving the test semiconductor substrate at a variable speed.
  • 27. The method of claim 26, wherein the moving of the test semiconductor substrate is performed in a vertical direction.
  • 28. The method of claim 26, wherein the moving of the test semiconductor substrate is performed in a horizontal direction.
  • 29. The method of claim 17, wherein the scanning of the region comprises: scanning the test semiconductor substrate using the ion beams while varying the ion implanting condition in a first direction of the test semiconductor substrate in a state where a notch is positioned in a first position; andscanning the test semiconductor substrate using the ion beams while varying the ion implanting condition in a second direction of the test semiconductor substrate in a state where the notch is positioned in a second position.
  • 30. The method of claim 29, wherein, in order to displace the notch from the first position to the second position, the test semiconductor substrate is rotated by a predetermined angle about a rotational axis that is located at a center of the test semiconductor substrate.
  • 31. The method of claim 17, wherein the ion implanting conditions are varied by varying an ion dose and wherein the scanning of the test semiconductor substrate comprises: scanning the test semiconductor substrate using the ion beams while varying a scan speed of the ion beams in a first direction of the test semiconductor substrate in a state where a notch is positioned in a first position; andscanning the test semiconductor substrate using the ion beams while varying the scan speed of the ion beams in a second direction of the test semiconductor substrate in a state where the notch is positioned in a second position.
  • 32. The method of claim 31, wherein in order to displace the notch from the first position to the second position, the test semiconductor substrate is rotated by a predetermined angle about a rotational axis that is located at a center of the test semiconductor substrate.
  • 33. A semiconductor process evaluation method, comprising: performing multiple scans of a test semiconductor substrate using ion beams under different ion implanting conditions; andmeasuring parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions, to conduct the semiconductor process evaluation.
  • 34. The method of claim 33, wherein the ion implanting conditions differ from each other by at least one process variable including ion dose, type of dopant, ion implanting energy, ion implanting angle, and/or notch orientation of the test semiconductor substrate.
  • 35. The method of claim 33, wherein the test semiconductor substrate is a test semiconductor wafer.
Priority Claims (1)
Number Date Country Kind
10-2005-0133030 Dec 2005 KR national