Semiconductor storage device and storage system

Abstract

A semiconductor storage device includes an external input/output port. A system bus of a server, which is extended to outside of the server, is connected to the external input/output port directly as a serial interface.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention will be described in detail based on the following figures, wherein:

FIG. 1 is a block diagram showing a storage system according to a first exemplary embodiment of the invention.

FIG. 2 is a block diagram showing an internal configuration of a semiconductor storage device shown in FIG. 1.

FIG. 3 is a block diagram showing an internal configuration of a semiconductor storage device according to a second exemplary embodiment of the invention.

FIG. 4 is a block diagram showing a storage system according to a third exemplary embodiment of the invention.

FIG. 5 is a flowchart showing the operation of the storage system according to the third exemplary embodiment of the invention.

Claims

1. A semiconductor storage device comprising: an external input/output port to which a system bus of a server, which is extended to outside of the server, is connected directly as a serial interface.

2. A semiconductor storage device comprising: an external input/output port to which a system bus of a server, which is extended to outside of the server, is connected directly as a serial interface; anda device controller that connects to the server using predetermined number of links among serial transmission links of the serial interface, which are successful in connection on initialization.

3. A semiconductor storage device comprising: an external input/output port to which a system bus of a server, which is extended to outside of the server, is connected directly as a serial interface; anda device controller that connects to the server using predetermined number of links among serial transmission links of the serial interface, which are successful in connection on initialization, wherein:the device controller comprises: an external link detection section that detects the serial transmission links, which are successful in connection; anda first register that stores a detection result of the external link detection section, the first register that can be accessed from an outside of the device.

4. The device according to claim 3, further comprising: a memory controller connected to the device controller through a control bus and a memory bus, wherein:the memory controller comprises: a downstream bus-error detection section that detects an error in downstream transmission in the memory bus;a memory error detection section that detects an error relating to access to a memory; anda third register that stores a detection result of the downstream bus-error detection section and a detection result of the memory error detection section, the third register that can be accessed from the outside of the device, through the control bus, and the device controller further comprises:an upstream bus-error detection section that detects an error in upstream transmission in the memory bus; anda second register that stores a detection result of the upstream bus-error detection section, the second register that can be accessed from the outside of the device.

5. The device according to claim 4, wherein the device controller reads contents of the first to third registers, terminates data transmission when a predetermined bit is valid, and outputs an error interrupt signal to the server.

6. The device according to claim 1, wherein the serial interface is based on a differential transmission system using two signal lines as one lane.

7. A storage system comprising: a storage server; anda semiconductor storage device connected to the storage server, wherein:the semiconductor storage device comprises an external input/output port to which a system bus of the server, which is extended to outside of the server, is connected directly as a serial interface.

8. A storage system comprising: a storage server;a semiconductor storage device connected to the storage server; anda magnetic storage device, wherein:the semiconductor storage device comprises an external input/output port to which a system bus of the server, which is extended to outside of the server, is connected directly as a serial interface,the storage server comprises: a first external input/output port that connects to the magnetic storage device; anda second external input/output port that connects to the semiconductor storage device, anda transmission band per port in the second external input/output port is higher than that in the first external input/output port.

9. A storage system comprising: a storage server; anda semiconductor storage device connected to the storage server, wherein:the semiconductor storage device comprises: an external input/output port to which a system bus of the server, which is extended to outside of the server, is connected directly as a serial interface; anda device controller that connects to the server using predetermined number of links among serial transmission links of the serial interface, which are successful in connection on initialization.

10. The system according to claim 9, wherein: the semiconductor storage device further comprises a memory controller connected to the device controller through a control bus and a memory bus;the device controller comprises: an external link detection section that detects the serial transmission links, which are successful in connection;a first register that stores a detection result of the external link detection section, the first register that can be accessed from an outside of the device controller;an upstream bus-error detection section that detects an error in upstream transmission in the memory bus; anda second register that stores a detection result of the upstream bus-error detection section, the second register that can be accessed from the outside of the device controller,the memory controller comprises: a downstream bus-error detection section that detects an error in downstream transmission in the memory bus;a memory error detection section that detects an error relating to access to a memory; anda third register that stores a detection result of the downstream bus-error detection section and a detection result of the memory error detection section, the third register that can be accessed from an outside of the memory controller, through the control bus.

11. The system according to claim 8, wherein: when detecting an error interrupt signal from the second external input/output port, the storage server terminates data transmission relating to the pertinent semiconductor storage device.

12. The system according to claim 8, wherein the storage server causes the semiconductor storage device to function as an external storage device.

13. The system according to claim 8, wherein the storage server comprises a cache control unit that causes the semiconductor storage device to function as cache memory for the magnetic storage device.

14. A storage system comprising: a storage server;a semiconductor storage device connected to the storage server; anda magnetic storage device, wherein:the semiconductor storage device comprises an external input/output port to which a system bus of the server, which is extended to outside of the server, is connected directly as a serial interface,the storage server comprises: a first external input/output port that connects to the magnetic storage device;a second external input/output port that connects to the semiconductor storage device; anda cache control unit that causes the semiconductor storage device to function as cache memory for the magnetic storage device,a transmission band per port in the second external input/output port is higher than that in the first external input/output port, andthe cache control unit is implemented by software on the storage server.

15. The system according to claim 13, wherein the semiconductor storage device comprises a block-address retrieval processing unit that checks whether or not there is a cache hit about a block to be accessed.

16. The system according to claim 15, wherein the block-address retrieval processing unit is provided in the device controller or the memory controller.