Embodiments of this disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor structure and a manufacturing method for the same.
With relentless development of semiconductor structures, the feature size of the semiconductor structures constantly decreases. However, limited by lithography machines, the decrease of the feature size of the semiconductor structure is constrained. Therefore, making a chip with higher storage density on a wafer is the research goal for many in the field. In a two-dimensional or planar semiconductor device, storage units are all arranged in a horizontal direction. Therefore, the packing density of the two-dimensional or planar semiconductor devices may depend on an area occupied by a single storage unit, and the packing density of the two-dimensional or planar semiconductor device is greatly affected by technologies used to form fine patterns. Consequently, the packing density of the two-dimensional or planar semiconductor device is limited. Therefore, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.
However, the locations of various functional components in an existing three-dimensional semiconductor device need to be redesigned. For example, existing layout space needs to be fully used while ensuring various functional components are not mutually affected, so as to improve the packing density of the three-dimensional semiconductor device in a wafer.
Embodiments of this disclosure provide a semiconductor structure and a manufacturing method for the same that at least improve the packing density of a transistor structure and a capacitor structure in the semiconductor structure.
One aspect of the embodiments of this disclosure provides a semiconductor structure, including: a transistor structure and a capacitor structure that are arranged along a first direction, where the capacitor structure extends along the first direction; a wordline staircase structure, where the wordline staircase structure and the transistor structure are disposed along a second direction, the wordline staircase structure extends along the first direction, the first direction intersects the second direction, and the wordline staircase structure is electrically connected to the transistor structure, where a plane perpendicular to the second direction is used as a reference plane, an orthographic projection of the transistor structure on the reference plane is a first projection, an orthographic projection of the capacitor structure on the reference plane is a second projection, an orthographic projection of the wordline staircase structure on the reference plane is a third projection, the third projection covers the first projection, and the third projection partially overlaps the second projection.
According to some embodiments of this disclosure, another aspect of the embodiments of this disclosure further provides a manufacturing method for a semiconductor structure, including: forming a transistor structure and a capacitor structure that are arranged along a first direction, where the capacitor structure extends along the first direction; and forming a wordline staircase structure, where the wordline staircase structure and the transistor structure are disposed along a second direction, the wordline staircase structure extends along the first direction, the first direction intersects the second direction, and the wordline staircase structure is electrically connected to the transistor structure, where a plane perpendicular to the second direction is used as a reference plane, an orthographic projection of the transistor structure on the reference plane is a first projection, an orthographic projection of the capacitor structure on the reference plane is a second projection, an orthographic projection of the wordline staircase structure on the reference plane is a third projection, the third projection covers the first projection, and the third projection partially overlaps the second projection.
One or more embodiments are exemplified by the corresponding accompanying drawings, and these exemplifications do not constitute limitations on the embodiments. Similar elements are denoted with the same reference numerals in the accompanying drawings. Unless otherwise stated, the accompanying drawings do not conform to scale. To describe technical solutions of embodiments of this disclosure or conventional technologies more clearly, the following briefly describes the accompanying drawings to be used in the embodiments. Apparently, the accompanying drawings in the following description show merely some embodiments of this disclosure, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
Embodiments of this disclosure provide a semiconductor structure and a manufacturing method for the same. In the semiconductor structure, a transistor structure is neighboring to a capacitor structure along a first direction, and a transistor structure is neighboring to a wordline staircase structure along a second direction. In this way, the total structural length of the transistor structure, the capacitor structure, and the wordline staircase structure in the first direction is reduced while the transistor structure is electrically connected to the wordline staircase structure. In addition, it can be understood that the structural length of the semiconductor structure in the first direction usually depends on the structural length of the capacitor structure in the first direction. A portion of the wordline staircase structure extending along the first direction faces the capacitor structure, so that the wordline staircase structure can be arranged along the first direction to the extent possible while the structural length of the wordline staircase structure in the second direction is reduced. These structures can increase the length of the facing area between the wordline staircase structure and the capacitor structure, effectively use the layout space, and reduce the total layout area of the semiconductor structure. Therefore, the packing density of the transistor structure and the capacitor structure in the semiconductor structure is improved.
The following describes in detail the embodiments of this disclosure with reference to the accompanying drawings. However, a person of ordinary skill in the art can understand that in the embodiments of this disclosure, to help the readers better understand the embodiments of this disclosure, many technical details are provided. However, the technical solutions claimed in the embodiments of this disclosure can also be implemented even without these technical details and various changes and modifications made based on the following embodiments.
An embodiment of this disclosure provides a manufacturing method for a semiconductor structure. The manufacturing method for a semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.
As shown in
It can be understood that, as shown in
The following describes the semiconductor structure in detail with reference to
In some embodiments, as shown in
It can be understood that, for a single storage structure 103, the wordline staircase structure 102 is protruded relative to the transistor structure 100 and the capacitor structure 101 in the second direction Y. In addition, due to the requirement to increase the electric capacity of the capacitor structure 101, the structural length of the capacitor structure 101 is greater than the structural length of the wordline staircase structure 102 in the first direction X, so that in the extension direction of the wordline staircase structure 102, a portion of region facing the capacitor structure 101 is vacant. The wordline staircase structure 102 may merely have a step structure in the first direction X, or may have step structures in both the first direction X and the second direction Y, thereby increasing the quantity of step structures within a same area. In an embodiment of this disclosure, two neighboring storage structure 103 in the first direction X are centrosymmetric, and the vacant region of one of the two storage structures 103 may correspond to the vacant region of the other storage structure 103, that is, the capacitor structure 101 in one of the storage structures 103 may be deployed in the vacant region, which does not face the wordline staircase structure 102, of the other storage structure 103, to improve the layout density of the storage structure 103.
In addition, the wordline staircase structure 102 in one of the two storage structures 103 and the capacitor structure 101 in the other storage structure 103 are disposed along the first direction X. In this way, the structural length of two storage structures 103 in the second direction Y is the same as that of one storage structure 103 in the second direction Y, that is, the wordline staircase structure 102 in one of the two storage structures 103 is disposed in parallel to the capacitor structure 101 in the other storage structure 103. This further improves the layout density of the storage structure 103, thereby improving the packing density of the semiconductor structure.
There is a first gap between the wordline staircase structure 102 in one of the two storage structures 103 and the capacitor structure 101 in the other storage structure 103. When the structural length of the first gap in the first direction X is not considered, the structural length of the two storage structures 103 in the first direction X is equivalent to a sum of the structural length of one storage structure 103 in the first direction X and the structural length of one wordline staircase structure 102 in the first direction X. In this way, the structural length of two storage structures 103 in the first direction X can be reduced to further improve the layout density of the storage structure 103.
It should be noted that
In some embodiments, as shown in
In some embodiments, as shown in
It can be understood that along the third direction Z, a plurality of sub transistor structures 110 and a plurality of sub capacitor structures 111 may be arranged, one sub transistor structure 110 may be used as an individual transistor unit, one sub capacitor structure 111 may be used as an individual capacitor unit, and one transistor unit and capacitor unit may form a storage unit. In this way, by stacking the sub transistor structures 110 and the sub capacitor structures 111 in the third direction Z, the layout density of the storage units in the semiconductor structure is improved, thereby improving the packing density of the semiconductor structure.
In addition, the sub transistor structures 110 are connected to the step structures 112 in a one-to-one correspondence, and the lengths of the plurality of step structures 112 in the first direction X are different. Therefore, different sub transistor structures 110 can be controlled by using different step structures 112, so that different sub transistor structures 110 are independent of each other. In some embodiments, in the direction from the sub transistor structure 110 to the substrate 160, the lengths of the plurality of step structures 112 in the first direction X may gradually increase.
In some embodiments, still as shown in
In addition, in some embodiments, the bottom electrode layer 121 in the sub capacitor structure 111 includes the semiconductor channel 113 in the third region 143 and a sub bottom electrode layer 151. The sub bottom electrode layer 151 covers a portion of side wall/top surface, extending along the first direction X, of the third region 143. The capacitor dielectric layer 131 covers a side wall/top surface, away from the third region 143 and extending along the first direction X, of the sub bottom electrode layer 151. The top electrode layer 141 covers a side wall/top surface, away from the sub bottom electrode layer 151 and extending along the first direction X, of the sub capacitor dielectric layer 131. The sub capacitor structure 111 is electrically connected to the sub transistor structure 110 through the second region 133, that is, a signal in the sub transistor structure 110 is transmitted to the sub capacitor structure 111 for storage through the second region 133, or a signal stored in the sub capacitor structure 111 is transmitted to the sub transistor structure 110 through the second region 133.
In some embodiments, the top electrode layer 141 may include a diffusion impervious layer (not shown in the figure) and a sub top electrode layer (not shown in the figure) that are sequentially stacked. The diffusion impervious layer covers a side wall/top surface, away from the sub bottom electrode layer 151 and extending along the first direction X, of the capacitor dielectric layer 131. The sub top electrode layer covers a side wall/top surface, away from the capacitor dielectric layer 131 and extending along the first direction X, of the diffusion impervious layer. The diffusion impervious layer prevents diffusion of a conducting material in the sub top electrode layer toward the capacitor dielectric layer 131, to ensure good insulation performance of the capacitor dielectric layer 131 and good conductivity of the sub top electrode layer. In an example, the diffusion impervious layer may be made of titanium nitride; the sub top electrode layer and the sub bottom electrode layer 151 may both be made of at least one of conducting materials such as polysilicon, titanium nitride, or tungsten; and the capacitor dielectric layer 131 may be made of a dielectric material with a high dielectric constant such as hafnium oxide, chromium oxide, or zirconium oxide.
In some embodiments, as shown in
In some embodiments, as shown in
In some embodiments, the step structure 112 may include a supporting layer 153, a dielectric layer 132, and a conducting layer 122. The supporting layer 153 and the semiconductor channel 103 may be integrated, the dielectric layer 132 and the gate dielectric layer 130 may be integrated, and the conducting layer 122 and the gate conducting layer 140 may be integrated. In an example, the electric connection layer 150 is in contact with and connected to the gate conducting layer 140 in the transistor structure 100, and the electric connection layer 150 and the gate conducting layer 140 in the transistor structure 100 are on a same layer. The electric connection layer 150 is in contact with and connected to the conducting layer 122 in the wordline staircase structure 102, and the electric connection layer 150 and the conducting layer 122 in the wordline staircase structure 102 are on a same layer. As can be learned, the conducting layer 122 is electrically connected to the gate conducting layer 140 through the electric connection layer 150, so that the step structure 112 is electrically connected to the sub transistor structure 110.
In another embodiment, the step structure may include a conducting layer, and the conducting layer is electrically connected to a gate conducting layer through an electric connection layer, and the conducting layer and a sub transistor structure are on a same layer.
In some embodiments, still as shown in
It should be noted that the electric connection layers 150 are in a one-to-one correspondence with the sub transistor structures 110, that is, there are a plurality of electric connection layers 150 sequentially disposed along the third direction Z, and the first dielectric layer 107 is further configured to insulate the plurality of electric connection layers 150.
In some embodiments, as shown in
It can be understood that, as shown in
It should be noted that
The following describes the support structure 104 in detail with reference to
In some embodiments, as shown in
It can be understood that the plurality of storage structures 103 extending along the second direction Y can share the support structure 104, so that one support structure 104 can fasten and support a plurality of capacitor structures 101 to improve the stability of the semiconductor structure.
In some embodiments, as shown in
As can be understood, that the first support layer 114 covers a portion of side wall, extending along the first direction X, of the bottom electrode layer 121 means that the first support layer 114 covers the portion of side wall at the third region 143, of the bottom electrode layer 121. In an example, the first support layer 114 may fully occupy the first gap, and can implement electrical isolation between the step structure 112 in one of the two storage structures 103 and the capacitor structure 101 in the other storage structure 103 while fastening and supporting the capacitor structure 101, to prevent electrical interference between the neighboring storage structures 103.
In some embodiments, as shown in
As can be learned from the foregoing description, along the third direction Z, the gate structure 120 may include the gate dielectric layer 130 and the gate conducting layer 140 that are sequentially stacked.
It can be understood that the first support layer 114, the second support layer 124, and the third support layer 134 separately cover different parts of side wall (e.g., top or bottom surface) of the semiconductor channel 113 to support the semiconductor channel 113. In addition, because the second support layer 124 covers a plurality of stack structures arranged along the second direction Y, the second support layer 124 further covers a portion of side wall of the supporting layer 153 in the step structure 112 while covering the side wall of the second region.
The following describes the first support layer 114, the second support layer 124, and the third support layer 134 in detail with reference to a specific example.
In an example, as shown in
It should be noted that the side wall of the first region 123, the side wall of the second region 133, and the side wall of the third region 143 are the side wall, extending along the first direction X, of the semiconductor channel 113. It can be understood that the second support layer 124 covers the side wall of the second region 133, so that the second support layer 124 can fasten and support both the transistor structure 100 and the capacitor structure 101, and can implement electrical isolation between the gate structure 120 and the sub bottom electrode layer 151 or the top electrode layer 141. The first support layer 114, the third support layer 134, and the sub bottom electrode layer 151 cover the side wall, extending along the first direction X, of the third region 143 together. The first support layer 114 and the third support layer 134 fasten and support the capacitor structure 101 together.
In some embodiments, as shown in
It can be understood that the step structures 112 are in a one-to-one correspondence with the sub transistor structures 110, and the first conducting columns 115 are in a one-to-one correspondence with the sub transistor structures 110, so that different sub transistor structures 110 can be controlled by using different first conducting columns 115. In an example, the first conducting columns 115 are in contact with and connected to conducting layers 122 in the step structures 112, and the second conducting columns 125 are in contact with and connected to top electrode layers 141 in the capacitor structures 101.
It should be noted that
In some embodiments, as shown in
It can be understood that the second dielectric layer 137 and the third dielectric layer 147 support the first conducting column 115 and the second conducting column 125 together and make the semiconductor structure flat.
In some embodiments, as shown in
In conclusion, along the first direction X, the transistor structure 100 is neighboring to the capacitor structure 101; and along the second direction Y, the transistor structure 100 is neighboring to the wordline staircase structure 102. In this way, while the transistor structure 100 is electrically connected to the wordline staircase structure 102, the total structural length of the transistor structure 100, the capacitor structure 101, and the wordline staircase structure 102 in the first direction X is reduced. In addition, a portion of region, extending along the first direction X, of the wordline staircase structure 102 faces the capacitor structure 101. In this way, the wordline staircase structure 102 can be extended along the first direction X as long as possible while the structural length of the wordline staircase structure 102 in the second direction Y is reduced, so as to increase the length of the transition region between the wordline staircase structure 102 and the capacitor structure 101, effectively use the layout space, and reduce the total layout area of the semiconductor structure, thereby improving the packing density of the transistor structure 100 and the capacitor structure 101 in the semiconductor structure.
Another embodiment of this disclosure further provides a manufacturing method for a semiconductor structure to manufacture the semiconductor structure provided in the foregoing embodiments. The manufacturing method for a semiconductor structure provided in the another embodiment of this disclosure is described in detail below with reference to
As shown in
In some embodiments, the wordline staircase structure 102 and the transistor structure 100 are formed by using a same preparation step. In this way, the manufacturing process of the semiconductor structure is simplified and the manufacturing costs of the semiconductor structure are reduced. How to form the wordline staircase structure 102 and the transistor structure 100 by using the same preparation step will be described in detail below with reference to specific embodiments.
In some embodiments, as shown in
In some embodiments, the support structure 104 includes a first support layer 114, and forming the first support layer 114 may include the following steps:
As shown in
It should be noted that two neighboring first stack structures 116 are centrosymmetric, and two neighboring second stack structures 126 are centrosymmetric. The first stack structure 116 is configured to subsequently form a transistor structure and a capacitor structure. The second stack structure 126 is configured to subsequently form a wordline step structure.
In some embodiments, the step of forming the first stack structure 116 and the second stack structure 126 may include: as shown in
In some embodiments, before the forming an initial first semiconductor layer 136 and an initial second semiconductor layer 146, the method further includes: providing a substrate 160, and subsequently forming the initial first semiconductor layer 136 and the initial second semiconductor layer 146 on the substrate 160.
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It can be understood that the top view of the fourth mask layer 189 is also shown in
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In some embodiments, as shown in
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The second semiconductor layer 166 in the second stack structure 126 may be used as the supporting layer 153 in the step structure. The second opening 129 exposes a portion of supporting layer 153.
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It can be understood that the first hole 118, the second hole 128, and the third hole 138 may be formed simultaneously; and the first support layer 114, the second support layer 124, and the third support layer 134 may be formed simultaneously to simply the process steps of manufacturing the support structure 104.
In some embodiments, forming the transistor structure 100 may include the following step:
With reference to
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A dielectric layer 132 is provided between the conducting layer 122 and the second semiconductor layer 166 in the second stack structure 126. The second semiconductor layer 166 in the second stack structure 126 is a supporting layer 153. The dielectric layer 132 and the gate dielectric layer 130 are integrated. The conducting layer 122 and the gate conducting layer 140 are integrated. A step of forming the gate structure 120, the conducting layer 122, and the dielectric layer 132 includes: forming the conducting layer 122 and the gate conducting layer 140, where the conducting layer 122 and the gate conducting layer 140 conformally cover the side wall extending along the first direction X and exposed by the second semiconductor layer 166 in
The semiconductor channel 113 of the first region 123 and the gate structure 120 form the sub transistor structure 110. The second semiconductor layer 166, the dielectric layer 132, and the conducting layer 122 in the second stack structure 126 form the initial wordline staircase structure 142. A plurality of sub transistor structures 110 arranged along the third direction Z form the transistor structure 100.
In some embodiments, still as shown in
In some embodiments, as shown in
Still as shown in
It should be noted that the first dielectric layer 107 is formed on a top surface of the third region 143 on the top. Therefore, when the second sacrificial layer 127 is removed, the first dielectric layer 107 on the top surface of the third region 143 is removed to expose the entire side wall, extending along the first direction X, of the third region 143 on the top.
As shown in
It can be understood that for a third region 143, the third region 143, and the sub bottom electrode layer 151, the capacitor dielectric layer 131, and the top electrode layer 141 that sequentially cover the side wall of the third region 143 form a sub capacitor structure 111. A plurality of sub capacitor structures 111 arranged along the third direction Z (as shown in
It should be noted that in the step of forming the sub bottom electrode layer 151, the capacitor dielectric layer 131, and the top electrode layer 141, the sub bottom electrode layer 151, the capacitor dielectric layer 131, and the top electrode layer 141 may further cover the top surface of the first dielectric layer 107. Subsequently, flatting processing is performed to form the capacitor structure 101 shown in
In some embodiments, the step of forming the top electrode layer 141 may include: forming a diffusion impervious layer (not shown in the figure) and a sub top electrode layer (not shown in the figure) that are sequentially stacked, where the diffusion impervious layer covers a side wall (top surface), away from the sub bottom electrode layer 151 and extending along the first direction X, of the capacitor dielectric layer 131; and the sub top electrode layer covers a side wall (top surface), away from the capacitor dielectric layer 131 and extending along the first direction X, of the diffusion impervious layer.
In some embodiments, as shown in
It can be understood that the dielectric layer 132 in the wordline staircase structure 102 and the gate dielectric layer 130 in the transistor structure 100 are formed by using a same preparation step, and the conducting layer 122 in the wordline staircase structure 102 and the gate conducting layer 140 in the transistor structure 100 are formed by using a same preparation step.
It should be noted that a manufacturing method for forming a plurality of step structures 112 having different lengths in the first direction X is not limited in this embodiment of this disclosure, provided that the wordline staircase structure 102 shown in
In some embodiments, as shown in
In conclusion, in the semiconductor structure formed by using the foregoing manufacturing method, along the first direction X, the transistor structure 100 is neighboring to the capacitor structure 101; and along the second direction Y, the transistor structure 100 is neighboring to the wordline staircase structure 102. In this way, while the transistor structure 100 is electrically connected to the wordline staircase structure 102, the total structural length of the transistor structure 100, the capacitor structure 101, and the wordline staircase structure 102 in the first direction X is reduced. In addition, a portion of region, extending along the first direction X, of the wordline staircase structure 102 faces the capacitor structure 101. In this way, the wordline staircase structure 102 can be extended along the first direction X as long as possible while the structural length of the wordline staircase structure 102 in the second direction Y is reduced, so as to increase the length of the transition region between the wordline staircase structure 102 and the capacitor structure 101, effectively use the layout space, and reduce the total layout area of the semiconductor structure, thereby improving the packing density of the transistor structure 100 and the capacitor structure 101 in the semiconductor structure.
A person of ordinary skill in the art can understand that the foregoing implementations are specific embodiments for implementing this disclosure. However, in actual application, forms and details of the foregoing implementations may be modified without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, the protection scope of the embodiments of this disclosure shall be subject to the scope defined by the claims.
Number | Date | Country | Kind |
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202210716305.7 | Jun 2022 | CN | national |
This application is a continuation application of International Patent Application No. PCT/CN2022/107125, filed on Jul. 21, 2022, which claims priority to Chinese Patent Application No. 202210716305.7, filed with the China National Intellectual Property Administration on Jun. 22, 2022 and entitled “SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR SAME.” The above-referenced applications are incorporated herein by reference in their entirety.
Number | Date | Country | |
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Parent | PCT/CN2022/107125 | Jul 2022 | US |
Child | 17954316 | US |