The present application claims priority benefit of Chinese patent application No. 201210310953.9, filed on 28 Aug. 2012, entitled
“SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME”, which is herein incorporated by reference in its entirety.
The present invention relates to semiconductor manufacturing field, and particularly, to a semiconductor structure and a method for manufacturing the same.
With development of semiconductor structure manufacturing technology, integrated circuits with better performance and more powerful functions require greater element density, and sizes of elements and spacing among elements need to be further downscaled. Accordingly, lithography process faces greater demands and challenges during procedure of forming semiconductor structures.
Particularly, in manufacturing static random access memory (SRAM), line-and-cut dual patterning technology is usually applied in order to form gates inside semiconductor structures. Application of aforementioned technology is described here below with reference to
However, aforementioned conventional process has the following advantages. Firstly, aforementioned process requires extremely precise distance between tips of gates in lithography. Specifically, it becomes increasingly difficult to implement such a gate line patterning process along with developments of downscaling size in devices. In particular, it becomes extremely difficult to manufacture cutting masks. Additionally, application of aforementioned technique would be more complicated in replacement gate and high K dielectric processes. Accordingly, sidewall spacer dual patterning is probably required at sub-22 nm technical node.
Meanwhile, spacers usually have to be formed on two sides of electrically isolated gates to surround the gates in subsequent processes. Since cuts 16 have been formed between gates, the spacer material is deposited on two sides of the gate and further into cutes 16 when forming the spacers. However, because the cuts 16 are quite narrow, spacer material is prone to form voids within the cuts, which consequently is unfavorable for subsequent processing. Particularly, short-circuits may arise at subsequent process for forming metal plugs. Additionally, if the gate is a dummy gate, the voids will give rise to short circuits at subsequent replacement gate process, which consequently deteriorates performance and stability of semiconductor devices.
The present invention is intended to provide a semiconductor structure and a method for manufacturing the same to suppress defects arising at formation of gates for semiconductor structures, and is favorable for facilitating subsequent process for manufacturing semiconductor devices.
In one aspect, the present invention provides a method for manufacturing a semiconductor structure comprising:
(a) forming gate lines extending along one direction on a substrate;
(b) forming a photoresist layer to cover a semiconductor structure, and patterning the photoresist layer to form openings that span over the gate lines; and
(c) implanting ions into the gate lines via the openings, such that the gate lines are insulated at the openings.
Accordingly, the present invention further provides a semiconductor structure, which comprises:
a substrate;
gate lines, which extend along one direction and are formed on the substrate, and spacers formed on two sides of the gate lines; and
insulating regions, which isolate neighboring gate lines from each other at said direction, wherein the material for the insulating regions is different from the material for the spacers.
As compared to the line-and-cut dual patterning techniques in the prior art, the present invention provides a semiconductor structure and a method for manufacturing the same, in which an insulating layer is formed along gate length direction by ion implantation instead of forming cuts on gate lines, so as to form electrically isolated gates. Therefore, the gate lines are not disconnected physically, and the gate lines are kept in complete shape instead. Such processes would not cause defects that exist in the prior art, and therefore facilitates subsequent process and guarantees performance of semiconductor devices.
Other additional features, aspects and advantages of the present invention are made more evident after reading the following detailed description of exemplary embodiment(s) in conjunction with accompanying drawings:
The same or similar reference signs in the appended drawings denote the same or similar elements.
The objectives, technical solutions and advantages of the present invention are made more evident according to the following detailed description of exemplary embodiments in conjunction with the accompanying drawings.
Embodiments of the present invention will be described in detail below, wherein examples of embodiments are illustrated in the appended drawings, in which same or similar reference signs throughout denote same or similar elements, or elements having same or similar functions. It should be understood that embodiments described below in conjunction with the drawings are illustrative. These embodiments are provided for explaining the present invention only, and thus shall not be interpreted as a limit to the present invention.
Various embodiments or examples are provided here below to implement different structures of the present invention. To simplify the disclosure of the present invention, descriptions of components and arrangements of specific examples are given below. Of course, they are only illustrative and not limiting the present invention. Moreover, in the present invention, reference numbers and/or letters may be repeated in different examples. Such repetition is for purposes of simplicity and clarity, and does not denote any relationship between respective embodiments and/or arrangements under discussion. Furthermore, the present invention provides various examples for various processes and materials. However, it is obvious for a person of ordinary skill in the art that other processes and/or materials may be alternatively utilized. In addition, following structures where a first feature is “on/above” a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact with each other, and may also include an embodiment in which another feature is formed between the first feature and the second feature such that the first and second features might not be in direct contact with each other. However, layer structural diagrams are illustrated in the appended drawings. It should be noted that the appended drawings might not be drawn to scale. For purposes of clarity, some details are enlarged while some details are omitted from the appended drawings. Respective regions, shapes of layers and their relative dimensions and positional relationships are given exemplarily and thus are not drawn to scale, in which difference is allowed due to permitted manufacturing tolerance or technical limits in practice. Meanwhile, those skilled in the art can design regions/layers in different shapes, sizes and relative positions according to requirements in practice.
Preferred embodiments of the present invention are described according to a method for manufacturing a semiconductor structure provided by the present invention.
With reference to
In step S101, gate lines extending along one direction are formed on a substrate.
In step S102, a photoresist layer is formed to cover a semiconductor structure. The photoresist layer is patterned to form openings that span over the gate lines.
At an optional step S103, a self-assembly copolymer is formed within openings to narrow the openings.
In step S104, ions are implanted into the gate lines via the openings, such that the gate lines are insulated at the openings.
With reference to
Typically, the substrate 100 may have, but not limited to, a thickness of around several hundred micrometers, which, for example, may be in the range of 400 μm-800 μm. According to design requirements, the substrate 100 may be bulk Si or Silicon-On-Insulator (SOI). A shallow trench isolation (STI) structure may be formed on the substrate in advance, such that the STI structure separates the surface of the substrate into independent active regions.
The material for the photoresist layer 201 may be a vinyl monomer material, a material containing nitrine quinone compound or a polyethylene lauric acid material. Of course, other materials as appropriate may be used according to manufacturing requirements in practice.
The gate lines 210 extending along one direction (the direction perpendicular to paper sheet shown in
With reference to
In the present embodiment, neither source/drain regions nor spacers are formed at this stage, and following description is based on such a structure.
With reference to
Usually, the material for the photoresist layer 300 may be a vinyl monomer material, a material containing nitrine quinone compound or a polyethylene lauric acid material. As shown in
With reference to
In this case, the step S103 is optionally performed to form a self-assembly copolymer within the openings to narrow the openings.
Because the openings 310 are further processed in subsequent steps,
With reference to
After formation of the self-assembly copolymer layer 320 on the inner walls of the openings 310, the distance between two opposite walls of the opening 310 along the gate width direction becomes W2, wherein W2<W1, because the self-assembly copolymer 320 has a thickness. Usually, W2 is less than 30 nm, for example, 10 nm. Therefore, after the self-assembly copolymer layer 320 is laid on the inner walls of the openings 310, the distance between two opposite walls of the opening 310 along the gate width direction is further decreased.
With reference to
The step S103 might not be performed in the present embodiment, and the following description is given on such a basis.
Next, with reference to
After formation of the insulating layer 230, the semiconductor structure may be further processed, as shown in
Additionally, according to design requirements of semiconductor structures, at least one strained layer 400 may be formed to cover the gate lines 210, the spacers 220 and the substrate 100 after formation of spacers 220. The strained layer is provided for purposes of increasing stress so as to enhance performance of semiconductor devices, as shown in
Optionally, it is possible to firstly form spacers 220 and at least one strained layer 400, and then form the insulating layer 230. Namely, the step for forming the insulating layer 230 may be performed at last. With reference to the above embodiments, a pattern composed of gate lines 210 shown in
With regard to the technical solution of the present invention, the step for forming the insulating layer 230 may be performed after the step for forming the spacers 220, or after both steps for forming the spacers 220 and forming the strained layer 400 (usually, the strained layer 400 is formed after formation of the spacers 220), or may be performed before formation of spacers 220 and the strained layer 400. Therefore, it is possible to arrange manufacturing steps flexibly, and a variety of manufacturing procedures may be provided. Nonetheless, it is noteworthy that the step for forming the insulating layer 230 (i.e. forming electrically isolated gates) should precede the step for forming contact plugs that are in contact with source/drain regions.
No matter which method for manufacturing a semiconductor structure provided by the present invention is performed, the step for forming the insulating layer 230 may be followed by such steps as: forming at least one dielectric layer that covers the gate lines, spacers and source/drain regions (if a strained layer 400 has already been formed in the semiconductor structure, then the at least one dielectric layer also covers the strained layer 400), and forming contact plugs, which are embedded within the at least one dielectric layer, to be electrically connected with source/drain regions 100 and/or the gates. The at least one dielectric layer may be formed on the substrate 100 by means of Chemical-Vapor Deposition (CVD), High-Density Plasma CVD or other processes as appropriate. The material for the dielectric layer may be any one selected from a group consisting of SiO2, carbon-doped SiO2, BPSG, PSG, USG, SiOxNy, a low k material or combinations thereof. The material for the contact plugs may be any one selected from a group consisting of W, Al, TiAl alloy or combinations thereof.
As compared to the line-and-cut dual patterning techniques in the prior art, the present invention provides a semiconductor structure and a method for manufacturing the same in which an insulating layer is formed along gate length direction by ion implantation instead of forming cuts on gate lines, so as to form electrically isolated gates. This process neither causes damage to the physical shape of the gate lines 210 nor forms any physical cuts. Instead, the gate lines 210 maintain its complete shape. Such processes would not give rise to defects in the prior art when forming a dielectric layer at subsequent steps, and therefore facilitates subsequent process and guarantees performance of semiconductor devices. In addition, formation of the insulating layer 230 is not limited by formation of spacers 220 and the strained layer 400. Therefore, manufacturing steps are flexible and a variety of manufacturing procedures may be provided, which can satisfy more scenarios in practice.
A preferred structure of the semiconductor structure provided by the present invention is described here below. Now refer to
a substrate 100;
gate lines 210 extending along one direction, which are formed on the substrate; and spacers 220 formed on two sides of the gate lines;
insulating regions 230, which isolate the neighboring gate lines 210 along said direction, wherein the material for the insulating regions 230 is different from the material for the spacers 220.
The substrate 100 comprises Si substrate (e.g. Si wafer). According to design requirements in the prior art (e.g. a P-type substrate or an N-type substrate), the substrate 100 may be of various doping configurations. The substrate 100 in other embodiments may further comprise other basic semiconductors, for example, germanium. Alternatively, the substrate 100 may comprise a compound semiconductor, such as SiC, GaAs, InAs or InP. Typically, the substrate 100 may have, but is not limited to, a thickness of around several hundred micrometers, which, for example, may be in the range of 400 μm-800 μm. There may be a shallow trench isolation structure 120 formed on the substrate 100. The shallow trench isolation structure 120 separates the surface of the substrate 100 into independent active regions 110.
The gate line 210 is a gate stack, which comprises a gate dielectric layer and a gate material layer on the gate dielectric layer, and therefore, the gate dielectric layer is located in the lower position in the gate stack on the substrate 100. Usually, the material for the gate dielectric layer may be a thermal oxide layer, which comprises SiO2 or SiOxNy, or may be a high K dielectric, for example, any one selected from a group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, La2O3, ZrO2, LaAlO or combinations thereof, with a thickness in the range of 1 nm-4 nm. The gate material layer may be any one selected from a group consisting of Poly-Si, Ti, Co, Ni, Al, W, alloy, metal silicide or combinations thereof. In some embodiments, the gate material layer my be in a multi-layer structure, which, for example, is formed by a gate metal layer and a gate electrode layer. The material for the gate metal layer may be any one selected from a group consisting of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTa or combinations thereof, with a thickness in the range of 5 nm-20 nm. Poly-Si may be selected as the material for the gate electrode layer, whose thickness may be in the range of 20 nm-80 nm. Optionally, the gate stack may further comprise at least one dielectric cap layer that covers the gate material layer for purposes of protecting other structures of the gate stack located beneath it. Usually, the size of gate lines and the pitch between gate lines may be determined according to requirements for designing semiconductor devices. Generally, the gate lines are arranged in parallel.
In addition, spacers 220 are formed on two sides of the gate lines and surround the gate lines. The spacers 220 may be formed with Si3N4, SiO2, SiOxNy, SiC and/or other material as appropriate. The spacers 220 may be in a multi-layer structure. The spacers 220 may be formed by depositing-etching process, with a thickness in the range of about 10 nm-100 nm. Source/drain regions may be formed within active regions 110 on the substrate 100. Generally, source/drain regions are formed after formation of gate lines 210.
The gate lines 210 are cut off by the insulating layer 230 along the gate length direction, such that the gate lines 210 are cut into electrically isolated gates, such as gate 211 and gate 212. The gate 211 and the gate 212 are positioned on one gate line 210 but are electrically isolated by the insulating layer 230. Usually, the material for the insulating layer 230 is an insulating material such as an oxide of the material for forming the gate stack (i.e. material for the gate lines), for example, SiO2 and metal oxide, which is different from the material for the spacers 220. The above mentioned process is different from isolating tips of neighboring gates by means of spacer material in the prior art. Preferably, the insulating layer 230 is formed above the shallow trench isolation structure 120, which is favorable for saving area and improving integrity. In the gate width direction, the thickness of the insulating layer 230 is less than 50 nm, for example 10 nm.
The insulating layer 230 is formed by means of ion implantation, for example, implanting oxygen ions.
Now refer to
Optionally, as shown in
Optionally, the semiconductor structure further comprises at least a dielectric layer that covers the gate lines, spacers and source/drain regions (if a strained layer 400 has already been formed in the semiconductor structure, the at least one dielectric layer covers the strained layer 400); contact plugs, which are embedded within the at least one dielectric layer, are electrically connected to source/drain regions and/or the gates. The material for the at least one dielectric layer may be any one selected from a group consisting of SiO2, carbon-doped SiO2, BPSG, PSG, USG, SiOxNy, a low k material or combinations thereof. The material for the contact plugs may be any one selected from a group consisting of W, Al, TiAl alloy or combinations thereof.
It should be noted that the semiconductor structure provided in the embodiments and other semiconductor structures may be included in one semiconductor device.
Although the exemplary embodiments and their advantages have been described in detail herein, it should be understood that various alternations, substitutions and modifications may be made to the embodiments without departing from the spirit of the present invention and the scope as defined by the appended claims. As for other examples, it may be easily understood by a person of ordinary skill in the art that the order of the process steps may be changed without departing from the scope of the present invention.
In addition, the scope, to which the present invention is applied, is not limited to the process, mechanism, manufacture, material composition, means, methods and steps described in the specific embodiments in the specification. According to the disclosure of the present invention, a person of ordinary skill in the art should readily appreciate from the disclosure of the present invention that the process, mechanism, manufacture, material composition, means, methods and steps currently existing or to be developed in future, which perform substantially the same functions or achieve substantially the same as that in the corresponding embodiments described in the present invention, may be applied according to the present invention. Therefore, it is intended that the scope of the appended claims of the present invention includes these process, mechanism, manufacture, material composition, means, methods or steps.
Number | Date | Country | Kind |
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201210310953.9 | Aug 2012 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2012/081509 | 9/17/2012 | WO | 00 |