Patent Application
20080082889
The best mode for carrying out the invention will be explained in details in reference to the drawings as follows.
Further, the semiconductor test system 10 includes DA converters 5, 6. The DA converter 5 on one side sets a voltage value of a signal at a high level inputted to DUT 4 by the driver 2. The DA converter 6 on the other side sets a voltage value of a signal at a low level inputted to DUT 4 by the driver 2. Further, DUT 4 is a semiconductor device constituting an object of test, such as a memory device and an IC device.
Further, the semiconductor test system 10 includes a DA converter 7, a DA converter 8, an adjustment DA converter 15 and an adjustment DA converter 16. The DA converter 7 sets a threshold value on a high level side for determining a signal outputted from DUT by the comparator 3a. The DA converter 8 sets a threshold value on a low level side for determining a signal outputted from DUT 4 by the comparator 3a. The adjustment DA converter 15 sets a voltage value of a signal at a high level, which is inputted to DUT 4 by the driver 2, to a voltage value at an adjustment high level adjusted in accordance with a characteristic of a transmission line 9 mentioned later. The adjustment DA converter 16 sets a voltage value of a signal at a low level, which is inputted to DUT 4 by the driver 2, to a voltage value at an adjustment low level adjusted in accordance with the characteristic of the transmission line 9 mentioned later. The driver 2 and the comparators 3a, 3b are connected to DUT 4 respectively through the transmission lines 9.
The PG&TG1 generates a test pattern data stored in a memory or the like (not illustrated) by a predetermined timing to output to the driver 2. Further, a memory or the like (not illustrated) stores data of an expected value and a comparison timing for comparing a signal outputted from DUT 4. The PG&TG1 compares signals outputted from the comparators 3a, 3b with the expected value.
Further, the PG&TG1 analyzes a test pattern data and transmits an instruction code for setting a target value thereof to a voltage value at an adjustment high level, to the adjustment DA converter 15 at a rise timing of a waveform of a test signal from a low level to a high level. Further, the PG&TG1 transmits an instruction code for setting the target value to a voltage value at an adjustment low level, to the adjustment DA converter 16 at a fall timing of the waveform of the test signal from the high level to the low level. Further, a further description will be given with regard to setting the voltage values at an adjustment high level and at an adjustment low level.
The driver 2 inputs the test signal of the waveform based on the test pattern data outputted from PG&TG1 to DUT 4 by way of the transmission line 9. Thereby, the signals at the high level, at the low level, at the adjustment high level and at the adjustment low level are outputted by the voltage values in accordance with respective settings of the DA converters 5, 6 and the adjustment DA converters 15, 16.
The comparator 3a is provided with a function of comparing the signal outputted from DUT 4 by way of the transmission line 9 with a threshold of a side of a high level set by the DA converter 7 and converting the signal into a logic signal at a high level based on a result of comparison to output to PG&TG1.
The comparator 3b compares the signal that is outputted from DUT 4 through the transmission line 9, with a threshold value on a low level side set by the DA converter 8, and converts the signal into a logic signal at a low level based on a comparison result to output to PG&TG1.
The DA converter 5 sets a voltage value of a signal of a high level when the driver 2 inputs the signal at the high level to DUT 4. The DA converter 6 sets a voltage value of a signal at a low level when the driver 2 inputs the signal at the low level to DUT 4. Further, the transmission line 9 is a cable for transmitting a signal of a coaxial cable, for example.
The adjustment DA converter 15 sets the voltage value of the signal at the high level, which is inputted by the driver 2 to DUT 4, to a voltage value at an adjustment high level only during a time interval of a minimum pulse width in rising of the waveform of the test signal from low level to high level.
Here, the voltage value at the adjustment high level becomes higher than a voltage value set by the DA converter 5, and becomes a virtual target value when a rising time period is prolonged by a characteristic of the transmission line 9. Further, in actual rising, the voltage value is adjusted to pass through a voltage value similar to that set by the DA converter 5 when a time period of a minimum pulse width has elapsed. The voltage value is previously calculated and set based on the characteristic of the transmission line 9 or a characteristic of the driver 2 or the like.
The adjustment DA converter 16 sets a voltage value of a signal at a low level, which is inputted to DUT 4 by the driver 2, to a voltage value at an adjustment low level only during a time interval of a minimum pulse width in falling of the waveform of the test signal from a high level to a low level.
The voltage value at the adjustment low level becomes lower than a voltage value set by the DA converter 6 conversely to the adjustment high level and becomes a virtual target value when a falling time period is prolonged by the characteristic of the transmission line 9. Further, in actual falling, the voltage value is adjusted to pass through a voltage value similar to that set by the DA converter 6 when a time period of the minimum pulse width has elapsed and is previously calculated and set based on the characteristic of the transmission line 9 or the characteristic of the driver 2 or the like.
As is apparent from comparison between the semiconductor test system 10 of the present embodiment and the semiconductor test system 11 of the comparative example, the semiconductor test system 10 of the present embodiment differs from the semiconductor test system 11 of the comparative example with respect to configurations that the adjustment DA converters 15, 16 are provided other than the DA converters 5, 6.
Next, a detailed explanation will be given of operation of the semiconductor test system 10 according to the present embodiment with reference to
In this case, as shown in
Then, as shown in
Further, in the case of rise, as shown in
In this way, according to the embodiment, even when time periods of rise and fall are prolonged by the characteristic of the transmission line 9, the target voltage values at time of changes are set to the adjustment high level VIHH and the adjustment low level VILL. Therefore, the slopes of rise and fall of actual waveforms become larger than inherent slopes. However, the waveforms of the actual test signals do not reach the adjustment high level VIHH and the adjustment low level VILL respectively within the time periods Tf and Tr but reach substantially the high level VIH and the low level VIL after elapse of the time periods of the minimum pulse width. Therefore, there are provided waveforms substantially the same as those when the waveforms are not influenced by timings by the characteristic of the transmission line 9. Therefore, in timings of reaching the threshold level VTH, Timing A in
As a result, as shown in
In this way, when the time periods of rise and fall are prolonged by the characteristic of the transmission line 9, the waveforms of the test signals that reaches DUT 4 through the transmission line 9 become slopes (more gradual than expected slopes) of completing fall and rise by time period width of time periods Tf2 and Tr2 longer than expected time periods different from the slopes of the expected waveforms shown in
In this respect, in the semiconductor test system 10 according to the present embodiment, during the time periods of the minimum pulse width when the waveform of the test signal arises from the low level to the high level and when the waveform of the test signal falls from the high level to the low level, the driver 2 outputs the signals of the voltage values of the adjustment high level VIHH and the adjustment low level VILL set by the adjustment DA converters 15 and 16. Therefore, even when the time period of fall is prolonged by the characteristic of the transmission line 9, there are provided expected waveforms substantially the same as those when the slopes of rise and fall of the waveforms are not influenced by the characteristic of the transmission line 9. Therefore, a failure of the signal applied to DUT 4 by the timing error does not arise.
In the above-described embodiment, there may be provided an adjustment control portion for variably controlling the voltage values of the adjustment high level VIHH and the adjustment low level VILL set by the adjustment DA converters 15 and 16. By such a configuration, even when the characteristic is changed by changing the transmission line 9 or the like, the voltage values of the adjustment high level VIHH and the adjustment low level VILL can be pertinently changed in accordance therewith.
Further, in one embodiment of the present invention, there may be provided a high level storing portion for storing a plurality of kinds of voltage values of the adjustment high level by the adjustment DA converter 15. In this case, there may be provided a high level selecting portion for selecting the voltage value stored in the storing portion and setting the voltage value to the voltage value of the signal of the high level inputted by the driver 2. Similarly, in one embodiment of the present invention, there may be provided a low level storing portion for storing a plurality of kinds of the voltage values of the adjustment low level by the adjustment DA converter 16. In this case, there may be provided a low level selecting portion for selecting any of the voltage values stored in the low level storing portion and setting the voltage value to the voltage value of the signal of the low level inputted by the driver 2. Also by such a constitution, the voltage value of the adjustment high level VIHH and the voltage value of the adjustment low level VILL can be changed in accordance with the change in the transmission line 9 or the like.
In one embodiment of the present invention, the voltage values of the adjustment high level and the adjustment low level respectively set by the adjustment DA converters 15 and 16 may be set in accordance with not only the characteristic of the transmission line 9 but also a characteristic such as a relay and a connector, which is interposed on a line from the driver 2 to DUT 4 and can influence on the waveform of the test signal.
Although in one embodiment of the present invention, the test signal is generated by PG&TG1 and is inputted to DUT 4 by way of the driver 2, the embodiment is not limited thereto but the configuration of the present embodiment can be used even in other signal or waveform so far as when some signal is inputted to an external circuit from the driver 2 by way of the transmission line 9.
Although in one embodiment of the present invention, the adjustment DA converters 15 and 16 set the waveform of the test signal to the voltage values of the adjustment high level and the adjustment low level respectively only during the time periods of the minimum pulse width in rising and in falling, the embodiment is not limited to the time width but may set the voltages by a plurality of pulse widths.
While there has been described in connection with the exemplary embodiments of the present invention, it will be obvious to those skilled in the art that various changes and modification may be made therein without departing from the present invention. It is aimed, therefore, to cover in the appended claim all such changes and modifications as fall within the true spirit and scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-264758 | Sep 2006 | JP | national |
