Semiconductor wafer, semiconductor chip, semiconductor device, and wafer testing method

Abstract

A semiconductor wafer of the present invention includes switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad. The semiconductor wafer also includes switch control pads which are provided in the scribing region or the semiconductor chips. Voltages of the switch control pads are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer. The switch control pads are provided with signals whose voltages are different from the substrate voltage so that the switch circuits are turned on. Moreover, each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an entire semiconductor wafer (P-type substrate) of one embodiment of the present invention.

FIG. 2 is a diagram illustrating a magnified arbitrary part of the semiconductor wafer and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

FIG. 3 is a circuit diagram illustrating one example of a configuration of a switch circuit provided in each of the chips.

FIG. 4 is a diagram illustrating a state of the chips under a wafer test.

FIG. 5 is a diagram illustrating a magnified arbitrary part of a semiconductor wafer (N-type substrate) of the one embodiment of the present invention and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

FIG. 6 is a diagram illustrating a state of the chips, formed on the semiconductor wafer as illustrated in FIG. 5, under a wafer test.

FIG. 7 is a diagram illustrating a magnified arbitrary part of a semiconductor wafer (P-type substrate) of another embodiment of the present invention and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

FIG. 8 is a diagram illustrating another example of a configuration of the semiconductor wafer as illustrated in FIG. 7.

FIG. 9 is a diagram illustrating a magnified arbitrary part of a conventional semiconductor wafer and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

FIG. 10 is a diagram illustrating a magnified arbitrary part of a semiconductor wafer (P-type substrate) of yet another embodiment of the present invention and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

FIG. 11 is a diagram illustrating an example of a configuration of a selector circuit provided in each of the chips formed on the semiconductor wafer as illustrated in FIG. 10.

FIG. 12 is a diagram illustrating a magnified arbitrary part of a semiconductor wafer (P-type substrate) of still another embodiment of the present invention and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

FIG. 13 is a diagram illustrating a magnified arbitrary part of a conventional semiconductor wafer and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

FIG. 14 is a diagram illustrating a magnified arbitrary part of a conventional semiconductor wafer and briefly illustrating an internal configuration of chips formed on the semiconductor wafer.

Claims

1. A semiconductor wafer on which (i) a plurality of semiconductor chips are formed so as to be arranged and aligned lengthways and crosswise and (ii) test pads for use in wafer test are provided in a scribing region that is a reserved region for dicing, the semiconductor wafer comprising: switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad; andswitch control pads, provided in the scribing region or the semiconductor chips, whose voltages are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer, said switch control pads receiving signals whose voltages are different from the substrate voltage so that said switch circuits are turned on, wherein:each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips.

2. The semiconductor wafer as set forth in claim 1, wherein: each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to a plurality of said switch circuits of each of the adjacent semiconductor chips; andfor each of the semiconductor chips provided are a plurality of said switch control pads each of which is connected to a different combination of said switch circuits.

3. The semiconductor wafer as set forth in claim 1, wherein: each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to a plurality of said switch circuits of each of the adjacent semiconductor chips; andfor each of the semiconductor chips provided are (a) a plurality of said switch control pads and (b) a selector circuit for selecting one or more switch circuits to be turned on among said switch circuits of each of the semiconductor chips, according to a combination of the signals respectively provided to the switch control pads.

4. The semiconductor wafer as set forth in claim 3, wherein: the selector circuit and a power supply pad of the selector circuit are provided in the scribing region.

5. A wafer testing method of a semiconductor wafer including: a plurality of semiconductor chips formed so as to be arranged and aligned lengthways and crosswise;test pads for use in wafer test, being provided in a scribing region that is a reserved region for dicing;switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad; andswitch control pads, provided in the scribing region or the semiconductor chips, whose voltages are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer, said switch control pads receiving signals whose voltages are different from the substrate voltage so that said switch circuits are turned on, wherein:each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips,wherein:a probe needle is brought into contact with at least one of the switch control pads so that at least one of the switch circuits of a semiconductor chip to be tested only is turned on among the semiconductor chips; anda probe needle is brought into contact with the test pad so that electrical characteristics of the semiconductor chip to be tested are measured.

6. The wafer testing method as set forth in claim 5, wherein: each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to a plurality of said switch circuits of each of the adjacent semiconductor chips; andfor each of the semiconductor chips provided are a plurality of said switch control pads each of which is connected to a different combination of said switch circuits.

7. The wafer testing method as set forth in claim 5, wherein: each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to a plurality of said switch circuits of each of the adjacent semiconductor chips; andfor each of the semiconductor chips provided are (a) a plurality of said switch control pads and (b) a selector circuit for selecting one or more switch circuits to be turned on among said switch circuits of each of the semiconductor chips, according to a combination of the signals respectively provided to the switch control pads.

8. The wafer testing method as set forth in claim 7, wherein: the selector circuit and a power supply pad of the selector circuit are provided in the scribing region.

9. A semiconductor chip cut from a semiconductor wafer including: a plurality of semiconductor chips formed so as to be arranged and aligned lengthways and crosswise;test pads for use in wafer test, being provided in a scribing region that is a reserved region for dicing;switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad; andswitch control pads, provided in the scribing region or the semiconductor chips, whose voltages are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer, said switch control pads receiving signals whose voltages are different from the substrate voltage so that said switch circuits are turned on, wherein:each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips.

10. A semiconductor device comprising a semiconductor chip cut from a semiconductor wafer including: a plurality of semiconductor chips formed so as to be arranged and aligned lengthways and crosswise;test pads for use in wafer test, being provided in a scribing region that is a reserved region for dicing;switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad; andswitch control pads, provided in the scribing region or the semiconductor chips, whose voltages are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer, said switch control pads receiving signals whose voltages are different from the substrate voltage so that said switch circuits are turned on, wherein:each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips.