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1. Field of the Invention
This invention relates to monolithic dynamic random access memory array circuitry and, more particularly, to techniques for sense amp equilibration.
2. Description of the Prior Art
Monolithic dynamic random access memory (DRAM) devices are well known. Within a DRAM, data is transported between sense amp and array on a complementary-logic bitline. After a read or refresh cycle, the complementary-logic bitline pairs are equilibrated to match each other, and biased to a predetermined voltage so they can be properly read by their sense amp in a future cycle.
During a read or refresh cycle, a selected data cell is connected to its bitline, raising or lowering the bitline from its bias voltage. Its sense amp then senses the small voltage difference between the new bitline level and its bias level, and amplifies that difference to a full logic one or logic zero level. In this way, the infinitesimal charge of a tiny memory cell is captured and presented to the rest of the chip and consequently to the outside world. The charge of the data cell is also refreshed by the amplified voltage level on the bitline. The bitline equilibration and bias circuitry is commonly considered to be part of the sense amp circuitry.
It is also known that circuit area, sometimes called “real estate”, is at a premium. The smaller a device can be made, the faster it is likely to be, and more economical to manufacture. Consequently, semiconductor engineers and mask designers all over the world perpetually strive to reduce circuit size in order to stay cost competitive.
In a DRAM device, the memory array by far takes the most real estate. Second to the memory array in size are the sense amps and related circuitry. Even a small area reduction for a single sense amp is multiplied across all the sense amps, and chip size consequently can be significantly reduced, thus improving cost competitiveness.
Blodgett, in patent U.S. Pat. No. 6,466,499 B1, herein incorporated by reference, shows typical DRAM technology, and is state-of-the-art, indicated by its very recent issue date of Oct. 15, 2002. Conventional three-transistor sense amp equilibrate and bias circuits are shown as elements 50a and 50b in
In Blodgett, equilibrate transistor 54 is gated by equilibrate signal EQa to short complementary-logic bitlines D0 and D0* together, thus equilibrating them. EQa also gates bias transistors 56 and 58, so that bias transistor 56 shorts bitline D0 to node Veq, and so that bias transistor 58 shorts bitline D0* to node Veq. D0 and D0* are thus biased to the voltage on node Veq.
For clarity and ease of comparison, in the present specification, prior art is represented in the present application in
In
Typical prior art as illustrated in
Further, as shown in
Zagar, in patent US RE35,825, herein incorporated by reference, is a prior art attempt to avoid problems due to row-to-column shorts, and to reduce transistor count. There is no equilibrate transistor, as that function is taken over by biasing transistors QnA/QnB being activated simultaneously. As shown in Zagar
Performance in Zagar is compromised because both BLs are shorted (equilibrated) through two series n-channel transistors (Q1A and Q1B, for example), instead of through a single transistor, thus doubling equilibrate time. Two series transistors of one width will have half of the drive of a single transistor of the same width, hence slower equilibration performance. The biasing speed is not as critical as the equilibrate speed. Zagar thus reduces transistor count, but at the expense of slowing equilibration time.
Disclosed herein is a new DRAM complementary-logic bitline equilibration and biasing circuit, which has the distinct advantage of being implemented using less real estate than prior art, thus lowering the manufacturing cost of the DRAM.
Specifically, this is accomplished by eliminating one of the bias transistors per bitline pair. Said transistor has not been hitherto recognized as redundant.
This allows a smaller circuit layout which significantly reduces the area of sense amps and related circuitry, while preserving identical control requirements and performance.
List of Drawing Figures:
Please refer to
BL and BLn are bitlines in a typical complementary-logic bitline pair, within a typical DRAM chip. Transistors Q1 and Q2 and current limiting device QL function as bitline pair equilibrate and bias circuitry, the function of which is well-known in the art.
Equilibrate transistor Q1 is gated by equilibrate node EQ, and is also connected to BL and BLn, so that when Q1 is activated by EQ, BL and BLn are shorted together through Q1. Biasing transistor Q2 is gated by equilibrate node EQ, and is also connected to BL and to the drain terminal of current limiting device QL, so that when Q2 is activated by EQ, BL is shorted to QL. The source terminal of QL is connected to bias node Vbias.
QL is a resistive device well known in the art, such as a long-L transistor, and its function is to limit current flow, so that if a bitline has a fault, Vbias is not depleted of charge and is still able to bias healthy bitlines.
Equilibrate signal EQ gates equilibrate transistor Q1, and biasing transistor Q2. When activated, equilibrate transistor Q1 shorts BL and BLn together. And when activated, biasing transistor Q2 shorts BL to biasing node Vbias through current limiting device QL. Because Q1 and Q2 are activated simultaneously, BLn is shorted to BL, which is shorted to Vbias (through current limiting device QL), thus simultaneously equilibrating and biasing both BL and BLn.
In all respects, the inventive is controlled the same as in prior art.
The difference between this circuit and prior art is that prior art uses two bias transistors, Q2 and Q3 (as shown in
Referring to inventive layout in
The prior art layout of
For purposes of this application, in regard to layout, ‘next to’ refers to an orientation wherein an element can be placed between duplicate equilibrating circuitry blocks, allowing interstitial location between repeating blocks. This is illustrated in
This is also illustrated in
While there is shown and described the present preferred embodiment of the invention, it is to be distinctly understood that this invention is not limited thereto but may be variously embodied to practice within the scope of the following claims.
For example, bias transistor Q2 can be connected to BL rather than BLn. The equilibrate circuitry can be used in other sense amps not connected to BLs but to a data path, for example, so by ‘bitline pair’, a data path is also circumscribed. The inventive circuitry is also valid, independent of location of isolation devices between the array and sense amps: that is, the inventive circuitry is valid on either side of array isolation devices. Adding a two-terminal n-channel device in place of the three-terminal n-channel device Q3 to balance BL and BLn more closely will still be within the scope of the invention. Also, current limiting device QL may or may not be required, depending on overall circuit design of the chip. So when the Vbias node is indicated connected to a biasing voltage circuit, a current limiting device may or may not be a part of that biasing voltage circuit. In this case, PPLUG can then be located ‘next to’ Vbias, rather than QL, resulting in the same inventive intent of reducing circuit length.
Clearly, other layouts may be conceived which express the reduced real estate requirements of the inventive circuitry. Such layouts are expressions of the inventive circuitry and are therefore within the scope of this invention. Also, though the above description discloses many details, these details should not be understood to limit the current invention. Obvious variations such as a minor change in logic design, addition of passive devices, or a modified scheme for writing and reading data, while making use of the structures, functions, or methods of the current invention, would fall within the scope of the patent rights claimed by the inventor. Therefore the scope of the invention should be limited only by the appended claims and their legal equivalents.