Patent Application
20250210096
This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0180297 filed on Dec. 13, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated by reference herein in their entirety.
Example embodiments relate generally to semiconductor integrated circuits, and more particularly to sense amplifier circuits of semiconductor memory devices, and semiconductor memory devices including the same.
Semiconductor memory devices may be divided into two categories depending upon whether or not they retain stored data when disconnected from a power supply. These fall into two categories: nonvolatile memory devices, which keep their stored data even after being disconnected from the power source, and volatile memory devices, which lose their recorded data. Volatile memory devices can read and write data quickly, but when they shut down, the data they contain could be gone. Nonvolatile memory devices can be used to store data that needs to be kept around since the contents are retained even after the device is powered down.
Semiconductor memory devices may include a plurality of memory cells. It may be necessary to precharge bitlines and complimentary bitlines to a precharge voltage, carry out a charge sharing operation, and observe variations in the bitlines' and complementary bitlines' voltage levels in order to identify data contained in the memory cells. Sense amplifiers then may receive and amplify the voltage differences between the bitlines and the complementary bitlines to detect the data stored in the memory cells.
At least one example embodiment of the present disclosure provides a sense amplifier circuit capable of efficiently preventing defect and reducing size.
At least one example embodiment of the present disclosure provides a semiconductor memory device including the sense amplifier circuit.
According to example embodiments, a sense amplifier circuit includes a plurality of bitline sense amplifiers. Each of the plurality of bitline sense amplifiers includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer circuit. The amplifying circuit is electrically connected to a bitline and a complementary bitline, senses a voltage difference between the bitline and the complementary bitline, and adjusts a voltage of a sensing bitline and a complementary sensing bitline based on the voltage difference. The isolation circuit electrically connects the bitline and the complementary bitline with the complementary sensing bitline and the sensing bitline, respectively. The offset cancellation circuit electrically connects the bitline and the complementary bitline to the sensing bitline and the complementary sensing bitline, respectively. The equalizer circuit equalizes the bitline and the complementary bitline to a precharge voltage. The equalizer circuit includes an equalizing transistor that has a source, a gate configured to receive an equalizing signal, and a drain. An active region is formed such that sources of equalizing transistors of a first bitline sense amplifier and a second bitline sense amplifier are connected to each other and sources of equalizing transistors of the first bitline sense amplifier and a third bitline sense amplifier are separated from each other.
According to example embodiments, a semiconductor memory device includes a memory cell array and a sense amplifier circuit. The memory cell array includes a plurality of memory cells. The sense amplifier circuit includes a plurality of bitline sense amplifiers connected to the plurality of memory cells. Each of the plurality of bitline sense amplifiers includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer circuit. The amplifying circuit is electrically connected to a bitline and a complementary bitline, senses a voltage difference between the bitline and the complementary bitline, and adjusts a voltage of a sensing bitline and a complementary sensing bitline based on the voltage difference. The isolation circuit electrically connects the bitline and the complementary bitline with the complementary sensing bitline and the sensing bitline, respectively. The offset cancellation circuit electrically connects the bitline and the complementary bitline to the sensing bitline and the complementary sensing bitline, respectively. The equalizer circuit equalizes the bitline and the complementary bitline to a precharge voltage. The equalizer circuit includes an equalizing transistor that has a source, a gate configured to receive an equalizing signal, and a drain. An active region is formed such that sources of equalizing transistors of a first bitline sense amplifier and a second bitline sense amplifier are connected to each other and sources of equalizing transistors of the first bitline sense amplifier and a third bitline sense amplifier are separated from each other.
According to example embodiments, a sense amplifier circuit includes a plurality of bitline sense amplifiers. Each of the plurality of bitline sense amplifiers includes an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer circuit. The amplifying circuit is electrically connected to a bitline and a complementary bitline, senses a voltage difference between the bitline and the complementary bitline based on a first control signal and a second control signal, and adjusts a voltage of a sensing bitline and a complementary sensing bitline based on the voltage difference. The isolation circuit electrically connects the bitline and the complementary bitline with the complementary sensing bitline and the sensing bitline, respectively, based on an isolation signal. The offset cancellation circuit electrically connects the bitline and the complementary bitline to the sensing bitline and the complementary sensing bitline, respectively, based on an offset cancellation signal. The equalizer circuit is electrically connected to the complementary sensing bitline, and equalizes the bitline and the complementary bitline to a precharge voltage. The equalizer circuit includes an equalizing transistor that has a source configured to receive the precharge voltage, a gate configured to receive an equalizing signal, and a drain electrically connected to the complementary sensing bitline. Sources of first and second equalizing transistors included in first and second bitline sense amplifiers that are adjacent to each other are connected to each other, and a first active region corresponding to the sources of the first and second equalizing transistors is integrally formed. Sources of third and fourth equalizing transistors included in the third and fourth bitline sense amplifiers that are adjacent to each other and spaced apart from the first and second bitline sense amplifiers are connected to each other, and a second active region corresponding to the sources of the third and fourth equalizing transistors is integrally formed. The sources of the first and second equalizing transistors and the sources of the third and fourth equalizing transistors are separated from each other, and an active cut region is formed between the first and second active regions to separate the first active region from the second active region.
In the sense amplifier circuit and the semiconductor memory device according to example embodiments, some of the sources of the equalizing transistors included in the bitline sense amplifiers and the corresponding active regions may be separated. For example, the sources of the equalizing transistors included in the same bitline sense amplifier group may be electrically connected to each other, and the sources of the equalizing transistors included in the different bitline sense amplifier groups may be electrically separated from each other. Accordingly, defects or failures in the sense amplifier circuit may be prevented and a size of the sense amplifier circuit may be reduced, as compared with the conventional sense amplifier circuit.
Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application.
Referring to
In some example embodiments, as will be described with reference to
Each of the plurality of bitline sense amplifiers BLSA may be connected to a bitline and a complementary bitline, and may include an amplifying circuit, an isolation circuit, an offset cancellation circuit and an equalizer circuit. A detailed circuit configuration of each bitline sense amplifier will be described with reference to
The plurality of bitline sense amplifiers BLSA may be divided or classified into a plurality of bitline sense amplifier groups 101, 102 and 103. For example, the first bitline sense amplifier group 101 may include two or more bitline sense amplifiers BLSA, the second bitline sense amplifier group 102 may include two or more bitline sense amplifiers BLSA, and the K-th bitline sense amplifier group 103 may include two or more bitline sense amplifiers BLSA, where K is a positive integer greater than or equal to two.
The plurality of bitline sense amplifiers BLSA may receive a precharge voltage VBL. For example, the precharge voltage VBL may be provided to the equalizer circuit. For example, as will be described with reference to
In some example embodiments, sources of the equalizing transistors of bitline sense amplifiers BLSA may be entirely separated and partially connected each other. For example, sources of equalizing transistors included in bitline sense amplifiers in the same bitline sense amplifier group may be connected to each other, and sources of equalizing transistors included in bitline sense amplifiers in different bitline sense amplifier groups may be separated or isolated from each other.
For example, as illustrated in
In other words, when the plurality of bitline sense amplifiers BLSA include a first bitline sense amplifier, a second bitline sense amplifier adjacent to the first bitline sense amplifier, and a third bitline sense amplifier adjacent to the second bitline sense amplifier, and when the first and second bitline sense amplifiers are included in the same bitline sense amplifier group and the first and third bitline sense amplifiers are included in different bitline sense amplifier groups, an active region may be formed such that sources of equalizing transistors of the first bitline sense amplifier and the second bitline sense amplifier are electrically connected to each other, and sources of equalizing transistors of the first bitline sense amplifier and the third bitline sense amplifier are electrically separated or isolated from each other because the first and the third bitline sense amplifiers are in a different bitline sense amplifier group.
In some example embodiments, as will be described with reference to
Referring to
In an example of
For example, the first and second bitline sense amplifiers BLSA11 and BLSA12, which are a pair of bitline sense amplifiers, may be disposed or arranged adjacent to each other, and may form or may be included in a first group of bitline sense amplifiers. For example, the third and fourth bitline sense amplifiers BLSA21 and BLSA22, which are another pair of bitline sense amplifiers, may be disposed or arranged adjacent to each other, may be spaced apart from the first and second bitline sense amplifiers BLSA11 and BLSA12, and may form or may be included in a second group of bitline sense amplifiers.
As described with reference to
Although
In a conventional sense amplifier circuit, sources of all equalizing transistors included in all bitline sense amplifiers were connected to each other.
In the sense amplifier circuit according to example embodiments, however, some of the sources of the equalizing transistors included in the bitline sense amplifiers and the corresponding active regions may be separated. For example, the plurality of bitline sense amplifiers may be divided into several bitline sense amplifier groups, the sources of the equalizing transistors included in the same bitline sense amplifier group may be electrically connected to each other, and the sources of the equalizing transistors included in the different bitline sense amplifier groups may be electrically separated from each other. Accordingly, defects or failures in the sense amplifier circuit may be prevented and a size of the sense amplifier circuit may be reduced, as compared with the conventional sense amplifier circuit in which the sources of all equalizing transistors are connected to each other.
Referring to
In
The bitline sense amplifier 110a may be connected to a bitline BL and a complementary bitline BLB disposed opposite to the bitline BL, and may be connected to a control line 111 and a complementary control line 112 disposed opposite to the control line 111. The bitline sense amplifier 110a may be connected to a first memory cell MC1 through the bitline BL and a second memory cell MC2 through the complementary bitline BLB, respectively. For example, the bitline sense amplifier 110a, the first memory cell MC1 and the second memory cell MC2 may constitute a semiconductor memory device.
The first memory cell MC1 may include a cell transistor CT1 that is connected to a wordline WLi and the bitline BL, respectively and a cell capacitor CC1 connected to a ground voltage VSS. The second memory cell MC2 may include a cell transistor CT2 that is connected to a wordline WLj and the complementary bitline BLB, respectively, and a cell capacitor CC2 connected to the ground voltage VSS.
Each of the amplifying circuit 121 and 122 may be electrically connected to the bitline BL and the complementary bitline BLB, may sense a voltage difference between the bitline BL and the complementary bitline BLB based on a first control signal LA and a second control signal LAB, and may adjust a voltage of a sensing bitline SBL and a complementary sensing bitline SBLB based on the sensed voltage difference.
In some example embodiments, the amplifying circuit 121 and 122 may include a p-type amplifier 121 and an n-type amplifier 122. The p-type amplifier 121 may include a first p-type metal oxide semiconductor (PMOS) transistor MP1 and a second PMOS transistor MP2, and the n-type amplifier 122 may include a first n-type metal oxide semiconductor (NMOS) transistor MN1 and a second NMOS transistor MN2. However, in another example, the amplifying circuit 121 may be n-type amplifier, the amplifying circuit 122 may be p-type amplifier.
The first PMOS transistor MP1 may be connected between the control line 111 to which the first control signal LA is provided and the sensing bitline SBL (e.g., between a first node N1 and the sensing bitline SBL). In this case the first PMOS transistor MP1 may include a gate (or a gate electrode or a control electrode) connected to the complementary sensing bitline SBLB (or a fourth node N4). The second PMOS transistor MP1 may be connected between the control line 111 and the complementary sensing bitline SBLB. In this case, the second PMOS transistor MP2 may include a gate connected to the sensing bitline SBL (or a third node N3).
The first NMOS transistor MN1 may be connected between the complementary control line 112 to which the second control signal LAB is provided and the sensing bitline SBL (e.g., between a second node N2 and the sensing bitline SBL). In this case, the first NMOS transistor MN1 may include a gate connected to the bitline BL (or a fifth node N5). The second NMOS transistor MN2 may be connected between the complementary control line 112 and the complementary sensing bitline SBLB. In this case, the second NMOS transistor MN2 may include a gate connected to the complementary bitline BLB (or a sixth node N6).
The offset cancellation circuit 131 may be electrically connected between the bitline BL and the sensing bitline SBL based on an offset cancellation signal P1. Similarly, the offset cancellation circuit 132 may be electrically connected between the complementary bitline BLB and the complementary sensing bitline SBLB based on an offset cancellation signal P1.
The offset cancellation circuit 131 may include a first offset cancellation transistor OC1, and the offset cancellation circuit 132 may include and a second offset cancellation transistor OC2. In this case, the first offset cancellation transistor OC1 may be connected between the bitline BL and the sensing bitline SBL, and may include a gate to receive the offset cancellation signal P1. Similarly, the second offset cancellation transistor OC2 may be connected between the complementary bitline BLB and the complementary sensing bitline SBLB, and may include a gate to receive the offset cancellation signal P1.
The isolation circuit 135 may be electrically connected between the bitline BL and the complementary bitline BLB with the complementary sensing bitline SBLB and the sensing bitline SBL, respectively, based on an isolation signal P2.
In this case, the isolation circuit 135 may include a first isolation transistor ISO1 and a second isolation transistor ISO2. The first isolation transistor ISO1 may be connected between the bitline BL and the complementary sensing bitline SBLB, and the first isolation transistor ISO1 may include a gate to receive the isolation signal P2. The second isolation transistor ISO2 may be connected between the complementary bitline BLB and the sensing bitline SBL, and the second isolation transistor ISO2 may include a gate to receive the isolation signal P2.
The equalizer circuit 141 may be electrically connected between the precharge voltage VBL and the complementary sensing bitline SBLB, and may equalize the bitline BL and the complementary bitline BLB to the precharge voltage VBL based on an equalizing signal PEQ. In this case, the equalizer circuit 141 may include an equalizing transistor EQ. The equalizing transistor EQ may include a source (or a first electrode), a gate to receive the equalizing signal PEQ, and a drain (or a drain electrode or a second electrode). As described above, the sources of the equalizing transistors EQ included in the same bitline sense amplifier group may be electrically connected to each other, and the sources of the equalizing transistors EQ included in the different bitline sense amplifier groups may be electrically separated from each other.
Referring to
As depicted in
A region where the equalizing transistor EQ, the second offset cancellation transistor OC2, the second isolation transistor ISO2 and the second NMOS transistor MN2 among the components included in bitline sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 are formed may include or may be divided into a first region 20, a second region 30 adjacent to the first region 20, and a third region 40 adjacent to the second region 30. In this case, the first region 20 may be disposed on the second region 30, and the second region 20 may be disposed on the third region 30 along the second direction D2.
The bitline sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 may include active regions AR11, AR12, AR13, AR14, AR21, AR22, AR23, and AR24 that are formed in the semiconductor substrate 10, and may include gate patterns 21, 31, 32, 41, 42, 43, and 44 that are formed on the semiconductor substrate 10 and the active regions AR11, AR12, AR13, AR14, AR21, AR22, AR23, and AR24.
The active region AR11 may be disposed in the first region 20, and may have a rectangular shape with long sides parallel to the first direction D1 and short sides parallel to the second direction D2 in a plan view. The active regions AR12 and AR13 may be disposed in the first region 20 and the second region 30, and each of the active regions AR12 and AR13 may have a rectangular shape with long sides parallel to the second direction D2 and short sides parallel to the first direction D1 in a plan view. The active regions AR12 and AR13 may be disposed below the active region AR11 along the second direction D2, and may be spaced apart from each other along the first direction D1. In this case, one portion of the active region AR12 may be disposed in the first region 20, and the other portion of the active region AR12 may be disposed in the second region 30. Similarly, one portion of the active region AR13 may be disposed in the first region 20, and the other portion of the active region AR13 may be disposed in the second region 30. The active region AR14 may be disposed in the third region 40, and may be spaced apart from the active regions AR12 and AR13 along the second direction D2. For convenience of illustration, the active regions AR11, AR12, and AR13 are described as separate regions, however, example embodiments are not limited thereto. For example, the active regions AR11, AR12, and AR13 may be formed integrally to form one active region.
Arrangements and shapes of the active regions AR21, AR22, AR23 and AR24 may be substantially the same as those of the active regions AR11, AR12, AR13 and AR14. For example, the active region AR21 may be disposed in the first region 20, the active regions AR22 and AR23 may be disposed in the first region 20 and the second region 30, and the active region AR24 may be disposed in the third region 40. In addition, the active regions AR22 and AR23 may be disposed below the active region AR21 along the second direction D2, and the active region AR24 may be spaced apart from the active regions AR22 and AR23 along the second direction D2.
The gate pattern 21 may extend along the first direction D1 on the active regions AR12 and AR13 and the active regions AR22 and AR23 in the first region 20, and may receive the equalizing signal PEQ. The gate patterns 31 and 32 may extend along the first direction D1 on the active regions AR12 and AR13 and the active regions AR22 and AR23 in the second region 30, may be spaced apart from each other along the second direction D2, and may receive the offset cancellation signal P1 and the isolation signal P2, respectively. The gate patterns 41 and 42 may extend along the second direction D2 on the active region AR14 in the third region 40, and may be spaced apart from each other along the first direction D1. The gate patterns 43 and 44 may extend along the second direction D2 on the active region AR24 in the third region 40, and may be spaced apart from each other along the first direction D1.
The active regions AR11, AR12, AR13, and AR14 and the gate patterns 21, 31, 32, 41, and 42 may correspond to the equalizing transistor EQ, the second offset cancellation transistor OC2, the second isolation transistor ISO2 and the second NMOS transistor MN2 that are included in the bitline sense amplifiers BLSA11 and BLSA12.
For example, the active regions AR11, AR12 and AR13 in the first region 20 and the gate pattern 21 in the first region 20 may correspond to the equalizing transistors EQ of the bitline sense amplifiers BLSA11 and BLSA12. In this case, the active regions AR11, AR12 and AR13 in the first region 20 and the gate pattern 21 in the first region 20 may constitute the equalizing transistors EQ of the bitline sense amplifiers BLSA11 and BLSA12. The active region AR12 in the second region 30 and the gate pattern 31 in the second region 30 may correspond to or constitute the second offset cancellation transistor OC2 of the bitline sense amplifier BLSA11. In this case, the active region AR12 in the second region 30 and the gate pattern 31 in the second region 30 may constitute the second offset cancellation transistor OC2 of the bitline sense amplifier BLSA11.The active region AR13 in the second region 30 and the gate pattern 31 in the second region 30 may correspond to the second offset cancellation transistor OC2 of the bitline sense amplifier BLSA12. In this case, the active region AR13 in the second region 30 and the gate pattern 31 in the second region 30 may constitute the second offset cancellation transistor OC2 of the bitline sense amplifier BLSA12. The active region AR12 in the second region 30 and the gate pattern 32 in the second region 30 may correspond to the second isolation transistor ISO2 of the bitline sense amplifier BLSA11, and the active region AR13 in the second region 30 and the gate pattern 32 in the second region 30 may correspond to the second isolation transistor ISO2 of the bitline sense amplifier BLSA12. In this case, the active region AR12 in the second region 30 and the gate pattern 32 in the second region 30 may constitute or form the second isolation transistor ISO2 of the bitline sense amplifier BLSA11, and the active region AR13 in the second region 30 and the gate pattern 32 in the second region 30 may constitute or form the second isolation transistor ISO2 of the bitline sense amplifier BLSA12. The active region AR14 in the third region 40 and the gate pattern 41 in the third region 40 may correspond to the second NMOS transistor MN2 of the bitline sense amplifier BLSA11, and the active region AR14 in the third region 40 and the gate pattern 42 in the third region 40 may correspond to the second NMOS transistor MN2 of the bitline sense amplifier BLSA12. In this case, the active region AR14 in the third region 40 and the gate pattern 41 in the third region 40 may constitute the second NMOS transistor MN2 of the bitline sense amplifier BLSA11, and the active region AR14 in the third region 40 and the gate pattern 42 in the third region 40 may constitute the second NMOS transistor MN2 of the bitline sense amplifier BLSA12.
Similarly, the active regions AR21, AR22, AR23 and AR24 and the gate patterns 21, 31, 32, 43 and 44 may correspond to the equalizing transistor EQ, the second offset cancellation transistor OC2, the second isolation transistor ISO2 and the second NMOS transistor MN2 that are included in the bitline sense amplifiers BLSA21 and BLSA22.
Some active regions AR11 and AR14 for the bitline sense amplifiers BLSA11 and BLSA12 may be connected to each other and may be formed integrally, and thus the bitline sense amplifiers BLSA11 and BLSA12 may be disposed adjacent to each other and may constitute a pair. Likewise, some active regions AR21 and AR24 for the bitline sense amplifiers BLSA21 and BLSA22 may be connected to each other and may be formed integrally, and thus the bitline sense amplifiers BLSA21 and BLSA22 may be disposed adjacent to each other and may constitute a pair. In another example, all active regions AR11, AR12, AR13 and AR14 for the bitline sense amplifiers BLSA11 and BLSA12 and all active regions AR21, AR22, AR23 and AR24 for the bitline sense amplifiers BLSA21 and BLSA22 may be separated from each other, and thus the bitline sense amplifiers BLSA11 and BLSA12 may be arranged to be spaced apart from the bitline sense amplifiers BLSA21 and BLSA22.
In some example embodiments, to separate the sources of the equalizing transistors EQ of the bitline sense amplifiers BLSA11 and BLSA12 from the sources of the equalizing transistors EQ of the bitline sense amplifiers BLSA21 and BLSA22, e.g., to separate the active region AR11 and the active region AR21 from each other, an active cut region ACR1 may be formed between the active region AR11 and the active region AR21. For example, in a manufacturing process, the active regions AR11 and AR21 may be formed integrally, and then the active cut region ACR1 may be formed between the active regions AR11 and AR21 to separate the active regions AR11 and AR21 from each other.
Conventionally, the active regions AR11 and AR21 were connected to each other and formed integrally. However, in the sense amplifier circuit according to example embodiments, the active regions AR11 and AR21 may be separated from each other by forming the active cut region ACR1, and thus the defects in the sense amplifier circuit may be prevented and the size of the sense amplifier circuit may be reduced. In addition, the equalizing transistor EQ and the second cancellation removal transistor OC2 may be formed in adjacent active region (or the same active region), and thus the size of the sense amplifier circuit may be further reduced.
Referring to
In the semiconductor substrate 10, the active regions AR11 and AR12 (or the first region 20) may be defined by a device isolation region STI, and doped regions 23a and 23b serving as sources and drains of the equalizing transistors EQ of the bitline sense amplifiers BLSA11 and BLSA12 may be formed. For example, the doped regions 23a and 23b may be N+ doped regions, the doped region 23a may be included in the active region AR11, and the doped region 23b may be included in the active region AR12. Thereafter, a gate insulating layer 21a and the gate pattern 21 disposed on the gate insulating layer 21 serving as gates of the equalizing transistors EQ may be sequentially stacked on the semiconductor substrate 10 along the third direction D3 (e.g., thickness direction).
A first direct contact DC1 may be disposed on the doped region 23a included in the active region AR11, and may be electrically connected to the doped region 23a. In this case, the first direction contact DC1 may be in direct contact with the doped region 23a. A first bitline metal pattern BLMP1 may be disposed on the first direct contact DC1, and may be electrically connected to the first direct contact DC1. A second direct contact DC2 may be disposed on the first bitline metal pattern BLMP1, and may be electrically connected to the first bitline metal pattern BLMP1. A second bitline metal pattern BLMP2 may be disposed on the second direct contact DC2, and may be electrically connected to the second direct contact DC2. In this case, the second bitline metal pattern BLMP2 may be electrically connected to the doped region 23a.
Therefore, the precharge voltage VBL may be provided to the doped region 23a (e.g., to the active region AR11) through the second bitline metal pattern BLMP2, the second direct contact DC2, the first bitline metal pattern BLMP1 and the first direct contact DC1.
Referring to
In the semiconductor substrate 10, a doped region 24a which serves as sources of the equalizing transistors EQ of the bitline sense amplifiers BLSA21 and BLSA22 may be formed. For example, the doped region 24a may be an N+ doped region, and may be included in the active region AR21. The active cut region ACR1 may be formed between the active regions AR11 and AR21. In this case, the active cut region ACR1 may be formed between the doped regions 23a and 24a.
A third direct contact DC3 may be disposed on the doped region 24a included in the active region AR21 along the third direction D3, and may be electrically connected to the doped region 24a. A third bitline metal pattern BLMP3 may be disposed on the third direct contact DC3, and may be electrically connected to the third direct contact DC3. A fourth direct contact DC4 may be disposed on the third bitline metal pattern BLMP3, and may be electrically connected to the third bitline metal pattern BLMP3. The second bitline metal pattern BLMP2 may extend to be disposed on the fourth direct contact DC4, and may be electrically connected to the fourth direct contact DC4. In this case, the second bitline metal pattern BLMP2 may be electrically connected to the doped regions 23a and 24a.
Therefore, the precharge voltage VBL may be provided to the doped region 24a (e.g., to the active region AR21) through the second bitline metal pattern BLMP2, the fourth direct contact DC4, the third bitline metal pattern BLMP3 and the third direct contact DC3.
As described above, a two-stacked BP structure in which direct contacts and bitline metal patterns are stacked in two layers may be applied employed or adopted to the sense amplifier circuit according to example embodiments. Accordingly, the precharge voltage VBL may be efficiently provided to the active regions AR11 and AR21 while the active cut region ACR1 is formed to separate the active regions AR11 and AR21.
Referring to
An example of
The conductive pattern 27 may be spaced apart from the gate pattern 21 along the second direction D2, and may partially overlap the first region 20. The conductive pattern 27 may extend in the first direction D1. In this case, the conductive pattern 27 may be partially disposed on the active cut region ACR1 along the third direction D3. The conductive pattern 27 may transmit the precharge voltage VBL, and may apply the precharge voltage VBL to the source of the equalizing transistor EQ.
Referring to
An insulating layer 27a and the conductive pattern 27 may be sequentially stacked on the device isolation region STI and the doped region 23a along the third direction (e.g., thickness direction), and may be spaced apart from the gate insulating layer 21a and the gate pattern 21 disposed on the gate insulating layer 21a. The first direct contact DC1 may be electrically connected to the doped region 23a serving as the sources of the equalizing transistors EQ by penetrating at least a portion of a wiring structure including the conductive pattern 27 and the insulating layer 27a in the third direction D3. Since the precharge voltage VBL is applied to the conductive pattern 27, the precharge voltage VBL may be provided to the sources of the equalizing transistors EQ through the first direct contact DC1.
As described above, the doped region 23a serving as the sources of the equalizing transistors EQ may be electrically connected to the conductive pattern 27 through the first direct contact DC1 that penetrates at least a portion of the wiring structure including the conductive pattern 27 and the insulating layer 27a, and the conductive pattern 27 may receive the precharge voltage VBL and may provide the precharge voltage VBL to the doped region 23a through the first direct contact DC1. Since the precharge voltage VBL does not need to be connected to the doped region 23a through an extra metal contact, a width of the bitline metal patterns may be reduced, and a pitch corresponding to a gap between the bitline metal patterns may be increased. Accordingly, the size of the bitline sense amplifier may be reduced, and a degree of wiring freedom may be increased.
Referring to
An example of
The equalizer circuit 142 may be connected between the precharge voltage VBL and the sensing bitline SBL, and may equalize the bitline BL and the complementary bitline BLB to the precharge voltage VBL based on the equalizing signal PEQ. The equalizer circuit 142 may include the equalizing transistor EQ. The equalizing transistor EQ may include a source, a gate to receive the equalizing signal PEQ, and a drain. As described above, the sources of the equalizing transistors EQ included in the same bitline sense amplifier group may be electrically connected to each other, and the sources of the equalizing transistors EQ included in the different bitline sense amplifier groups may be electrically separated from each other.
In some example embodiments, when each of the bitline sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 included in the sense amplifier circuit 100a has the circuit configuration illustrated in
Referring to
In an example of
For example, the first to fourth bitline sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 may be included in a first group of bitline sense amplifiers. Among the first group of bitline sense amplifiers, the first and second bitline sense amplifiers BLSA31 and BLSA32 may be disposed adjacent to each other, the third and fourth bitline sense amplifiers BLSA33 and BLSA34 may be disposed adjacent to each other, and the first and second bitline sense amplifiers BLSA31 and BLSA32 may be spaced apart from the third and fourth bitline sense amplifiers BLSA33 and BLSA34. In this case, sources of first equalizing transistors included in the first group of bitline sense amplifiers may be electrically connected to each other, and active regions corresponding to the sources of the first equalizing transistors may be integrally formed.
Similarly, the fifth to eighth bitline sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 may be included in a second group of bitline sense amplifiers. Among the second group of bitline sense amplifiers, the fifth and sixth bitline sense amplifiers BLSA41 and BLSA42 may be disposed adjacent to each other, the seventh and eighth bitline sense amplifiers BLSA43 and BLSA44 may be disposed adjacent to each other, and the fifth and sixth bitline sense amplifiers BLSA41 and BLSA42 may be spaced apart from the seventh and eighth bitline sense amplifiers BLSA43 and BLSA44. In this case, sources of second equalizing transistors included in the second group of bitline sense amplifiers may be electrically connected to each other, and active regions corresponding to the sources of the second equalizing transistors may be integrally formed.
The sources of the first equalizing transistors and the sources of the second equalizing transistors may be electrically isolated from each other, and the active regions corresponding to the sources of the first equalizing transistors and the active regions corresponding to the sources of the second equalizing transistors may be separated from each other.
Referring to
Configurations of the bitline sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 may be substantially the same as the configurations of the bitline sense amplifiers BLSA11, BLSA12, BLSA21, and BLSA22 of
In some example embodiments, to separate the sources of the equalizing transistors EQ of the bitline sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 and the corresponding active regions from the sources of the equalizing transistors EQ of the bitline sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44 and the corresponding active regions, an active cut region ACR2 may be formed. In this case, the active cut region ACR2 may be formed between the bitline sense amplifiers BLSA31, BLSA32, BLSA33, and BLSA34 and the bitline sense amplifiers BLSA41, BLSA42, BLSA43, and BLSA44.
Although example embodiments are described based on the examples where the number of bitline sense amplifiers included in one bitline sense amplifier group is two and four, example embodiments are not limited thereto, and the number of bitline sense amplifiers included in one bitline sense amplifier group may be variously determined according to example embodiments.
Referring to
Referring to
Referring to
Firstly, the precharge voltage VBL may be provided to the sensing bitline SBL in response to the equalizing signal PEQ having the logic high level (e.g., High), and then, the first and second offset cancellation transistors OC1 and OC2 may be turned on in response to the offset cancellation signal P1 having the logic high level, and the first and second isolation transistors ISO1 and ISO2 may be turned on in response to the isolation signal P2 having the logic high level (e.g., High). Therefore, the bitline BL, the complementary bitline BLB, the sensing bitline SBL, and the complementary sensing bitline SBLB may be connected to one node and may be charged to the precharge voltage VBL. In this case, the first and second control signals LA and LAB may be charged to the precharge voltage VBL. Thus, in this case, the bitline BL, the complementary bitline BLB, the sensing bitline SBL, the complementary sensing bitline SBLB, and the first and second control signals LA and LAB may be equally charged to the precharge voltage VBL.
Referring to
The first and second isolation transistors ISO1 and ISO2 may be turned off in response to the isolation signal P2 having the logic low level, and the first and second offset cancellation transistors OC1 and OC2 may be turned on in response to the offset cancellation signal P1 having the logic high level. In this case, the first control signal LA may be transitioned from the precharge voltage VBL to an internal power supply voltage VINTA, and the second control signal LAB may be transitioned from the precharge voltage VBL to a ground voltage VSS. The internal power supply voltage VINTA may be a voltage supplied to a memory cell array (e.g., a memory cell array 300 in
In the bitline sense amplifier 110a, for example, the first and second PMOS transistors MP1 and MP2 and the first and second NMOS transistors MN1 and MN2 may have different threshold voltages (e.g., Vth) than each other due to a variation in manufacturing processes, temperature, or the like. In this case, the bitline sense amplifier 110a may cause offset noise due to the differences between the threshold voltages of the first and second PMOS transistors MP1 and MP2 and the first and second NMOS transistors MN1 and MN2.
In some example embodiments, an offset of the bitline sense amplifier 110b may be compensated based on the offset cancelling operation, which will be described with reference to first to fourth examples (e.g., Cases I to IV) in
In a first example (e.g., Case I) of
In a second example (e.g., Case II) of
In a third example (e.g., Case III) of
In a fourth example (e.g., Case IV) of
In the above-described first to fourth examples (e.g., Cases I to IV), the voltage of the complementary bitline BLB may be increased or decreased to the predetermined level as compared to the voltage of the bitline BL, and thus the bitline BL and the complementary bitline BLB may have a predetermined voltage difference. Such voltage difference may be interpreted as an offset voltage due to the offset noise. This means that the offset noise of the bitline sense amplifier 110a may be cancelled by causing the bitline BL and the complementary bitline BLB to have a voltage difference by the offset voltage. In other words, the bitline sense amplifier 110a may compensate for the offset by the offset cancelling operation.
Referring to
The first and second offset cancellation transistors OC1 and OC2 and the first and second isolation transistors ISO1 and ISO2 may be turned off in response to the offset cancellation signal P1 and the isolation signal P2 having the logic low level (e.g., Low as shown in
For example, when data having a value of ‘1’ is stored in the memory cell, the voltage of the bitline BL may increase by a predetermined level during the charge sharing operation. On the other hand, when data having a value of ‘0’ is stored in the memory cell, the voltage of the bitline BL may decrease by a predetermined level during the charge sharing operation.
Referring to
When the charge sharing operation described in
For example, when data having a value of ‘1’ is stored in the memory cell, the voltage of the sensing bitline SBL may increase to the internal power supply voltage VINTA, and the voltage of the complementary sensing bitline SBLB may decrease to the ground voltage VSS during the pre-sensing operation. On the other hand, when data having a value of ‘0’ is stored in the memory cell, the voltage of the sensing bitline SBL may decrease to the ground voltage VSS, and the voltage of the complementary sensing bitline SBLB may increase to the internal power supply voltage VINTA.
For example, during the pre-sensing operation, the bitline BL and the complementary bitline BLB, and the sensing bitline SBL and the complementary sensing bitline SBLB may be disconnected from each other by the first and second isolation transistors ISO1 and ISO2 and the first and second offset cancellation transistors OC1 and OC2. When the bitline sense amplifier 110a is separated from the bitline BL and the complementary bitline BLB, a coupling effect between the bitlines BL may be reduced and a sensing rate may be improved.
Referring to
The first and second isolation transistors ISO1 and ISO2 may be turned on in response to the isolation signal P2 having the logic high level (e.g., High as shown in
In some example embodiments, after the pre-sensing operation, the sensing bitline pair SBL and SBLB of the bitline sense amplifier 110a may be connected to a data line, and data may be output to a local sense amplifier, a global sense amplifier, and/or a data I/O buffer (e.g., the data I/O buffer 295 in
As described above, the bitline sense amplifier 110a may compensate for the offset of the bitline sense amplifier 110a by the offset cancelling operation, may minimize the coupling between the bitlines BL by the pre-sensing operation, and thus an effective sensing margin thereof may be improved.
Referring to
In
In a first time interval from t0 to t1, the bitline sense amplifier 110a may perform the precharging operation (S110). In this case, the equalizing signal PEQ, the offset cancellation signal P1, and the isolation signal P2 may have the logic high level (e.g., High), and the bitline pair BL and BLB and the sensing bitline pair SBL and SBLB may be precharged to the precharge voltage VBL. In addition, the first control signal LA and the second control signal LAB may be precharged to the precharge voltage VBL.
In a second time interval from t1 to t2, the bitline sense amplifier 110a may perform the offset cancelling operation (S120). In this case, the isolation signal P2 may have the logic low level (e.g., Low). The first control signal LA may increase from the precharge voltage VBL to the internal power supply voltage VINTA, and the second control signal LAB may decrease from the precharge voltage VBL to the ground voltage VSS. The bitline sense amplifier 110a may perform the above-described offset cancelling operation. Since the threshold voltage of the first NMOS transistor MN1 is greater than the threshold voltage of the second NMOS transistor MN2 by the offset voltage Vos, the voltage of the complementary bitline BLB may be greater than the voltage of bitline BL by the offset voltage Vos during the offset cancelling operation. Therefore, the voltages of the bitline BL and the complementary bitline BLB may have a difference by the offset voltage Vos, and thus the offset noise of the bitline sense amplifier 110a may be cancelled.
In a third time interval from t2 to t3, the bitline sense amplifier 110a may perform the charge sharing operation (S130). In this case, the offset cancellation signal P1 and the isolation signal ISO may have the logic low level (e.g., Low), the wordline (e.g., the wordline WLi) connected to the memory cell may be activated, and the charge sharing operation may be performed between the electric charges stored in the cell capacitor of the memory cell and the electric charges stored in the bitline. Since data having the value of ‘1’ is stored in the memory cell, the voltage level of the bitline BL may increase by a predetermined level during the charge sharing operation.
In a fourth time interval from t3 to t4, the bitline sense amplifier 110a may perform the pre-sensing operation (S140). In this case, the first control signal LA may be transitioned from the precharge voltage VBL to the internal power supply voltage VINTA, and the second control signal LAB may be transitioned the precharge voltage VBL to the ground voltage VSS. Thus, in the bitline sense amplifier 110a, the voltage of the sensing bitline SBL may increase to the internal power supply voltage VINTA, and the voltage of the complementary sensing bitline SBLB may decrease to the ground voltage VSS, based on the voltage difference between the bitline BL and the complementary bitline BLB.
In a fifth time interval from t4 to t5, the bitline sense amplifier 110a may perform the restoring operation (S150). In this case, the isolation signal P2 may have the logic high level (e.g., High) and the offset cancellation signal P1 may remain to the logic low level (e.g., Low), and first and second isolation transistors ISO1 and ISO2 may be turned on. The bitline pair BL and BLB and the sensing bitline pair SBL and SBLB may be respectively connected to each other, and the bitline pair BL and BLB may be charged or discharged to the voltage level of the sensing bitline pair SBL and SBLB.
Referring to
The memory cell array 300 may include first to eighth bank arrays 310 to 380 (e.g., first to eighth bank arrays 310, 320, 330, 340, 350, 360, 370, and 380). The row decoder 260 may include first to eighth bank row decoders 260a to 260h connected to the first to eighth bank arrays 310 to 380, respectively. In this case, the first bank row decoder 260a may be connected to the first bank array 310, and the eighth bank row decoder 260h may be connected to the eighth bank array 380. The column decoder 270 may include first to eighth bank column decoders 270a to 270h connected to the first to eighth bank arrays 310 to 380 respectively. In this case, the first bank column 270a may be connected to the first bank array 310, and the eighth bank column decoder 270h may be connected to the eighth bank array 380. The sense amplifier circuit 285 may include first to eighth bank sense amplifiers 285a to 285h connected to the first to eighth bank arrays 310 to 380 respectively. In this case, the first bank sense amplifiers 285a may be connected to the first bank array 310, and the eighth bank sense amplifiers 285h may be connected to the eighth bank array 380.
The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form first to eighth banks, respectively. Each of the first to eighth bank arrays 310 to 380 may include a plurality of wordlines WL, a plurality of bitlines BL, and a plurality of memory cells MC intersected with the wordlines WL and the bitlines BL.
Although
The address register 220 may receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller (e.g., a memory controller 520 in
The bank control logic circuit 230 may generate bank control signals in response to the bank address BANK_ADDR. One of the first to eighth bank row decoders 260a to 260h and one of the first to eighth bank column decoders 270a to 270h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.
The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h respectively.
The activated one of the first to eighth bank row decoders 260a to 260h may decode the row address RA generated from the row address multiplexer 240, and may activate in the corresponding bank array a wordline WL corresponding to the row address RA. For example, the activated bank row decoder may generate a wordline driving voltage and may apply the wordline driving voltage to the wordline WL corresponding to the row address RA.
The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In some example embodiments, in a burst mode, the column address latch 250 may generate column addresses that increment from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address to the first to eighth bank column decoders 270a to 270h respectively.
The activated one of the first to eighth bank column decoders 270a to 270h may decode the column address COL_ADDR generated from the column address latch 250 and may control the I/O gating circuit 290 to output data corresponding to the column address COL_ADDR.
The I/O gating circuit 290 may include circuitry configured to gate input/output data. The I/O gating circuit 290 may further include read data latches configured to store data generated from the first to eighth bank arrays 310 to 380 and may also include write control devices for writing data to the first to eighth bank arrays 310 to 380 respectively.
Data DAT read from one of the first to eighth bank arrays 310 to 380 may be sensed by a sense amplifier connected to the one bank array from which the data DAT is to be read, and may be stored in the read data latches. The data DAT stored in the read data latches may be provided to the memory controller via the data I/O buffer 295. Data DAT to be written in one of the first to eighth bank arrays 310 to 380 may be provided to the I/O gating circuit 290 via the data I/O buffer 295 from the memory controller, and the I/O gating circuit 290 may write the data DAT in the one bank array through the write drivers.
The control logic circuit 210 may control operations of the semiconductor memory device 200. For example, the control logic circuit 210 may generate control signals for the semiconductor memory device 200 to perform the write operation and/or the read operation. The control logic circuit 210 may include a command decoder 211 and a mode register 212. In this case, the command decoder 211 may decode a command CMD received from the memory controller, and the mode register 212 may set an operation mode of the semiconductor memory device 200. In some example embodiments, operations described herein as being performed by the control logic circuit 210 may be performed by processing circuitry. For example, the command decoder 211 may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, and a chip selection signal.
The sense amplifier circuit 285 may be the sense amplifier circuit according to example embodiments, and may include the plurality of bitline sense amplifiers with the separation structure in which some sources and/or some active regions of the equalizing transistors are separated. Accordingly, the defects in the sense amplifier circuit 285 may be prevented and the size of the sense amplifier circuit 285 may be reduced.
Referring to
Although the semiconductor memory device according to example embodiments is described based on a DRAM, the semiconductor memory device according to example embodiments may be any volatile memory device, and/or any nonvolatile memory device, e.g., a static random access memory (SRAM), a flash memory, a phase-change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), or the like.
Referring to
The semiconductor memory device 540 is controlled by the memory controller 520. For example, based on requests from a host (not illustrated), the memory controller 520 may store (e.g., write or program) data into the semiconductor memory device 540, or may retrieve (e.g., read or sense) data from the semiconductor memory device 540.
The semiconductor memory device 540 may include a sense amplifier circuit 550. The sense amplifier circuit 550 may be the sense amplifier circuit according to example embodiments, and may include the plurality of bitline sense amplifiers with the separation structure in which some sources and/or some active regions of the equalizing transistors are separated. Accordingly, the defects in the sense amplifier circuit 550 may be prevented and the size of the sense amplifier circuit 550 may be reduced.
The plurality of signal lines 530 may include control lines to transmit a control signal CTRL, command lines to transmit a command CMD, address lines to transmit an address ADDR, data input/output (I/O) lines, and power lines to transmit a power supply voltage PWR. In this case, the memory controller 520 may transmit the command CMD, the address ADDR, and the control signal CTRL to the semiconductor memory device 540 via the command lines, the address lines, and the control lines, may exchange data DAT with the semiconductor memory device 540 via the data I/O lines, and may transmit the power supply voltage PWR to the semiconductor memory device 540 via the power lines. Although not illustrated in
Referring to
The buffer chip 890 may control the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d and the PMIC 885, by a memory controller (e.g., the memory controller 520 in
The SPD chip 880 may be a programmable read only memory (PROM) (e.g., an electrically erasable PROM (EEPROM)). The SPD chip 880 may include initial information and/or device information DI of the memory module 800. In some example embodiments, the SPD chip 880 may include the initial information and/or the device information DI such as a module form, a module configuration, a storage capacity, a module type, an execution environment, and/or the like of the memory module 800.
When a memory system including the memory module 800 is booted up, the memory controller may read the device information DI from the SPD chip 880, and may recognize the memory module 800 based on the device information DI. The memory controller may control the memory module 800 based on the device information DI from the SPD chip 880. For example, the memory controller may recognize a type of the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d included in the memory module 800 based on the device information DI from the SPD chip 880.
Here, the circuit board 801 which is a printed circuit board (PCB) may extend in a second direction D2 perpendicular to a first direction D1. The circuit board 801 may include a first edge portion 803 and a second edge portion 805. The first edge portion 803 and the second edge portion 805 may extend in the first direction D1. The buffer chip 890 may be disposed on a center of the circuit board 801. However, in another example, the buffer chip 890 may be disposed on any portion of the circuit board 801. The plurality of semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d may be arranged in a plurality of rows between the buffer chip 890 and the first edge portion 803, and between the buffer chip 890 and the second edge portion 805. In some example embodiments, operations described herein as being performed by the buffer chip 890 may be performed by processing circuitry.
In this example, the semiconductor memory devices 851a to 851e and 852a to 852e may be arranged along a plurality of rows between the buffer chip 890 and the first edge portion 803. The semiconductor memory devices 853a to 853d and 854a to 854d may be arranged along a plurality of rows between the buffer chip 890 and the second edge portion 805. In this case, the plurality of semiconductor memory devices 851a to 851e and 852a to 852e may be disposed between the first edge portion 803 and the buffer chip 890. In addition, the plurality of semiconductor memory devices 853a to 853d and 854a to 854d may be disposed between the second edge portion 805 and the buffer chip 890. For example, the semiconductor memory devices 851a to 851d, 852a to 852d, 853a to 853d and 854a to 854d may be data chips storing normal data, and the semiconductor memory devices 851e and 852e may be as parity chips storing parity data or error correction code (ECC) data.
The buffer chip 890 may provide a command/address signal (e.g., CA) to the semiconductor memory devices 851a to 851e through a command/address transmission line 861, and may provide a command/address signal to the semiconductor memory devices 852a to 852e through a command/address transmission line 863. In addition, the buffer chip 890 may provide a command/address signal to the semiconductor memory devices 853a to 853d through a command/address transmission line 871, and may provide a command/address signal to the semiconductor memory devices 854a to 854d through a command/address transmission line 873.
The command/address transmission lines 861 and 863 may be connected in common to the module resistance unit 860 disposed to be adjacent to the first edge portion 803, and the command/address transmission lines 871 and 873 may be connected in common to the module resistance unit 870 disposed to be adjacent to the second edge portion 805. In this case, one end of the command/address transmission lines 861 and 863 may be connected to the buffer chip 890, and the other end of the command/address transmission lines 861 and 863 may be connected to the module resistance unit 860. Similarity, one end of the command/address transmission lines 871 and 873 may be connected to the buffer chip 890, and the other end of the command/address transmission lines 871 and 873 may be connected to the module resistance unit 870. Each of the module resistance units 860 and 870 may include a termination resistor Rtt/2 connected to a termination voltage Vtt.
The SPD chip 880 may be disposed to be adjacent to the buffer chip 890, and the PMIC 885 may be disposed between the semiconductor memory device 853d and the second edge portion 805. In another example, the PMIC 885 may be disposed on any portion of the circuit board 801. The PMIC 885 may generate a power supply voltage VDD based on an input voltage VIN from an external source, and may provide a power supply voltage VDD to the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d.
In some example embodiments, each of the semiconductor memory devices 851a to 851e, 852a to 852e, 853a to 853d, and 854a to 854d may be a DRAM device, and may include the sense amplifier circuit according to example embodiments.
Referring to
The application processor 910 may include a memory controller 911. The application processor 910 may execute applications such as at least one of a web browser, a game application, a video player, etc. The connectivity module 920 may perform wired and/or wireless communication with an external device.
The memory module 950 may store data processed by the application processor 910 and/or operate as a working memory. The memory module 950 may include a plurality of semiconductor memory devices (MD) 951, 952, 953, . . . , 95q (where q is a positive integer greater than three), and/or a buffer chip (RCD) 961. The memory module 950 may be the memory module 800 of
In some example embodiments, each of the semiconductor memory devices 951 to 95q may be a DRAM device, and may include the sense amplifier circuit according to example embodiments.
The nonvolatile memory device 940 may store a boot image for booting the electronic system 900. The user interface 930 may include at least one input device, such as a keypad, a touch screen, a touch pen, and at least one output device, such as a speaker, a display device, etc. The power supply 970 may supply an operating voltage to the electronic system 900.
The electronic system 900 or components of the electronic system 900 may be mounted using various types of packages.
The example embodiments may be applied to various electronic devices and systems that include the semiconductor memory devices. For example, the example embodiments may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, an automotive, etc.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0180297 | Dec 2023 | KR | national |
