Patent Grant
12190985
A sense amplifier circuit is a circuit in a semiconductor memory chip that amplifies a power signal of a memory cell. When reading data from a memory cell, the sense amplifier circuit accepts an input representing a data bit stored in the memory cell, and amplifies the input to a voltage level high enough to be recognizable by an external device so that the data bit of the memory cell can be properly read.
It is to be noted that the above information disclosed in this Background section is only for facilitating the understanding of the background of this invention and therefore may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
This invention relates generally to the field of semiconductor technologies and, more specifically, to a sense amplifier circuit and its operation methods.
In view of the limitations of existing technologies described above, this disclosure provides a sense amplifier circuit, a memory device, and related operation methods that address the aforementioned limitations.
One aspect of this invention is directed to a sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit coupled to the amplification circuit.
The amplification circuit may include a first inverting amplifier and a second inverting amplifier. The first inverting amplifier may be connected to a first bitline, and the second inverting amplifier may be connected to a second bitline. The amplification circuit may be configured to amplify a voltage signal applied between the first bitline and the second bitline. The compensation circuit may be coupled to the amplification circuit and configured to compensate an input-referred offset voltage of the amplification circuit by conducting charge injections to at least one of the first bitline and the second bitline.
Another aspect of this invention is directed to another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bitline, and a second inverting amplifier connected to a second bitline. The amplification circuit may be configured to amplify a voltage signal applied between the first bitline and the second bitline. The compensation circuit may be coupled to the amplification circuit and configured to compensate an input-referred offset voltage of the amplification circuit. The compensation circuit may be configured to conduct a charging operation to charge at least one of the first bitline and the second bitline. At the end of the charging operation, a voltage difference between near-ends of the first bitline and the second bitline may be larger than the input-referred offset voltage of the amplification circuit.
Another aspect of this invention is directed to yet another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bitline, and a second inverting amplifier connected to a second bitline. The amplification circuit may be configured to amplify a voltage signal applied between the first bitline and the second bitline during a signal amplification stage. The compensation circuit may be coupled to the first bitline, the second bitline, and the amplification circuit, and may be configured to compensate an input-referred offset voltage of the amplification circuit during an offset compensation stage. At least one of the first bitline and the second bitline may be connected, through the compensation circuit, to one of the outputs of the first inverting amplifier and the second inverting amplifier during the signal amplification stage, and the at least one of the first bitline and the second bitline may be connected to the other of the outputs of the first inverting amplifier and the second inverting amplifier during the offset compensation stage.
Another aspect of this invention is directed to yet another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bitline, and a second inverting amplifier connected to a second bitline. The amplification circuit may be configured to amplify a voltage signal applied between the first bitline and the second bitline during a signal amplification stage. The compensation circuit may be coupled to the amplification circuit, and may be configured to compensate an input-referred offset voltage of the amplification circuit during an offset compensation stage. A gain of the sense amplifier circuit may be larger than one during the offset compensation stage.
Another aspect of this invention is directed to yet another sense amplifier circuit. The sense amplifier circuit may include an amplification circuit and a compensation circuit. The amplification circuit may include a first inverting amplifier connected to a first bitline, and a second inverting amplifier connected to a second bitline. The amplification circuit may be configured to amplify a voltage signal applied between the first bitline and the second bitline during a signal amplification stage. The compensation circuit may be coupled to the amplification circuit, and may be configured to compensate an input-referred offset voltage of the amplification circuit during an offset compensation stage. The first inverting amplifier and the second inverting amplifier may be cross-coupled during the offset compensation stage.
Another aspect of this invention is directed to a memory device. The memory device may include a plurality of memory cells and a plurality of sense amplifier circuits. Each of the plurality of sense amplifier circuits may be the sense amplifier circuit of any of the aforementioned embodiments, and may be connected to one of the plurality of memory cells.
Another aspect of this invention is direct to an input-referred offset voltage compensation method, applicable to the sense amplifier circuit of any of the aforementioned embodiments. The method may include generating, by operating the first, the second, the third, and the fourth switch circuits, a compensation voltage between the first bitline and the second bitline to compensate the input-referred offset voltage of the amplification circuit.
Another aspect of this invention is directed to an input-referred offset voltage compensation method, applicable to an amplifier circuit. The method may include: connecting, through a control circuit coupled to the amplifier circuit, a first node of the amplifier circuit with a second node of the amplifier circuit to cause voltages on the first node and the second node to converge; separating, through the control circuit, the first node from the second node; determining a time of compensation; powering on the amplifier circuit for the time of compensation to generate a first signal and a second signal, wherein the first signal is generated at the first node, and the second signal is generated at the second node; and routing, through the control circuit, the first signal to the second node, and the second signal to the first node to compensate an input-referred offset voltage of the amplifier circuit.
Another aspect of this invention is directed to a method to operate a sense amplifier circuit. The sense amplifier circuit may be connected to a first bitline through a first bitline switch circuit, and connected to a second bitline through a second bitline switch circuit. The sense amplifier circuit may be configured to amplify a voltage signal applied between the first bitline and the second bitline. The method may include: while the sense amplifier circuit amplifying the voltage signal, disconnecting the sense amplifier circuit from the first bitline and the second bitline by operating the first bitline switch circuit and the second bitline switch circuit; keeping the sense amplifier circuit disconnected from the first bitline and the second bitline for a predetermined period of time; and reconnecting the sense amplifier circuit with the first bitline and the second bitline by operating the first bitline switch circuit and the second bitline switch circuit.
Another aspect of this invention is directed to a memory device operation method, applicable to a memory device. The method may include: conducing the aforementioned input-referred offset voltage compensation method on a plurality of amplifier circuits arranged on a first side of a wordline of the memory device; and conducting the aforementioned input-referred offset voltage compensation method on a plurality of amplifier circuits arranged on a second side of the wordline of the memory device. The second side may be opposing the first side.
Another aspect of this invention is directed to an input-referred offset voltage compensation method, applicable to an amplification circuit having a first sub-circuit and a second sub-circuit, and having an input-referred offset voltage. The method may include: generating, in response to a voltage signal, a first signal by the first sub-circuit on a first I/O of the amplification circuit, and a second signal by the second sub-circuit on a second I/O of the amplification circuit. A difference between the first signal and the second signal may reflect the input-referred offset voltage in the circuit. The method may further include connecting, by a compensation circuit coupled to the amplification circuit, the first signal to the second I/O, and the second signal to the first I/O to compensate the input-referred offset voltage.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of this invention.
The accompanying drawings, which are incorporated in and constitute a part of the description, illustrate embodiments consistent with this invention and, together with the description, serve to explain the disclosed principles. It is apparent that these drawings present only some embodiments of this invention and those of ordinary skill in the art may obtain drawings of other embodiments from them without exerting any creative effort.
Modern memory devices are increasingly miniaturized in size and power consumption, and the amount of electric charge in individual memory cell is only capable of generating a signal of small magnitude for representing data in the memory cell. Therefore a sense amplifier circuit that can properly amplify small input signals is of vital importance in modern memory devices.
However, due to inevitable variation in circuit characteristics, there exists an offset voltage in the sense amplifier circuit that may reduce the sensitivity of the sense amplifier circuit and the performance of the associated memory cell. Due to the offset voltage, a voltage difference between two bitlines of a sense amplifier circuit must be larger than a minimum voltage, known as minimum voltage margin, for a sense amplifier circuit to work properly. In other words, a sense amplifier circuit with an offset voltage may require a larger input signal than what is otherwise needed to produce a recognizable voltage level. Additionally, voltage pulling capabilities between the pull-up circuit and the pull-down circuit of a sense amplifier circuit may be different, which may also impact the performance of a sense amplifier circuit. Therefore, a sense amplifier circuit that can remedy the aforementioned deficiencies, including the offset voltage, is desired.
Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are presented to provide a full and thorough understanding of this invention and to fully convey the concepts of the exemplary embodiments to others skilled in the art. In addition, the described features, structures, and characteristics may be combined in any suitable manner in one or more embodiments. In the following detailed description, many specific details are set forth to provide a more thorough understanding of this invention. However, those skilled in the art will recognize that the various embodiments can be practiced without one or more of the specific details or with other methods, components, materials, or the like. In some instances, well-known structures, materials, or operations are not shown or not described in detail to avoid obscuring aspects of the embodiments.
Further, the drawings are merely illustrative of this invention and are not necessarily drawn to scale. Throughout the drawing, like reference numbers indicate identical or similar elements, so any duplicate description of them will be omitted. The represented blocks in the drawing are purely functional entities, which do not necessarily correspond to physically separated entities. In other words, these functional entities may be implemented as software, or entirely or in part in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.
The flowcharts represented in the drawings are merely illustrative and do not necessarily include all shown steps. For example, some of these steps may be divided, while some can be at least partially combined. Therefore, the actual order in which they are performed may vary depending on the actual conditions.
1. Sense Amplifier Circuit
As shown in
A sense amplifier circuit, however, may have an offset voltage that may affect the sensitivity of the circuit. The offset voltage may be caused by various factors, including but not limited to, deviation between threshold voltages of corresponding transistors in the cross-coupled inverters, mismatch between series resistance on source/drain nodes of the transistors, mismatch between structural sizes of the corresponding circuit components, carrier mobility mismatch, substrate bias, mismatch on conductance coefficients, and mismatch on node capacitances of corresponding transistors. In one example, the offset voltage may be caused by the difference between threshold voltages of corresponding transistors in two inverting amplifiers in the sense amplifier circuit. For example, due to the variation in the manufacturing process, the threshold voltage of a transistor in one inverter may be higher than the threshold voltage of a corresponding transistor in a coupling inverter in the sense amplifier circuit. As a result, an input signal to the sense amplifier circuit must be larger than a minimum voltage margin, which is determined by the offset voltage, for data in an associated memory cell to be properly read. In other words, the offset voltage reduces the sensitivity of the sense amplifier circuit. In this application, for the ease of description, all of the above-mentioned variations and mismatches are collectively referred to as the “mismatch” in the sense amplifier circuit.
The impact of the offset voltage to a sense amplifier circuit is further described with reference to
The methods and devices that compensate a sense amplifier circuit from a voltage compensation perspective (i.e., compensating the input-referred offset voltage) are disclosed in this application. This invention, however, is not limited in this regard. Based on the same inventive concept disclosed herein, methods and devices that compensate a sense amplifier circuit from a current compensation perspective (i.e., compensating the input-referred offset current) are contemplated, and these methods and devices are within the protection scope of this application.
This application first presents a sense amplifier circuit that compensates an input-referred offset voltage therein.
As shown in
More specifically, the amplification circuit may include the first inverting amplifier INV1 (dashed box INV1 in
In some embodiments, as shown in
In some embodiments, conducting charge injections to the first bitline BLa and the second bitline BLb may include: injecting a first charge generated by the first inverting amplifier INV1 to the second bitline BLb; and injecting a second charge generated by the second inverting amplifier INV2 to the first bitline BLa. The first charge and the second charge may generate a compensation voltage between the first bitline BLa and the second bitline BLb after a distribution of the first charge and the second charge on the bitlines settled. In this application, an electrical charge is “settled” on a bitline means the electrical charge has been fully propagated on the bitline, and details of this concept will be explained in greater details with reference to accompanying drawings in a later part of this application. The compensation voltage may be substantially equal to the input-referred offset voltage of the amplification circuit. In this application, a first voltage is “substantially equal” to a second voltage means the first voltage is within a certain range of the second voltage. The range may be, for example, ±10% or ±5% of the second voltage, and this invention is not limited in this regard. In one example, the compensation voltage generated by the first charge and the second charge may be within ±5% of the input-referred offset voltage of the sense amplifier circuit.
The first charge and the second charge may have same of different charge amounts, and same or different charge polarities. This invention is not limited in these regards.
In some embodiments, conducting charge injections to the first bitline BLa and the second bitline BLa may include: only injection the first charge generated by the first inverting amplifier INV1 to the second bitline BLb, or only injection the second charge generated by the second inverting amplifier INV2 to the first bitline BLa. In these scenarios, the first charge or the second charge may generate a compensation voltage between the first bitline BLa and the second bitline BLB after a distribution of the first charge or the second charge on the bitlines settled, and the compensation voltage may be substantially equal to the input-referred offset voltage of the amplification circuit.
The compensation circuit may include one or more capacitive elements. The capacitive elements may be elements that are capable of storage electrical charges, and may include, but not limited to, capacitors, diodes, fie-effect transistor (FET), metal-oxide-semiconductor field-effect transistor (MOSFET) that are capable of storing electrical charges. In one example, the one or more capacitive element may include a Ni capacitor or a bitline parasitic capacitor.
In some embodiments, as shown in
In some embodiments, each of the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 may be a switch and may be in one of “ON” or “OFF” statuses. This invention, however, is not limited herein. Other suitable circuits that can provide an on/off switch function may be used as the switch circuit.
In some embodiments, each of the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 may be implemented using one or more transistors. For example, each of the switch circuits may comprise an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a transmission gate. In that cases, other than an “ON” or “OFF” status, the switch circuit may also be in an intermediate conductive status depending on the conductive status of the transistors. A conductive state of each of these switch circuits may be controlled by applying a voltage on the corresponding transistors, such as on a gate terminal of corresponding NMOS transistor, PMOS transistor, or transmission gate.
Additionally, in some embodiments, the sense amplifier circuit may further include a switch control circuit (not shown in the drawings) coupled to the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4. The switch control circuit may be configured to control a conductive status of each of these switch circuits. In one example, the switch control circuit may control a conductive status of each of these switch circuits by applying a voltage on a gate terminal of a corresponding transistor in each of the switch circuits.
Referring to
The second inverting amplifier may comprise a third transistor M3 and a fourth transistor M4. Each of the third transistor M3 and the fourth transistor M4 may have a first terminal, a second terminal, and a gate terminal. The second terminal of the third transistor M3 and the first terminal of the fourth transistor M4 may both be connected to the first node a. The gate terminal of the third transistor M3 and the gate terminal of the fourth transistor M4 may both be connected to the second node b. The first terminal of the first transistor M1 and the first terminal of the third transistor may be connected to the voltage node sapwr, and the second terminal of the second transistor M2 and the second terminal of the fourth transistor M4 may be connected to the ground node sagnd.
In some embodiments, the first transistor M1 and the third transistor M3 may each have a first conductivity type, and the second transistor M2 and the fourth transistor M4 may each have a second conductivity type opposing the first conductivity type. For example, the first transistor M1 and the third transistor M3 may be P-type transistors, and the second transistor M2 and the fourth transistor M4 may be N-type transistors.
Referring to
In the aforementioned embodiments, the first inverting amplifier INV1 and the second inverting amplifier INV2 may each comprise two transistors. The first inverting amplifier INV1 and the second inverting amplifier INV2, however, may also be implemented by other suitable circuits, provided that the circuits can provide an inversion function. For example, the first inverting amplifier INV1 and the second inverting amplifier INV2 may each include three or more transistors. Detailed composition of the first inverting amplifier INV1 and the second inverting amplifier INV2 are not limited in this invention.
In the sense amplifier circuit in accordance with some embodiments of this invention, the first switch circuit S1 and the second switch circuit S2 may be connected with the first bitline BLa, and the third switch circuit S3 and the fourth switch circuit S4 may be connected with the second bitline BLb. By controlling each of the switch circuits to be on “ON” or “OFF” status, the first bitline BLa and the second bitline BLb may be connected to different internal components (e.g., inverting amplifiers) of the sense amplifier circuit.
In some embodiments, conducting charge injections to first bitline BLa and the second bitline BLb may include: conducting charge injections to the first bitline BLa and the second bitline BLb by operating the first, the second, the third, and the fourth switch circuits. The first charge and the second charge may, after settled on the bitlines, generate a compensation voltage between the first bitline BLa and the second bitline BLb to compensation the input-referred offset voltage in the amplification circuit, so that the performance of the associated memory device may be improved.
Based on the aforementioned sense amplifier circuit, this invention further provides a memory device.
In some embodiments, the plurality of sense amplifier circuits may be alternately arranged on a first side of the wordline and a second side of the wordline opposing the first side. Each of the sense amplifier circuits arranged on the first side of the wordline may be connected to one of the plurality of memory cells through the first bitline, and each of the sense amplifier circuits arranged on the second side of the wordline may be connected to one of the plurality of memory cells through the second bitline.
2. Operation Methods of the Sense Amplifier Circuits
Based on the aforementioned sense amplifier circuits, this invention further presents operation methods of the sense amplifier circuits, which compensate the input-referred offset voltage of the amplification circuits.
2.1 Compensate Input-Referred Offset Voltage in the Amplification Circuit
In one example, the sense amplifier circuit operation method may be performed on a sense amplifier circuit shown in
The sense amplifier circuit operation method may include generating, by operating the first, the second, the third, and the fourth switch circuits, a compensation voltage between the first bitline BLa and the second bitline BLb to compensate the input-referred offset voltage of the amplification circuit.
More specifically, referring to
In step S410, a sense amplifier circuit may be provided. The sense amplifier circuit may be a sense amplifier circuit in any of the aforementioned embodiments. Relevant parts in the aforementioned embodiments may be referred to for detail composition of the sense amplifier circuit, which will not be repeatedly described herein for the sake of conciseness.
In step S420, the first switch circuit S1, the second switch circuit S2, the third switch circuit S3, and the fourth switch circuit S4 may all be switched on, as shown in
In step S430, the second switch circuit S2 and the fourth switch circuit S4 may be switched off, while the first switch circuit S1 and the third switch circuit S3 remain on, as shown in
The first switch circuit S1 and the third switch circuit S3 may remain on for a Time of compensation (Toc). By choosing a proper Toc, the voltage difference between the first bitline BLa and the second bitline BLb at the end of the Toc, referred to as a compensation voltage, may reach a desired voltage level. In some embodiments, the desired voltage level may be a voltage level that reflects an input-referred offset voltage of the amplification circuit. In some embodiments, the input-referred offset voltage of the amplification circuit may be the difference between threshold voltages of corresponding transistors in the first inverting amplifier INV1 and the second inverting amplifier INV2, and the compensation voltage may reflect the difference between the threshold voltages. For example, the compensation voltage may be substantially equal to the input-referred offset voltage. The desired voltage level, however, may be any other value depending on specific needs, and this invention is not limited in this regard.
The aforementioned step S430 may also be understood as a charging process, in which the compensation circuit conducts a charging operation to inject charges to at least one of the first bitline BLa and the second bitline BLb. Upon the completion of the charging operation, the charges injected to the first bitline BLa and/or the second bitline BLb may settled on the bitlines, and voltage difference between near-ends of the first bitline BLa and the second bitline BLb may decrease during this process. Therefore, to sufficiently compensate the input-referred offset voltage, the voltage difference between near-ends of the first bitline BLa and the second bitline BLb may be larger than the input-referred offset voltage of the amplification circuit at the end of the charging operation. For example, the voltage difference may be 10%-40% larger than the input-referred offset voltage at the end of the charging operation. Thus, after the charges injected to the first bitline BLa and the second bitline BLb settled on the bitlines, the resulted voltage difference at the near-ends of the bitlines may be substantially equal to the input-referred offset voltage.
Next, in step S440, the first switch circuit S1 and the third switch circuit S3 may be switched off, resulting in all the four switch circuits being switched off. Thus the compensation voltage may be retained at the first bitline BLa and the second bitline BLb. In this step, the voltage at the voltage node sapwr may be returned to the initial up voltage, and the voltage at the ground node sagnd may be returned to the initial down voltage.
Next, in step S450, the second switch circuit S2 and the fourth switch circuit S4 may be switched on, while the first switch circuit S1 and the third switch circuit S3 remain off, as shown in
Referring to
In step S430, corresponding to time Comstart in
In step S430, the second switch circuit S2 and the fourth switch circuit S4 may remain off, and the first switch circuit S1 and the third switch circuit S3 may remain on for a duration of Toc. During this time, the voltage of the first bitline BLa and the voltage of the second bitline BLb continue to diverge, as shown in
Next, in step S440, corresponding to time Comend in
As shown in
In this case, as shown in
In step S450, the second switch circuit S2 and the fourth switch circuit S4 are switched on while the first switch circuit S1 and the third switch circuit S3 remain off (as shown in
As shown in
In the sense amplifier circuit operation method of this invention described above, all the four switch circuits are first switched on for a sufficiently long time to cause voltages on the first bitline BLa, the second bitline BLb, the first node a, and the second node b to converge to one voltage level. Then, the second switch circuit and the fourth switch circuit are switched off, while the first switch circuit and the third switch circuit remain on, for a duration of Toc. In this step, mismatches in the sense amplifier circuit (e.g., a difference in the threshold voltages of corresponding transistors) may result in a voltage difference (i.e., the compensation voltage) between the first bitline BLa and the second bitline BLb. By choosing a proper Toc, the compensation voltage may reflect the input-referred offset voltage of the amplification circuit (e.g., the compensation voltage may have a substantially same magnitude as the difference of the threshold voltages). Then the first switch circuit and the third switch circuit are switched off, to retain the compensation voltage on the first bitline BLa and the second bitline BLb. When the second switch circuit and the fourth switch circuit are subsequently switched on to amplify an input signal, the input signal is superimposed on the compensation voltage so that the input-referred offset voltage of the amplification circuit may be compensated. Thus, the performance of the associated memory device may be improved.
Inherent electrical characteristics of bitlines, such as bitline resistances RBL and bitline parasitic capacitance CBL, may affect a voltage on a bitline. The sense amplifier circuit operation method of this invention takes into consideration these effects, and thus improves the accuracy of the input-referred offset voltage compensation.
Referring to
In some embodiments, taken into consideration charge propagation on the bitlines, the voltages on the first bitline and the second bitline immediately after Toc may be larger (in term of magnitude) than the voltages needed to compensate the input-referred offset voltage.
In some embodiment, when the compensation circuit is configured to compensate the input-referred offset voltage by conducting charge injections to the first bitline and the second bitline, the charges injected to the bitlines (i.e., the first charge and the second charge) may be determined on the basis that the settled voltages on the first bitline BLa and the second bitline BLa (i.e., V1_settle and V2_settle, respectively) may compensate the input-referred offset voltage. The first charge and the second charge may be determined based on the electronic characteristics of the first bitline BLa and the second bitline BLb. More specifically, they may be determined based on factors including, but not limited to, bitline resistances RBL and bitline parasitic capacitance CBL associated with the first bitline BLa and the second bitline BLb. In some embodiments, a mathematical model may be established to depict the relationship between the injected charges to compensate the input-referred offset voltage and the electronic characteristics of the first bitline BLa and the second bitline BLb. Then the first charge and the second charge may be determined based on this mathematical model. The injected charges may be determined by other methods, and this invention is not limited in this regard. By taking into consideration charge propagation on the bitlines and the voltage deviations it causes, this method improves the accuracy of the input-referred offset voltage compensation.
It should be noted that,
Based on the aforementioned sense amplifier circuit operation method, this invention further provides a memory device operation method. The memory device in this operation method may include a wordline, a plurality of memory cells connected to the wordline, and a plurality of sense amplifier circuits each connected one of the plurality of memory cells. Each of the sense amplifier circuits may be the sense amplifier circuit of any one of the aforementioned embodiments. Relevant part in the aforementioned embodiments for the sense amplifier circuit may be referred to for detail composition of the sense amplifier circuit, which will not be repeatedly described herein for the sake of conciseness.
The plurality of sense amplifier circuits may be alternately arranged on a first side of the wordline and a second side of the wordline opposing the first side. The sense amplifier circuits arranged on the first side of the wordline may each have the first bitline connected to the corresponding memory cell, and the sense amplifier circuits arranged on the second side of the wordline may each have the second bitline connected to the corresponding memory cell.
The memory device operation method may further include: conducting a sense amplifier operation method for each of the sense amplifier circuits arranged on the first side of the wordline; and, subsequently, conducting the sense amplifier operation method for each of the sense amplifier circuits arranged on the second side of the wordline. The sense amplifier operation method may be the method described in the aforementioned embodiments, hence detail descriptions of the sense amplifier operation method are omitted herein for the sake of conciseness.
In the memory device operation method described above, the operation method that compensates the input-referred offset voltage of a sense amplifier circuit are first conducted for the sense amplifier circuits located on the first side of the wordline, and then conducted for the sense amplifier circuits located on the second side of the wordline. Thus, interference between the sense amplifier circuits located on different sides of the wordline may be reduced, if not eliminated.
2.2 Control Switch Circuits for Faster Read Speed
The sense amplifier circuit operation methods described above may further include methods to control the conductive statuses of the switch circuits of the sense amplifier circuit to improve read speed of data in a memory cell.
In some embodiments, the methods to control the conductive statuses of the switch circuits of the sense amplifier circuit may be conducted following the aforementioned sense amplifier circuit operation method. More specifically, the methods may be conducted following step S450 of the aforementioned methods (i.e., after the second switch circuit and the fourth switch circuit are switched on).
In some embodiments, one of the methods may include: after Step S450, disconnecting the sense amplifier circuit from the first bitline and the second bitline by operating the second switch circuit and the fourth switch circuit; keeping the sense amplifier circuit disconnected from the first bitline and the second bitline for a predetermined period of time; and reconnecting the sense amplifier circuit with the first bitline and the second bitline by operating the second switch circuit and the fourth switch circuit. This method will be described below in greater details.
Referring to
As shown in
As shown in
In some embodiments, the aforementioned methods to control the conductive statuses of the switch circuits of the sense amplifier circuit may also be conducted on a sense amplifier circuit without first performing the aforementioned sense amplifier circuit operation method. More specifically, the methods may be conducted on a sense amplifier circuit that is connected to a first bitline through a first bitline switch circuit, and connected to a second bitline through a second bitline switch circuit. The sense amplifier circuit may be configured to amplify a voltage signal applied between the first bitline and the second bitline.
One of the methods may include: while the sense amplifier circuit amplifying the voltage signal, disconnecting the sense amplifier circuit from the first bitline and the second bitline by operating the first bitline switch circuit and the second bitline switch circuit; keeping the sense amplifier circuit disconnected from the first bitline and the second bitline for a predetermined period of time; and reconnecting the sense amplifier circuit with the first bitline and the second bitline by operating the first bitline switch circuit and the second bitline switch circuit.
In some embodiments, in the aforementioned method, when reconnecting the sense amplifier circuit with the first bitline and the second bitline, each of the first bitline switch circuit and the second bitline switch circuit may be set at a partial conductive status.
2.3 Calibrate for Variation on Voltage Pulling Capabilities
This invention further provides a calibration circuit configured to perform a calibration operation to determine a pull-up circuit, a pull-down circuit, a pull-up voltage (Vpup) and a pull-down voltage (Vpdn) for a sense amplifier circuit.
As shown in
In some embodiments, in the duplicated inverting amplifier, each of the first duplicate transistor M10 and the second duplicate transistor M20 may have a first terminal, a second terminal, and a gate terminal. The gate terminal of the first duplicate transistor M10 may be connected to the gate terminal of the second duplicate transistor M20 at an output node z. The second terminal of the first duplicate transistor M10 may be connected with the first terminal of the second duplicate transistor M20, the first terminal of the first duplicate transistor M10 may be connected to a voltage node sapwr0, and the second terminal of the second duplicate transistor M20 may be connected to a ground node sagnd0.
The voltage node sapwr0 may be provided with a plurality of pull-up circuits with different voltage pull-up capabilities, and the ground node may be provided with a plurality of pull-down circuits with different voltage pull-down capabilities. One or more pull-up circuits from the plurality of pull-up circuits may be selected to be coupled to the voltage node sapwr0, and one or more pull-down circuits from the plurality of pull-down circuits may be selected to be coupled to the ground node sagnd0. A pull-up voltage may be provided to the duplicated inverting amplifier through the selected one or more pull-up circuits, and a pull-down voltage may be provided to the duplicated inverting amplifier through the selected one or more pull-down circuits.
As shown in
An output voltage of the duplicated inverting amplifier at the output node z may be sent to a feedback circuit. A calibration voltage may be provided to the feedback circuit to be compared with the output voltage. The calibration voltage may be a desired voltage at the node z. In one example, the calibration voltage may be half of a source voltage VH (i.e., ½ VH). An output of the feedback circuit may be provided to a calibration control circuit. The calibration control circuit may adjust, based on a comparison result between the calibration voltage and the output voltage, the pull-up voltage Vpup and the pull-down voltage Vpdn to cause the output voltage to tune towards the calibration voltage.
As shown in
In step S910, one or more candidate pull-up circuits may be selected from a plurality of candidate pull-up circuits, and one or more candidate pull-down circuits may be selected from a plurality of candidate pull-down circuits according to a calibration voltage. The one or more candidate pull-up circuits and the one or more candidate pull-down circuits may be selected to cause an output voltage at the output node z to approach the calibration voltage. More specific, the candidate pull-up circuits and the candidate pull-down circuits may be selected on the basis that they produce an output voltage at the output node z that is closer to the calibration voltage than any other combination of candidate pull-up circuits and candidate pull-down circuits. In this step, a candidate pull-up voltage Vpup may be provided to the selected one or more candidate pull-up circuits, and a candidate pull-down voltage Vpdn may be provided to the selected one or more candidate pull-down circuits.
In step S920, the pull-up voltage Vpup and the pull-down voltage Vpdn may be adjusted to cause the output voltage to further approach the calibration voltage.
In step S930, the adjusted pull-up voltage Vpup and the adjusted pull-down voltage Vpdn may be saved in one or more registers.
The candidate pull-up voltage Vpup and the candidate pull-down voltage Vpdn stored in the one or more registers may be used in the aforementioned method for compensating an input-referred offset voltage of a sense amplifier circuit. That is, in the aforementioned method, providing a pull-up voltage to the voltage node may comprise: coupling the selected one or more candidate pull-up circuits to the voltage node; and providing the adjusted candidate pull-up voltage through the selected one or more candidate pull-up circuits to the voltage node. Providing the pull-down voltage to the ground node may comprise: coupling the selected one or more candidate pull-down circuits to the ground node; and providing the adjusted candidate pull-down voltage through the selected one or more candidate pull-down circuits to the ground node.
Additionally, for a memory device including a plurality of sense amplifier circuits (i.e., a SA array), the candidate pull-up voltage and the candidate pull-down voltage stored in the one or more registered may be used as a pull-up voltage and a pull-down voltage, respectively, for each of the plurality of sense amplifier circuit.
In some embodiments, the calibration circuit may further include a timing unit configured for setting a fixed time interval, and the calibration circuit may be further configured to perform the calibration process repeatedly at the fixed time interval. Thus, the pull-up voltage Vpup and the pull-down voltage Vpdn may be periodically adjusted according to changed conditions (e.g., temperature) or operational needs. In some embodiments, the fixed time interval may be 100 ms.
In the calibration process described above, by selecting one or more proper pull-up circuits from a plurality of candidate pull-up circuits, selecting one or more proper pull-down circuits from a candidate plurality of pull-down circuits, and by adjusting the pull-up voltage Vpup and the pull-down voltage Vpdn, the output voltage of the duplicated inverting amplifier may be as close to the calibration voltage (e.g., ½ VH) as possible. Thus, the difference between the voltage pulling capabilities of the pull-up circuit and the pull-down circuit may be compensated.
3. Determination of Time of Compensation (Toc)
The Toc of the aforementioned compensation process may be chosen so that the voltage difference between the first bitline BLa and the second bitline BLb (i.e., the compensation voltage) at the end of step S430 may reflect an input-referred offset voltage of the sense amplifier circuit, so that the input-referred offset voltage may be properly compensated. For example, the voltage difference may have a substantially same magnitude with an input-referred offset voltage.
The Toc may be determined based on various factors including, but not limited to, the transconductance of the sense amplifier circuit as a whole Gm, the bitline resistance RBL, and the bitline parasitic capacitance CBL. That is, the Toc may be determined by an equation of:
Toc=f(Gm,RBL,CBL)
In some embodiments, when determining the Toc, charge propagation on the bitlines may be taken into consideration, and the Toc may be determined so that the charges injected to the first bitline BLa and the second bitline BLa may, after fully propagated on the bitlines, generate a compensation voltage between the bitlines that compensates the input-referred offset voltage.
The Toc of a sense amplifier circuit may be determined through different methods. In one embodiment, the Toc may be determined by first establishing a mathematical model to obtain an analytical solution for the Toc, and then calculating the Toc based on the analytical solution. In another embodiment, the Toc may be obtained through a lookup table of the Toc. More specifically, a lookup table of the Toc on different conditions may first be established based on experimental data. The lookup table may include a plurality of compensation durations, each corresponding to one specific condition (i.e., when each of the factors, such as the transconductance Gm, the bitline resistance RBL, and a bitline parasitic capacitor CBL, is at a specific value). Then, a current condition may be determined. Current condition may include current value for each of the aforementioned factors, which may include, by not be limited to the transconductance Gm, the bitline resistance RBL, and the bitline parasitic capacitor CBL. The Toc then may be determined by finding in the lookup table the compensation duration corresponding to the current condition.
In step S1010, an equalization (EQ) process may be conducted on a sense amplifier (SA) circuit. That is, the SA circuit may have its two input bitlines connected to reset the SA circuit.
In step S1020, the two input bitlines of the SA circuit are separated, and one of the input bitlines may be selected to be read data (e.g., 0 or 1) thereon.
In step S1030, an EQ process may be conducted the SA circuit to reset the SA circuit.
In step S1040, after the EQ process, one Time of compensation Ti from a Time of compensation series (Ti, i=1, 2, . . . ) may be selected and applied on the SA circuit.
In step S1050, after the Toc, the data on the selected input bitlines may be read.
In step S1060, the data read from the selected input bitline may be compared with the data read in step S1020 to determine whether a change has occurred (i.e., changing from 0 to 1, or from 1 to 0).
If the data has changed, then the method is completed, and Ti is the determined Time of compensation (step S1070 in
In some embodiments, the Time of compensation series (Ti, i=1, 2, . . . ) may include a plurality of monotonic increasing or decreasing values for Time of compensation.
4. Compensation Circuits for Constant Toc
The transconductance of the sense amplifier circuit Gm, the bitline resistance RBL, and the bitline parasitic capacitor CBL may change with changed conditions (e.g., temperature), which may affect the Toc and hence the accuracy of the compensation.
This invention further presents circuits and related methods that provide compensation to the transconductance of the sense amplifier circuit Gm, the bitline resistance RBL, and the bitline parasitic capacitor CBL, respectively, to accommodate for changed conditions, so that the Toc of an amplifier circuit may remain relatively unchanged.
In some embodiments, the transconductance compensation circuit may include two constant-Gm circuits, each respectively coupled with the pull-up circuit and the pull-down circuit of the sense amplifier circuit. Other circuits that can adjust a transconductance of the sense amplifier circuit according to external conditions may be used, and this invention is not limited in this regard.
In one example, a memory device may include a wordline, a plurality of memory cells connected to the wordline and a plurality of sense amplifier circuits each connected to one of the plurality of memory cells. The sense amplifier circuit herein may be a sense amplifier circuit in any one of the aforementioned embodiments. Relevant part in the aforementioned embodiments for the sense amplifier circuit may be referred to for detail composition of the sense amplifier circuit, which will not be repeatedly described herein for the sake of conciseness.
In some embodiments, in the memory device, each of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit in each of the plurality of sense amplifier circuits comprises an N-type metal-oxide-semiconductor (NMOS) transistor, a P-type metal-oxide-semiconductor (PMOS) transistor, or a transmission gate.
In some embodiments, the memory device may include a dummy bitline configured to generate a bias voltage applying on at least one of the first switch circuit, the second switch circuit, the third switch circuit, and the fourth switch circuit in each of the plurality of sense amplifier circuits. The bias voltage may control a conductive state of the corresponding switch circuit.
In some embodiments, as shown in
As shown in
In some embodiments, the memory device may be connected with a reference resistor, which may be a standard resistor whose resistance under a specific condition has been accurately determined. The resistance of the adjustable resistors may be adjusted based on measured resistance of the reference resistor under current condition to compensate the changed bitline resistance RBL. In one example, the reference resistor may be connected in a voltage-dividing circuit, and the resistance of the reference resistor under current condition may be determined by measuring the voltage on the reference resistor. Other suitable methods may also be used to measure the resistance of the reference resistor under current condition, and this invention is not limited in this regard.
As shown in
The memory device may further include a dummy bitline coupled to at least one of the adjustable capacitors and a capacitance control circuit. The capacitance control circuit may be configured to generate a capacitance control signal. The dummy bitline may be configured to transmit the capacitance control signal to the at least one of the adjustable capacitors for controlling a capacitance of the at least one adjustable capacitor. In one example, the capacitance control signal may be provide to the corresponding capacitor adjusting circuit to adjust the capacitance of the at least one adjustable capacitor. By adjusting the capacitance of the at least one adjustable capacitor according to changed external conditions, the capacitance connected on each bitline of the sense amplifier circuit may be adjusted to compensate the bitline parasitic capacitor CBL.
In some embodiments, the memory device may include a memory cell matrix comprising a plurality of rows of memory cells and a plurality of columns of memory cells. Each column of memory cells may be connected to one bitline, and each row of memory cells may be connected to one wordline. In this case, one dummy bitline may be provided for every predetermined number of bitlines. In one example, the predetermined number may be 100. The predetermined number may be determined according to specific requirement, and this invention is not limited in this regard.
Based on the aforementioned sense amplifier circuit and operation methods thereof, this invention further provides an input-referred offset voltage compensation method, applicable to an amplifier circuit. The method may include: connecting a first node of the amplifier circuit with a second node of the amplifier circuit through a control circuit coupled to the amplifier circuit to cause voltages on the first node and the second node to converge; separating the first node from the second node through the control circuit; determining a time of compensation; powering on the amplifier circuit for the time of compensation to generate a first signal and a second signal, wherein the first signal is generated at the first node, and the second signal is generated at the second node; and routing the first signal to the second node, and the second signal to the first node through the control circuit to compensate an input-referred offset voltage of the amplifier circuit.
In some embodiments, in the aforementioned method, the input-referred offset voltage of the amplifier circuit may include a difference between threshold voltages of corresponding transistors in the amplifier circuit, and powering on the amplifier circuit for a time of compensation to generate a first signal and a second signal may include: determining the time of compensation; and powering on the amplifier circuit for the time of compensation to generate the first signal and the second signal. A different between the first signal and the second signal reflects the difference between the threshold voltages.
In some embodiments, in the aforementioned method, determining the time of compensation may include: determining the time of compensation based on a transconductance of the amplifier circuit, a bitline resistance, and a bitline parasitic capacitance of the amplifier circuit.
In some embodiments, in the aforementioned method, determining the time of compensation may include: establishing a lookup table for the time of compensation, wherein the lookup table may include a plurality of compensation durations each corresponding to one specific condition; determining a current condition; and determining the time of compensation by finding the compensation duration in the lookup table corresponding to the current condition.
In some embodiments, in the aforementioned method, powering on the amplifier circuit for the time of compensation to generate a first signal and a second signal may include: powering on the amplifier circuit by providing a pull-up voltage and a pull-down voltage to the amplifier circuit. The aforementioned method may further include: conducting a calibration process to determine the pull-up voltage and the pull-down voltage.
In some embodiments, the aforementioned method may further include: receiving an input signal pair for amplification on the first node and the second node, respectively. The input signal pair may be superimposed with the second signal on the first node and the first signal on the second node, respectively.
This invention further provides another input-referred offset voltage compensation method, applicable to an amplification circuit having a first sub-circuit and a second sub-circuit, and having an input-referred offset voltage. The method may include generating a first signal by the first sub-circuit on a first I/O of the amplification circuit, and a second signal by the second sub-circuit on a second I/O of the amplification circuit in response to a voltage signal, wherein a difference between the first signal and the second signal reflects the input-referred offset voltage in the circuit; and connecting the first signal to the second I/O, and the second signal to the first I/O by a compensation circuit coupled to the amplification circuit to compensate the input-referred offset voltage.
In some embodiments, in the aforementioned circuit, the compensation circuit may include: a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit. A first end of the first switch circuit may be connected to a first end of the second switch circuit at the first I/O. A first end of the third switch circuit may be connected to a first end of the fourth switch circuit at the second I/O. A second end of the first switch circuit may be connected to a second end of the fourth switch at an output of the second sub-circuit, and a second end of the second switch circuit may be connected to a second end of the third switch circuit at an output of the first sub-circuit.
In some embodiments, in the aforementioned method, generating a first signal by the first sub-circuit on a first I/O of the amplification circuit, and a second signal by the second sub-circuit on a second I/O of the amplification circuit may include: generating, by operating the first, the second, the third, and the fourth switch circuits, the first signal by the first sub-circuit on the first I/O and the second signal by the second sub-circuit on the second I/O.
In the aforementioned method, through a compensation circuit, the first signal is connected to the second I/O, and the second signal is connected to the first I/O. When the circuit accepting an input signal from the first I/O and the second I/O, the input signal is superimposed with the first signal and the second signal, therefore the input-referred offset voltage of the circuit may be compensated.
The accompanying drawings are merely illustrative of a series of processes included in the method according to some embodiments of this invention and are not intended to be limiting. It will be readily appreciated that the way in which the processes are illustrated does not indicate any chronological order of them or limit them to a particular chronological order. Furthermore, it will also be readily appreciated that the processes may be performed, for example, synchronously or asynchronously in multiple modules.
Other embodiments of this invention will be apparent to those skilled in the art from considering the specification and practicing the embodiments disclosed herein. Accordingly, this disclosure is intended to cover all and any variations, uses, or adaptations of this invention which follow, in general, the principles thereof and include such departures from this invention as come within common knowledge or customary practice within the art to which this invention pertains. It is also intended that the specification and examples be considered as exemplary only, with true scope and spirit of this invention being indicated by the appended claims.
The present disclosure is a US continuation of International Application No. PCT/CN2020/074385, filed on Feb. 6, 2020. The disclosure of International Application No. PCT/CN2020/074385 is hereby incorporated by reference in its entirety.
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| Number | Date | Country | |
|---|---|---|---|
| 20220270653 A1 | Aug 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2020/074385 | Feb 2020 | WO |
| Child | 17741722 | US |
