1. Technical Field
The present invention relates to memory circuits in general, and in particular to static random access memory circuits. Still more particularly, the present invention relates to a sense amplifier circuit for static random access memory circuits.
2. Description of Related Art
In general, memory cells within a static random access memory (SRAM) are connected to a set of bitline pairs BL and *BL. Each of the memory cells is also connected to a wordline WL disposed in the direction perpendicular to the bitline pairs. The data in each of the memory cells appears as an extremely small voltage difference between the corresponding bitline pair connected to the memory cell. Such voltage difference is typically in the range of several tens of a millivolt, and a sense amplifier is commonly utilized to differentially amplify the small voltage difference.
Referring now to the drawings and in particular to
Conventional sense amplifiers, such as latch-type sense amplifier 10, tend to be relatively slow because the bitline pair BL and *BL has a relatively large capacitive load, depending on the array size. Such relative high capacitive load hinders the development of a sufficiently acceptable differential signal between BL and *BL. Consequently, it would be desirable to provide a sense amplifier circuit that can operate in a relatively high speed.
In accordance with a preferred embodiment of the present invention, a sense amplifier includes a pair of inverters cross-coupled to each other. The sense amplifier also includes means for equalizing the charges within the pair of inverters before performing a sense operation, and means for sensing a current difference between a bitline and its complement from a memory cell during the sense operation.
All features and advantages of the present invention will become apparent in the following detailed written description.
The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
With reference now to
Any one of memory cells MC1 and MCn can be selected by setting a corresponding one of wordlines WL1 to WLn to a logic high level, and holding the remaining wordlines to a logic low level. Depending on the binary data stored in the selected memory cell, the power supply voltage Vcc. appears on one of common bitline pair cBL and *cBL and a voltage slightly lower than Vcc appears on the other one of common bitline pair cBL and *cBL. Such voltage difference is differentially amplified by sense amplifier 21.
Referring now to
Basically, a first inverter formed by transistors 31 and 34 is cross-coupled to a second inverter formed by transistors 32 and 36. The gates of transistors 31 and 34 are also coupled to the gates of transistors 32 and 36 via a transmission gate that is formed by transistors 33 and 38.
Sensor amplifier 21 can be activated or inactivated through an enable input 41 and *enable input 42 (i.e., complement of enable input 41) connected to the gates of transistors 33 and 38, respectively. Before performing a sensing operation, sensor amplifier 21 is inactivated by having enable input 41 at a logic low level and *enable input 42 at a logic high level. At such point, transistors 33 and 38 are turned on while transistors 35 and 37 are turned off. As a result, the potentials at the gates of transistors 31-32, 34 and 36 and the potentials at the drains of transistors 34 and 36 are equalized to a predetermined voltage Vcc -Vt, where Vt is the threshold voltage of transistors 34 and 36. Accordingly, the potentials of a common bitline pair cBL 43 and *cBL 44 connected to the drains of transistors 34 and 36, respectively, are also equalized to Vcc-Vt.
During a sensing operation, sensor amplifier 21 is activated by having enable input 41 at a logic high level and *enable input 42 at a logic low level. At such point, transistors 33 and 38 are turned off while transistors 35 and 37 are turned on. As a result, sense amplifier 21 begins to detect the current flow through common bitline pair cBL 43 and *cBL 44 accordingly.
Current is sourced from a selected memory cell within SRAM 20 (from
If the data stored in a selected memory cell is a logic “0,” then some of the current to transistor 37 is sourced from cBL 44, which leads to less current coming from transistors 32 and 36 when compared with corresponding transistors 31 and 34. Thus, the potential at the node between transistors 32 and 36 is higher than the potential at the node between transistors 31 and 34. Consequently, transistor 32 will be turned on more and transistor 36 will be turned off more. As a result, OUT 45 outputs a logic “1.”
As has been described, the present invention provides a sense amplifier circuit for SRAMs. The sense amplifier of the present invention preserves the GND+Vt precharage level of any SRAM, thus eliminating the potential of introducing addition timing related problems. The internal nodes of the sense amplifier of the present invention are biased to Vcc-Vt before performing a sensing operation, thus enabling a rapid recovery in the event of a transient upset. Current is sourced (or sunk) from a memory cell within a SRAM during operation and is otherwise fully complementary when activated. The GND+Vt precharage level is maintained, thus the power consumption of bitline restore is less than many prior art sense amplifiers.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
The present invention was made under government contract DSWA01-96-C-0106.
Number | Name | Date | Kind |
---|---|---|---|
5552728 | Lin | Sep 1996 | A |
5650971 | Longway et al. | Jul 1997 | A |
6091654 | Forbes et al. | Jul 2000 | A |
6754121 | Worley | Jun 2004 | B2 |
Entry |
---|
PCT International Search Report dated Jun. 22, 2006 of International Application No. PCT/US05/23904 filed Jul. 6, 2005. |
Number | Date | Country | |
---|---|---|---|
20060023614 A1 | Feb 2006 | US |