“A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor” Chen et al. Test Symposium, 1999. (ATS '99 Proceedings. Eighth Asian, 16-18.* |
“Delay-Testable Non-Scan Sequential Circuits with Clock Suppression” Tekumalla, et al. ‘Connecting the World’ IEEE International Symposium on Circuits and Systems, 1996. vol. 4, May 12-15 1996 pp. 137-140 vol. 4.* |
“Delay Testing with Clock Control: An Alternative to Enhanced Scan” □□ Tekumalla et al. International Test Conference, 1997. Nov. 1-6 1997 pp. 454-462.* |
IBM Technicall Disclosure Bulletin vol. 25 issue 5 pg 2314-2315 “Chip Partitioning Aid” Oct. 1, 1982.* |
Y. Bertrand et al., “Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits,” International Test Conference, pp. 989-997, 1993. |
M. Abramovici et al., “SMART and FAST: Test Generation for VLSI Scan-Design Circuits,” IEEE Design & Test, pp. 43-54, 1986. |
1. M. Abramovici et al., “FREEZE!: A New Approach for Testing Sequential Circuits,” Proc. 29th Design Automation Conf., pp. 22-25, Jun. 1992. |
Y. Santoso et al., “FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy,” Proc. Design Automation and Test in Europe Conf., 6 pages, Mar. 1999. |
V. D. Agrawal et al., “Design for Testability and Test Generation with Two Clocks,” Proc. 4th Int'l. Symp. on VLSI Design, pp. 112-117, Jan. 1991. |
K.L. Einspahr et al., “Clock Partitioning for Testability,” Proc. 3rd IEEE Great Lakes Symp. on VLSI, pp. 42-46, Mar. 1993. |
K.L. Einspahr et al., “Improving Circuit Testability by Clock Control,” Proc. 6th IEEE Great Lakes Symposium on VLSI, pp. 288-293, Mar. 1996. |
K.L. Einspahr et al., “A Synthesis for Testability Scheme for Finite State Machines Using Clock Control,” IEEE Transactions on CAD, vol. 18, No. 12, pp. 1780-1792, Dec. 1999. |
S.H. Baeg et al., “A New Design for Testability Method: Clock Line Control Design,” Proc. Custom Integrated Circuits Conf., pp. 26.2.1-26.2.4, 1993. |
K.B. Rajan et al., “Increasing Testability by Clock Transformation (Getting Rid of Those Darn States),” Proc. VLSI Test Symp., pp. 1-7, Apr. 1996. |
R. Gupta et al., “The Ballast Methodology for Structured Partial Scan Design,” IEEE Trans. on Computers, vol. 39, No. 4, pp. 538-544, Apr. 1990. |
T.M. Niermann et al., “PROOFS: A Fast , Memory-Efficient Sequential Circuit Fault Simulator,” IEEE Trans. CAD, vol. 11, No. 2, pp. 198-207, Feb. 1992. |
T.P. Kelsey et al., “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. on Computers, vol. 42, No. 11, pp. 1361-1371, Nov. 1993. |
M.A. Iyer et al., “Identifying Sequential Redundancies Without Search,” Proc. 33rd Design Automation Conf., pp. 457-462, Jun. 1996. |
D.E. Long et al., “FILL and FUNI: Algorithms to Identify Illegal States and Sequentially Untestable Faults,” ACM Trans. on Design Automation of Electronic Systems, 27 pages, Jul. 2000. |
I. Hamzaoglu et al., “New Techniques for Deterministic Test Pattern Generation,” Proc. VLSI Test Symp, pp. 446-452, 15 pages, Apr. 1998. |