Servo techniques for approximation of differential capacitance of a sensor

Abstract

Techniques and circuits are described for approximation of the differential capacitance of a capacitive sensor to, among other things, optimize device operation and power consumption. In particular, feedback techniques are utilized for measurement and approximation of the differential capacitance of the capacitive sensor. In accordance with the disclosure, the capacitance approximation value for a test cycle preceding a given test cycle is utilized to reduce the number of iterations to be performed in a continuous series of test cycles. The capacitance approximation value for the given test cycle is reported as being equivalent to that of the preceding test cycle if the variance between the selected capacitance and the unselected capacitance is less than or equal to a first predefined value.

Description

FIELD

The present disclosure pertains to methods for approximation of the differential capacitance of a capacitive sensor.

BACKGROUND

A wide variety of IMDs that employ electronic circuitry for providing various therapies such as electrical stimulation of body tissue, monitoring a physiologic condition, and/or providing a substance are known in the art. For example, cardiac pacemakers and implantable cardioverter-defibrillators (ICDs) have been developed for maintaining a desired heart rate during episodes of bradycardia or for applying cardioversion or defibrillation therapies to the heart upon detection of serious arrhythmias. Other devices deliver drugs to the brain, muscle and organ tissues, and/or nerves for treatment of a variety of conditions.

Over the past 20 years, the IMDs have evolved from relatively bulky, crude, and short-lived devices to complex, long-lived, and miniaturized IMDs that are steadily being miniaturized with their functionality continuously increasing. For example, numerous improvements have been made in cardioversion/defibrillation leads and electrodes that have enabled the cardioversion/defibrillation energy to be precisely delivered about selected upper and lower heart chambers and thereby dramatically reducing the delivered shock energy required to cardiovert or defibrillate the heart chamber. Moreover, the high voltage output circuitry has been improved in many respects to provide monophasic, biphasic, or multi-phase cardioversion/defibrillation shock or pulse waveforms that are efficacious, sometimes with particular combinations of cardioversion/defibrillation electrodes, in lowering the required shock energy to cardiovert or defibrillate the heart.

The miniaturization of IMDs is driving size and cost reduction of all IMD components including the electronic circuitry components, where it is desirable to reduce the size so that the overall circuitry can be more compact. As the dimensions of the IMDs decreases, the electronic circuits of the IMD circuitry are preferred to decrease power consumption in order to maintain or increase longevity. Furthermore, as the dimensions of the components are also shrinking, it is desirable to reduce the number of components within the IMD package.

One response to this desire has been through technological improvements to the existing components. For example, IMDs generally include capacitive sensors that include multiple components. Such sensors include accelerometers, pressure transducers, and similar transducers that may employ a capacitance system to detect, for example, position or motion. In some implementations, the sensors may include a sensing element that includes two parallel plate capacitive components acting in a differential manner in which acceleration of the sensor causes one of the capacitive components to increase in capacitance and the other capacitive component to decrease in capacitance. At rest, or at a constant acceleration, the difference between capacitances in the sensor may remain constant. A detection circuit may determine the values of the capacitances in the sensor by applying a voltage to the capacitive components, e.g., a square wave voltage, and producing an output voltage associated with the capacitive components. The output voltage produced may be digitized using an analog to digital (A/D) converter in order to produce a digital value that indicates the amount and direction of acceleration that is suitable for use in digital systems. Typically, the detection circuit used for determining the digital values of the two capacitances may include amplifiers, filters, oscillators, A/D converters etc.

It is desirable to provide improved techniques and circuits for capacitive sensing that overcome the limitations of the conventional state of the art capacitive sensors.

SUMMARY

In accordance with the present disclosure, an approximation of the differential capacitance of a capacitive sensor is achieved for, among other things, providing an indication of positioning, posture, physical activity, or motion of an object.

In an embodiment, a system for performing an abbreviated capacitance approximation test for determining the differential capacitance of a capacitive sensor in a given cycle comprises a control module communicatively coupled to a capacitance adjustment module and a capacitance approximation bank. The capacitance approximation bank includes a plurality of capacitors (N) that are utilized in the test to approximate the differential capacitance of the capacitive sensor. The capacitors in the capacitance approximation bank may have the same or varying capacitance values. The system may determine whether the approximation of the differential capacitance in a preceding cycle is an appropriate approximation of the differential capacitance in the given cycle. Accordingly, a memory module may further be coupled to the control module and utilized for storage of the value obtained for the approximate capacitance difference in the preceding cycle. In one example, the value stored in memory may include data indicative of the actual adjustment capacitor components that were connected in the preceding cycle.

In an embodiment, the control module may include criteria for modifying a sampling interval or frequency of the capacitance approximation test. The criteria for modification of the sampling interval may be based upon the magnitude of the difference between the capacitive components of the capacitive sensor. In yet another embodiment, the control module may include criteria for controlling the selection of one or more of the capacitors, in the capacitance approximation bank, to be connected to one of the capacitive components of the capacitive sensor.

In another embodiment, a method for performing an approximation test in a given cycle comprises measuring the difference between a first capacitive component and a second capacitive component of a capacitive sensor is measured and comparing the measured value to a threshold value. The method may perform an abbreviated test in response to the measured value being less than the threshold value wherein the abbreviated test utilizes the approximation results of a preceding test cycle in the given cycle.

The foregoing has outlined rather broadly certain features and/or technical advantages in order that the detailed description that follows may be better understood. Additional features and/or advantages will be described hereinafter which form the subject of the claims. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the appended claims. The novel features, both as to organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block diagram of an example capacitance approximation system;

FIG. 2 is a functional block diagram of the example capacitance approximation system that illustrates relative values of C₁ and C₂;

FIG. 3 is a functional block diagram of the example capacitance approximation system that illustrates a detailed view of an example capacitance adjustment module;

FIG. 4 is functional block diagram of an example capacitance comparison module of the capacitance approximation system of FIG. 1;

FIG. 5 illustrates an example method for determining the smaller of C₁ and C₂ of the capacitance approximation system;

FIG. 6 illustrates an example iterative approximation method;

FIG. 7 is a functional block diagram that illustrates a detailed view of an example capacitance adjustment module of the capacitance approximation system of FIG. 1;

FIG. 8 is a functional block diagram that illustrates a detailed view of another example capacitance adjustment module of the capacitance approximation system of FIG. 1;

FIG. 9 is a table that illustrates a numerical example of the iterative approximation method;

FIG. 10 illustrates an example iterative approximation method implemented using an array of capacitors having predetermined values;

FIG. 11 is a functional block diagram of an example capacitance approximation system that includes a zeroing module;

FIG. 12 illustrates a detailed view of an example zeroing module of the capacitance approximation system of FIG. 11;

FIG. 13 is an example iterative zeroing method implemented using an array of capacitors having predetermined values;

FIG. 14 is a functional block diagram of an example capacitance approximation system that includes a compensation module;

FIG. 15 illustrates a detailed view of an example compensation module of the capacitance approximation system of FIG. 14;

FIG. 16 is a functional block diagram of an example capacitance approximation system that includes an offset capacitor;

FIG. 17 is a table that illustrates a numerical example of an iterative approximation method using the example capacitance approximation system of FIG. 16;

FIG. 18 illustrates an example iterative approximation method implemented using the example capacitance approximation system of FIG. 16;

FIG. 19 is a functional block diagram of an example capacitance approximation system that approximates the value of a target capacitance;

FIG. 20 is a table that illustrates a numerical example of an iterative approximation method using the example capacitance approximation system of FIG. 19;

FIG. 21 illustrates an example iterative approximation method implemented using the example capacitance approximation system of FIG. 19;

FIG. 22 is a functional block diagram that illustrates an example implementation of the capacitance approximation system in a medical device system;

FIG. 23 is a functional block diagram that illustrates an example configuration of an implantable medical device that includes the capacitance approximation system;

FIG. 24 illustrates an example capacitance approximation block diagram according to an exemplary embodiment; and

FIG. 25 depicts an iterative approximation method in accordance with the present disclosure.

DETAILED DESCRIPTION

In accordance with the disclosure, a capacitive sensing system is described that may be usable in a variety of applications. For example, the techniques may be usable in an accelerometer device in an implantable medical device (IMD) to detect posture or movement of a patient. Although the present disclosure is particularly described with reference to implantable devices, the disclosure is in no manner limited to such applications. The disclosure may be used in any electronic application whereby employing a capacitive sensor device as described herein is beneficial as would be readily apparent to one skilled in the art. For example, the device as described herein may be used in automobile applications such as in air bag deployment mechanisms. Furthermore, an accelerometer will be discussed as the example capacitive sensor for ease of description, it being understood that the disclosure encompasses implementations of numerous other capacitive sensors and the like. Furthermore, the details of the omitted components and description of the capacitive sensor assembly are known to those of skill in the art and exemplary descriptions can be found in U.S. patent application No.: 2011/0105955 (Yudovsky, et al.), and U.S. patent application No.: 2008/0021336 (Dobak), both of which are incorporated herein by reference in their entirety.

In general, the disclosure is directed to obtaining an indication of relative position, physical activity, or motion of an object such as an organ of a patient or the patient's body. In the exemplary implementation of an accelerometer, the disclosure may be utilized to obtain the indication based on the differential capacitance of capacitive components of the accelerometer. In response to the indication, various actions may be taken by the IMD including modifying the patient's therapy. As such, the present disclosure optimizes operation of the IMD while minimizing the power consumption of the accelerometer.

FIG. 1 is a functional block diagram of a capacitance approximation system 100 that determines an approximate difference in capacitance between capacitance C₁ and capacitance C₂. The capacitances C₁ and C₂, and the difference between C₁ and C₂, may be expressed in units of Farads (e.g., pico-farads).

Capacitance approximation system 100 includes a control module 102, a capacitance comparison module 104, and a capacitance adjustment module 106. The modules of the present disclosure, e.g., control module 102, capacitance comparison module 104, capacitance adjustment module 106, and other modules described herein may be implemented using electronic hardware, firmware, and/or software.

The modules of the present disclosure may include any discrete and/or integrated electronic circuit components that implement analog and/or digital circuits capable of producing the functions attributed to the modules herein. For example, the modules may include analog circuits, e.g., amplification circuits, filtering circuits, and/or other signal conditioning circuits. The modules may also include digital circuits, e.g., combinational or sequential logic circuits, memory devices, etc. Furthermore, the modules may comprise memory that may include computer-readable instructions that, when executed cause the modules to perform various functions attributed to the modules herein. Memory may include any volatile, non-volatile, magnetic, or electrical media, such as a random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), electrically-erasable programmable ROM (EEPROM), flash memory, or any other digital media.

The modules of the present disclosure may also comprise any one or more of an application specific integrated circuit (ASIC), a microprocessor, a microcontroller, a digital signal processor (DSP), a field-programmable gate array (FPGA), or equivalent discrete or integrated logic circuitry. In some examples, modules may include multiple components, such as any combination of one or more microprocessors, one or more microcontrollers, one or more DSPs, one or more ASICs, or one or more FPGAs.

The functions attributed to the modules herein may be embodied as hardware, firmware, software, or any combination thereof. Depiction of different features as modules is intended to highlight different functional aspects and does not necessarily imply that such modules or units must be realized by separate hardware or software components. Rather, functionality associated with one or more modules may be performed by separate hardware or software components, or integrated within common or separate hardware or software components.

Throughout the disclosure, the actual difference between capacitances C₁ and C₂ may be referred to as ΔC. Accordingly, capacitance approximation system 100 determines an approximate value of ΔC. In other words, capacitance approximation system 100 approximates the actual difference between C₁ and C₂. Throughout the disclosure, the approximate value of ΔC determined by capacitance approximation system 100 may be referred to as ΔC_approx.

C₁ and C₂ may represent any two capacitances in general, and accordingly, capacitance approximation system 100 may determine an approximate difference between any two capacitances. In one example, C₁ and C₂ may be included in a capacitance based sensor, such as an accelerometer. When C₁ and C₂ are included in an accelerometer, the difference between capacitances C₁ and C₂ may indicate an amount of acceleration experienced by the accelerometer, e.g., along a single axis in some accelerometers. Accordingly, when C₁ and C₂ are included in an accelerometer, capacitance approximation system 100 may be used to determine an approximate acceleration of the accelerometer. Although C₁ and C₂ may represent capacitances within a capacitance based accelerometer, the capacitances C₁ and C₂ may represent any two capacitances in other capacitance based sensors that indicate parameters other than acceleration.

Capacitance approximation system 100 determines ΔC_approx using an iterative approximation method. The iterative approximation method may include three phases. During the first phase, capacitance approximation system 100 determines which of C₁ and C₂ is smaller. Capacitance approximation system 100 may modify the smaller of C₁ and C₂, as determined during the first phase, during subsequent phases. In other words, the smaller of C₁ and C₂ may be selected by capacitance approximation system 100 for modification during subsequent phases of the iterative approximation method, and accordingly the smaller of C₁ and C₂ as determined during the first phase may be referred to as the “selected capacitance.” The other capacitance (e.g., either C₁ or C₂), which is not selected for modification during the second and third phase may be referred to as the “unselected capacitance.”

During the second phase of the iterative approximation method, capacitance approximation system 100 iteratively adds capacitances having different predetermined values in parallel with the selected capacitance. During each iteration, after a predetermined capacitance is added to the selected capacitance, capacitance approximation system 100 determines whether the selected capacitance in combination with the predetermined capacitance is greater than the unselected capacitance. During each iteration, subsequent to the determination, capacitance approximation system 100 either removes the predetermined capacitance (i.e., disconnects the predetermined capacitance from the selected capacitance) or maintains the connection between the predetermined capacitance and the selected capacitance for subsequent iterations. For example, capacitance approximation system 100 removes the predetermined capacitance if the combination of the selected capacitance and the predetermined capacitance is greater than the unselected capacitance. Alternatively, capacitance approximation system 100 maintains the connection between the predetermined capacitance and the selected capacitance for subsequent iterations if the combination of the selected capacitance and the predetermined capacitance is less than the unselected capacitance.

During subsequent iterations of the second phase, capacitance approximation system 100 adds capacitances having other predetermined values to the selected capacitance and determines whether each of the predetermined capacitances in combination with the selected capacitance is greater or less than the unselected capacitance. Additionally, during the subsequent iterations, capacitance approximation system 100 determines whether to disconnect or maintain the connection of the other predetermined capacitances to the selected capacitance.

During the third phase, after a plurality (e.g., 8) of iterations, capacitance approximation system 100 approximates the difference between the selected and unselected capacitances based on which predetermined capacitances are connected to selected capacitance. For example, capacitance approximation system 100 may determine that ΔC_approx is equal to the amount of capacitance that may be added to the selected capacitance without causing the sum of added capacitance and the selected capacitance to be greater than the unselected capacitance. In other words, capacitance approximation system 100 may determine that ΔC_approx is equal to a maximum amount of predetermined capacitance that may be added to the selected capacitance without causing the selected capacitance to increase to a value that is greater than the unselected capacitance.

Operation of control module 102, capacitance comparison module 104, and capacitance adjustment module 106 are now discussed. Control module 102 may instruct capacitance comparison module 104 and capacitance adjustment module 106, e.g., according to the iterative approximation method, in order to determine ΔC_approx (i.e., approximate ΔC).

At the start of the iterative approximation method, control module 102 instructs capacitance comparison module 104 to determine which of C₁ and C₂ is smaller. This instruction from control module 102 is illustrated as “Detection Instruction” in FIG. 1. Capacitance comparison module 104, in response to the instruction from control module 102, determines which of C₁ and C₂ is smaller. Capacitance comparison module 104 then indicates to control module 102 which of C₁ and C₂ is smaller, illustrated as “Smaller Capacitance” in FIG. 1.

During subsequent steps of the iterative approximation method, control module 102 may modify whichever of C₁ and C₂ is initially determined to be smaller. The smaller of C₁ and C₂, as initially determined, may be subsequently adjusted according to the iterative approximation method, and may be referred to herein as the “selected capacitance.” The larger of C₁ and C₂, as initially determined, may not be adjusted during the iterative approximation method, and may be referred to as the “unselected capacitance.” Although the selected capacitance is described herein as being adjusted according to the iterative approximation method while the unselected capacitance is not adjusted, in other implementations, it is contemplated that either capacitance C₁ or C₂ may be modified during methods similar to the iterative approximation method as described herein. In one example, described with reference to FIGS. 14-15, the unselected capacitance may be modified to compensate for additional capacitance (e.g., parasitics) arising from operation of capacitance adjustment module 106.

After control module 102 receives indication of which of C₁ and C₂ is smaller, control module 102 may instruct capacitance adjustment module 106 to adjust the capacitance between the nodes 108 and 110 (i.e., nodes of C₁) and/or between nodes 112 and 110 (i.e., nodes of C₂). Instructions from control module 102 to capacitance adjustment module 106 may indicate where to add capacitance in the circuit, e.g., between nodes 108 and 110 or between nodes 112 and 110, and how much capacitance to add to the circuit. The instructions that indicate where to add capacitance and how much capacitance to add are illustrated in FIG. 1 as “Selected Capacitance” and “Predetermined Capacitance,” respectively. Details regarding which of C₁ and C₂ is adjusted, and to what extend C₁ and C₂ are adjusted during the iterative approximation method are discussed hereinafter.

In one example, control module 102 may instruct capacitance adjustment module 106 to add capacitance in parallel with C₁, i.e., between nodes 108 and 110. In another example, control module 102 may instruct capacitance adjustment module 106 to add capacitance in parallel with C₂, i.e., between nodes 112 and 110. In still other examples, control module 102 may instruct capacitance adjustment module 106 to add capacitances to both C₁ and C₂.

Capacitance adjustment module 106 may adjust the capacitance between the nodes 108 and 110 of C₁ according to instructions from control module 102. For example, capacitance adjustment module 106 may add a capacitance in parallel with C₁ to increase capacitance between the nodes 108 and 110 of C₁ in response to instructions from control module 102. Hereinafter, adding capacitance between nodes 108 and 110 may be referred to as adjusting C₁ or adding capacitance to C₁, since adding capacitance between nodes 108 and 110 may be electrically equivalent to adjusting/adding capacitance to C₁.

Capacitance adjustment module 106 may adjust the capacitance between the nodes 112 and 110 of capacitance C₂ according to instructions from control module 102. For example, capacitance adjustment module 106 may add a capacitance in parallel with C₂ to increase capacitance between the nodes 112 and 110 of C₂. Hereinafter, adding capacitance between nodes 112 and 110 may be referred to as adjusting C₂ or adding capacitance to C₂, since adding capacitance between nodes 112 and 110 may be electrically equivalent to adjusting/adding capacitance to C₂.

In some implementations, as described herein, capacitance adjustment module 106 may include a capacitor approximation bank that comprises an array of capacitors in which each capacitor of the array has a predetermined capacitance. Accordingly, in some implementations, capacitance adjustment module 106 may add one or more capacitors of the capacitor approximation bank to either C₁ or C₂ to adjust the capacitance of C₁ or C₂, respectively, according to instructions from control module 102.

Referring now to FIG. 2, in order to aid in the explanation of how capacitance approximation system 100 determines ΔC_approx, it will be assumed hereinafter that C₂ is the smaller capacitance of C₁ and C₂. Accordingly, C₁ is illustrated in FIG. 2 as equal to C₂ plus an additional capacitance ΔC (i.e., the actual difference between C₁ and C₂). As illustrated in subsequent figures, capacitance approximation system 100 may be described as approximating ΔC, i.e., determining ΔC_approx, under the assumption that C₁ is equal to C₂ plus ΔC.

As described above, capacitance approximation system 100 initially determines which of C₁ and C₂ is smaller. According to FIG. 2, control module 102 may instruct capacitance comparison module 104 to determine which of C₁ and C₂ is smaller, and in response to the instruction, capacitance comparison module 104 would determine that C₂ is smaller. Accordingly, control module 102 may select capacitance C₂ for adjustment during the iterative approximation method. Since C₂ is illustrated as the smaller capacitance, C₂ may also be referred to hereinafter as the selected capacitance and C₁ may be referred to as the unselected capacitance.

FIG. 3 shows a detailed view of an example capacitance adjustment module 106. Capacitance adjustment module 106 includes a selection module 120 and a capacitance module 122. Selection module 120 selectively connects either C₁ or C₂ to adjustable capacitance “C_adj” of capacitance module 122. Accordingly, selection module 120 is illustrated as a switch may connect either C₁ or C₂ to C_adj.

Selection module 120 may selectively connect either C₁ or C₂ to C_adj based on an instruction (e.g., a binary value) received from control module 102 indicating which capacitance is selected for adjustment. In the example of FIG. 3, selection module 120 selectively connects C₂ to C_adj in response to the instruction from control module 102 indicating that C₂ is the selected capacitance. Although selection module 120 is illustrated and described as connecting C₂ to C_adj since C₂ is the smaller of C₁ and C₂, selection module 120 may also connect C₁ to C_adj in examples where C₁ is smaller than C₂, i.e., in examples where C₁ is the selected capacitance.

C_adj may represent an adjustable capacitance that may be placed in parallel with either C₁ or C₂. In some examples, C_adj may be implemented using a capacitor approximation bank that comprises an array of capacitors having various predetermined values, described hereinafter with reference to FIGS. 7-8. Accordingly, in some examples, capacitance module 122 may selectively add capacitors from the array of capacitors in parallel with the selected capacitance in order to implement the adjustable capacitance C_adj. Although capacitance module 122 is described herein as including a capacitor approximation bank that implements C_adj, it is contemplated that the adjustable capacitance C_adj of capacitance module 122 may be implemented using other techniques.

Capacitance module 122 may set C_adj to the amount of capacitance indicated by control module 102 (e.g., the predetermined capacitance). In examples where C_adj is realized by a capacitor approximation bank, control module 102 may instruct capacitance module 122 using a binary value that indicates which capacitors of the array to connect/disconnect in order to achieve the amount of capacitance (e.g., the predetermined capacitance).

FIG. 4 shows a detailed view of an example capacitance comparison module 104. Capacitance comparison module 104 includes a first charging module 126-A, a second charging module 126-B, and a threshold detection module 128. First and second charging modules 126-A, 126-B charge capacitances C₁ and C₂, respectively. In some examples, C_adj may be connected to either C₁ or C₂, which may result in an adjusted value of either C₁ or C₂, respectively, which may in turn result in an adjusted charging time of C₁ or C₂.

Threshold detection module 128 monitors voltages across C₁ (i.e., V₁) and C₂ (i.e., V₂) while first and second charging modules 126-A, 126-B are charging C₁ and C₂. Threshold detection module 128 determines which of C₁ and C₂ is smaller based on which of the monitored voltages V₁ and V₂ crosses a threshold voltage first. Additionally, threshold detection module 128 may also determine which of C₁ and C₂ is larger based on which of C₁ and C₂ does not cross the threshold voltage first.

First and second charging modules 126-A, 126-B may include current sources (e.g., constant current sources). The current sources of each of first and second charging modules 126-A, 126-B may provide equal charging currents, labeled as “I” in FIG. 4. The equal charging currents may be implemented using current mirror circuits, for example.

Charging modules 126-A, 126-B may each provide the charging currents “I” to respective capacitances C₁ and C₂ starting at the same time in response to the detection instruction from control module 102. Assuming that C₁ and C₂ are discharged prior to receiving the detection instruction from control module 102, and assuming that the first and second charging modules 126-A, 126-B deliver equal currents, starting at approximately the same time in response to the detection instruction, the voltage across the smaller of C₁ and C₂ will increase at a higher rate. Accordingly, the greater of voltages V₁ and V₂ may be the voltage across the smaller of C₁ and C₂. For example, if voltage V₁ increases at a higher rate than voltage V₂, C₁ may be smaller than C₂, and vice versa. Threshold detection module 128 monitors voltages V₁ and V₂ while first and second charging modules 126-A, 126-B deliver current “I” to C₁ and C₂. Threshold detection module 128 monitors V₁ and V₂ to determine which of V₁ and V₂ cross the threshold voltage first. Since the smaller of C₁ and C₂ may develop voltage at a higher rate, the first of V₁ and V₂ to reach the threshold voltage corresponds to the smaller of C₁ and C₂. In other words, threshold detection module 128 detects which of C₁ and C₂ is smaller based on which of V₁ and V₂ increase beyond the threshold voltage first, after receipt of the detection instruction from control module 102.

In some implementations, threshold detection module 128 may include field effect transistor (FET) switches (e.g., metal-oxide-semiconductor FETs (MOSFETs)), the gates of which are connected to V₁ and V₂. In these implementations, threshold voltages of FET switches connected to V₁ and V₂ may serve as the predetermined threshold voltage, and current through the FET switches may serve as the indication of which of C₁ and C₂ is charged to the threshold voltage. In other words, voltages across C₁ and C₂ may be connected to gates of FET transistors and current may flow through the FET transistors, signaling, to control module 102 when the threshold voltage has been reached. In other implementations, threshold detection module 128 may include comparators that compare voltages V₁ and V₂ to the threshold voltage (e.g., a predetermined reference voltage). Accordingly, in some examples, comparators included in threshold detection module 128 may indicate when V₁ and V₂ reach the threshold voltage.

After threshold detection module 128 determines which of C₁ and C₂ is smaller, first and second charging modules 126-A, 126-B may discharge C₁ and C₂, e.g., by connecting a load in parallel with C₁ and C₂. Subsequently, first and second charging modules 126-A, 126-B may wait for the detection instruction from control module 102 before charging C₁ and C₂ again.

Although capacitance comparison module 104 is illustrated as charging C₁ and C₂, in examples where C_adj is connected in parallel with one of C₁ or C₂, capacitance comparison module may charge C_adj along with C₁ and C₂. Connection of C_adj in parallel with a capacitance (e.g., C₁ or C₂) may increase the charging time of the capacitance and in turn decrease a rate at which voltage develops across the capacitance. In this manner, during the iterative approximation method, threshold detection module 128 may determine whether C_adj added in parallel with the selected capacitance is greater than the unselected capacitance.

FIG. 5 illustrates a method for determining which of C₁ and C₂ is smaller. At the start of the method, it is assumed that C₁ and C₂ have been discharged, e.g., so that V₁ and V₂ are approximately 0V. First, charging modules 126-A, 126-B wait for a detection instruction from control module 102 (200). If charging modules 126-A, 126-B receive the detection instruction, charging modules 126-A, 126-B start charging C₁ and C₂ (202). For example, charging modules 126-A, 126-B may connect current sources to C₁ and C₂ that provide constant current to C₁ and C₂ in order to charge C₁ and C₂.

Threshold detection module 128 monitors voltages V₁ and V₂ across C₁ and C₂, respectively, while charging modules 126-A, 126-B are charging C₁ and C₂ (204). Threshold detection module 128 determines whether V₁ or V₂ has reached the threshold voltage (206). When one of V₁ and V₂ reach the threshold voltage, threshold detection module 128 determines which of V₁ and V₂ reached the threshold voltage first (208). Threshold detection module 128 then indicates to control module 102 which of V₁ and V₂ reached the threshold voltage first (i.e., which of C₁ and C₂ is smaller) (210). For example, if V₁ reaches the threshold voltage first, threshold detection module 128 indicates that C₁ is the smaller capacitance of C₁ and C₂. Alternatively, if V₂ reaches the threshold voltage first, threshold detection module 128 indicates that C₂ is the smaller capacitance of C₁ and C₂. Charging modules 126-A, 126-B then discharge C₁ and C₂ so that V₁ and V₂ may return to zero (212). For example, charging modules 126-A, 126-B may connect loads in parallel with C₁ and C₂ to discharge C₁ and C₂.

Referring now to FIG. 6, an example iterative approximation method 300 is shown. Control module 102 may determine ΔC_approx according to the iterative approximation method 300. The iterative approximation method 300 may include three phases. During the first phase, blocks (302) and (304), capacitance approximation system 100 determines which of C₁ and C₂ is smaller. In other words, during the first phase, capacitance approximation system 100 selects one of C₁ and C₂ for modification in subsequent phases.

During the second phase, blocks (306) to (312), capacitance approximation system 100 iteratively adds (e.g., in parallel), to the selected capacitance, capacitances having different predetermined values. During each iteration of blocks (306) to (312), after a predetermined capacitance is added to the selected capacitance, capacitance approximation system 100 determines whether the selected capacitance in combination with the predetermined capacitance is greater than the unselected capacitance. Subsequent to the determination, capacitance approximation system 100 removes the predetermined capacitance if the combination of the selected capacitance and the predetermined capacitance is greater than the unselected capacitance. In subsequent iterations, capacitance approximation system 100 adds capacitances having other predetermined values to the selected capacitance and determines whether each of the predetermined values in combination with the selected capacitance is greater than the unselected capacitance.

During the third phase, block (314), after a plurality of iterations of blocks (306) to (312), control module 102 approximates the difference between the selected and unselected capacitances based on which capacitances are connected to the selected capacitance. In other words, control module 102 determines ΔC_approx based on which predetermined capacitances, when combined with the selected capacitance, did not result in a combination of capacitances that were greater than the unselected capacitance.

The example iterative approximation method 300 is now discussed with reference to FIG. 6 under the assumption that C₂ is less than C₁, according to FIGS. 2-5. Initially, control module 102 instructs capacitance comparison module 104 to determine which of C₁ and C₂ is smaller (302). Capacitance comparison module 104 determines which of C₁ and C₂ is smaller (i.e., C₂) in response to the instruction from control module 102 (304). Capacitance comparison module 104 then indicates, to control module 102, which of C₁ and C₂ is smaller (i.e., indicates C₂). Control module 102 selects the smaller of C₁ and C₂ as the capacitance to adjust during the remaining steps of the iterative approximation method (i.e., blocks (306) to (314)). In other words, C₂ is the selected capacitance for the remainder of the iterative approximation method 300 and C₁ is the unselected capacitance for the remainder of the iterative approximation method 300.

After control module 102 selects a capacitance to modify (i.e., C₂), control module 102 instructs capacitance adjustment module 106 to add a predetermined capacitance to the selected capacitance. In other words, control module 102 instructs capacitance adjustment module 106 to increase the selected capacitance by a predetermined capacitance. In response to the instruction, capacitance adjustment module 106 adds the predetermined capacitance (i.e., C_adj) in parallel with the selected capacitance (i.e., C₂) (306). Accordingly, after block (306), the selected capacitance may be equal to the sum of the selected capacitance prior to block (306) and the predetermined capacitance added in block (306).

Control module 102 then instructs capacitance comparison module 104 to determine whether the selected capacitance (i.e., C₂+C_adj) is larger or smaller than the unselected capacitance. Capacitance comparison module 104 then determines which of the capacitances is smaller. If capacitance comparison module 104 determines that the selected capacitance (i.e., C₂+C_adj) is not less than the unselected capacitance (C₁), control module 102 instructs capacitance adjustment module 106 to disconnect the predetermined capacitance from the selected capacitance (310). If capacitance comparison module 104 determines that the selected capacitance (i.e., C₂+C_adj) is smaller than the unselected capacitance (C₁), control module 102 does not instruct capacitance adjustment module 106 to disconnect the predetermined capacitance from the selected capacitance. Accordingly, the predetermined capacitance may remain connected to the selected capacitance during further iterations in which other capacitances having other predetermined values may be added in parallel with the selected capacitance.

Control module 102 then determines whether to end the iterative approximation method (312). For example, control module 102 may end the iterative approximation method after a predetermined number of iterations have been performed.

If control module 102 decides not to end the iterative approximation method, for example, when the predetermined number of iterations has not been performed, control module 102 initiates another iteration of blocks (306) to (312). In other words, capacitance approximation system 100 performs blocks (306) to (312) of the method 300 again. If the predetermined capacitance was not removed during the prior iteration at block (310), the predetermined capacitance may remain connected during the second iteration.

During the second iteration, control module 102 instructs capacitance adjustment module 106 to add another predetermined capacitance in parallel with the selected capacitance. The predetermined capacitance added in the second iteration may be referred to as a “second predetermined capacitance.” In some implementations, the second predetermined capacitance added in the second iteration may have the same value as the predetermined capacitance added during the first iteration. In other implementations, as explained hereinafter with reference to FIGS. 7-8, the second predetermined capacitance added in the second iteration may have a different value than the predetermined capacitance added during the first iteration.

Capacitance adjustment module 106 adds the second predetermined capacitance in parallel with the selected capacitance in response to the instruction (306). In examples where the predetermined capacitance from the first iteration was not disconnected from the selected capacitance (i.e., C₂) during the first iteration, the selected capacitance at block (308) may be the sum of the selected capacitance from the first iteration, the predetermined capacitance added during the first iteration, and the second predetermined capacitance.

Capacitance comparison module 104, in response to an instruction from control module 102, then determines whether the increase in the selected capacitance causes the selected capacitance to be greater than the unselected capacitance (308). If the selected capacitance in combination with the second predetermined capacitance is greater than the unselected capacitance, capacitance adjustment module 106 disconnects the second predetermined capacitance (310). If the selected capacitance in combination with the second predetermined capacitance is less than the unselected capacitance, capacitance adjustment module 106 does not disconnect the second predetermined capacitance.

Control module 102 then determines whether to end the iterative approximation method (312). If control module 102 does not end the approximation method, the method continues at block (306) for a third iteration of blocks (306) to (312). If control module 102 decides to end the iterative approximation method, for example, if a predetermined number of iterations has been performed, then control module 102 approximates the difference between C₁ and C₂ (i.e., determines ΔC_approx) (314). Control module 102 determines ΔC_approx based on the total of the predetermined capacitances that are still connected to the selected capacitance (i.e., C₂). For example, control module 102 determines that ΔC_approx is equal to the sum of the predetermined capacitances which are connected to the selected capacitance.

In examples in which the predetermined capacitance from the first iteration and the second predetermined capacitance from the second iteration are still connected after the end of the approximation, control module 102 may determine that ΔC_approx is equal to the sum of the predetermined capacitance from the first iteration and the second predetermined capacitance. In examples in which the predetermined capacitance from only the first iteration is connected after the end of the approximation, control module 102 may determine that ΔC_approx is equal to the predetermined capacitance from the first iteration. In examples in which only the second predetermined capacitance from the second iteration is connected, control module 102 may determine that ΔC_approx is equal to the second predetermined capacitance. In examples in which neither the predetermined capacitance from the first iteration nor the second predetermined capacitance are connected, control module 102 determines that ΔC_approx is less than the smaller of the predetermined capacitance from the first iteration and the second predetermined capacitance.

Referring now to FIG. 7, a detailed view of an example capacitance adjustment module 106 is shown to further illustrate an example implementation of capacitance approximation system 100. Capacitance module 122 includes N capacitors. Capacitance module 122 also includes N switches that may selectively connect or disconnect each of the N capacitors to the selected capacitance C₂. Each of the N capacitors includes a label that indicates their respective values. The capacitor on the far right of capacitance module 122 has a capacitance C (e.g., in units of Farads) and may be connected to the selected capacitance via switch S₀. The capacitor to the left of C has a capacitance of 2C (i.e., twice the capacitance of C) and may be connected to the selected capacitance via switch S₁. The capacitor on the far left may be the largest capacitance, having a value of C×2^N-1, and may be connected to the selected capacitance via switch S_N-1.

Control module 102 may instruct capacitance module 122 to open/close any, or all, of switches S₀ to S_N-1. Capacitance module 122, in response to an instruction from control module 102, may open/close any of switches S₀ to S_N-1, and therefore may selectively connect/disconnect any of capacitors C to C×2^N-1 to/from the selected capacitance. For example, capacitance module 122 may open all of switches S₀ to S_N-1 to disconnect all capacitors C to C×2^N-1 from the selected capacitance. As another example, capacitance module 122 may close all switches S₀ to S_N-1 to connect all capacitances to the selected capacitance. During the iterative approximation method, capacitance module 122 may selectively connect any of the capacitors C to C×2^N-1 in response to instructions from control module 102.

Capacitance adjustment module 106 may selectively couple any combination of capacitances C to C×2^N-1 to achieve any combination of discrete capacitor values. Accordingly, capacitance module 122 may selectively produce a predetermined capacitance value that may be connected in parallel to the selected capacitance and which may corresponding to any combination of capacitors C to C×2^N-1. A minimum achievable capacitance value may be C, while a maximum achievable capacitance value may be the sum of all capacitors from C to C×2^N-1.

Capacitance module 122 may selectively couple any combination of capacitors to the selected capacitance in response to an instruction from control module 102, illustrated as “Predetermined Capacitance” in FIG. 7. In the example capacitance module 122 of FIG. 7, since the capacitor array includes N capacitors, control module 102 may instruct capacitance module to connect/disconnect the N capacitors using an N bit binary value. Each of the N bits of the binary value may correspond to one of the N switches of capacitance module 122. Capacitance module 122 may close a switch in response to a bit value of 1. Capacitance module 122 may open a switch in response to a bit value of 0. In some examples, switches S₀ to S_N-1 may be transistor switches, or transmission gates, that selectively connect capacitors C to C×2^N-1 to the selected capacitance based on the binary value received from control module 102. In other words, each of the N bit binary values generated by control module 102 may represent a signal that controls a switch connecting one of the N capacitors to the selected capacitance.

Since the N capacitors illustrated in FIG. 7 are binary-weighted, the N bit value set by control module 102 may be readily translated in a digital implementation, e.g., by control module 102, into an amount of capacitance that is added to the selected capacitance. For example, if control module 102 stores the value C, when control module 102 instructs capacitance module 122 using the value 0001, control module 102 may determine that a value of C will be added in parallel to the selected capacitance in response to the instruction. As a further example, if control module 102 stores the value C, control module 102 may determine that a value of 3C will be added to the selected capacitance in response to the instruction 0011. Accordingly, control module 102 may determine, based on the value C, what amount of capacitance will be added to the selected capacitance in response to any binary instruction that the control module 102 may generate. Furthermore, since the N capacitors are binary-weighted, and represented by a binary value, the value of the capacitance added to the selected capacitance may be directly determined by a digital system and stored as a binary representation in a digital system, without any conversion prior to storage. The direct determination of capacitance by the digital system may eliminate the need for amplifiers and associated A/D converters typically used in capacitance measurement circuits since capacitance approximation system 100 is itself an A/D converter that determines a digital value.

A numerical example of capacitance approximation system 100 implementing the iterative approximation method is now described with reference to FIGS. 8-9. Example capacitance module 122, as shown in FIG. 8, includes four capacitors (i.e., N=4) which are binary weighted (e.g., C, 2C, 4C, and 8C). Control module 102 may set a 4-bit binary value (e.g., 0000-1111) that controls which of the four capacitors are connected to the selected capacitance C₂. For example, a binary value 1000 may indicate that the largest capacitor (i.e., 8C) should be connected to the selected capacitance. As an additional example, a binary value 1111 may indicate that all of the capacitors should be connected to the selected capacitance.

In the example of FIG. 8, C₁=10C and C₂=3.5C. Operation of the capacitance approximation system 100 as illustrated in FIG. 8 is now described using the capacitance values of C₁, C₂, and capacitance module 122.

FIG. 9 is a table that illustrates, for each iteration of the method, binary values set by control module 102, the combined capacitance of the selected capacitance and capacitance from capacitance module 122, comparison results of the capacitances C₁ and C₂ by capacitance comparison module 104, and a decision made by control module 102 in response to the comparison.

During the first phase of the iterative approximation method, control module 102 instructs selection module 120 not to connect any capacitors of capacitance module 122 to either C₁ or C₂. In other words, control module 102 initially instructs selection module 120 not to connect capacitance module 122 to either C₁ or C₂. Control module 102 then instructs capacitance comparison module 104 to determine which of C₁ and C₂ is smaller. Capacitance comparison module 104 then determines which of C₁ and C₂ is smaller. Since C₂ (3.5C) is smaller than C₁ (10C), capacitance comparison module 102 may charge C₂ to the threshold voltage at a faster rate, and accordingly, capacitance comparison module 104 may determine that C₂ is smaller than C₁. Control module 102 may then instruct selection module 120 to connect C₂ to capacitance module 122. Initially, upon connection of C₂ to capacitance module 122 via selection module 120, capacitance module 122 may not have any capacitors connected to C₂ via switches S₀-S₃.

At the start of the second phase of the iterative approximation method, during the first iteration, capacitance module 122 may connect the largest capacitor (i.e., 8C) to C₂ in response to an instruction (e.g., 1000) from control module 102. Control module 102 then instructs capacitance comparison module 104 to determine which is larger, C₁, or the combination of C₂ with 8C. During the first iteration, capacitance comparison module 104 determines that the combination of C₂ and 8C (i.e., 11.5C) is greater than unselected capacitance C₁. Control module 102, based on results of the comparison, instructs capacitance module 122 to disconnect 8C from C₂. Capacitance module 122, in response to the instruction (e.g., 0000) from control module 102, then disconnects 8C from C₂ via switch S₃.

During the second iteration, capacitance module 122 may connect the second largest capacitor (i.e., 4C) to C₂ in response to an instruction (e.g., 0100) from control module 102. Although control module 102 is described above as setting instruction 0000 to disconnect 8C from C₂, then setting instruction 0100 to connect 4C to C₂, control module 102 may perform both tasks by transitioning the instruction in a single step from 1000 to 0100 since the transition would both disconnect 8C and connect 4C. During the second iteration, capacitance comparison module 104 determines that the combination of C₂ and 4C (i.e., 7.5C) is less than unselected capacitance C₁. Control module 102, therefore, does not instruct capacitance module 122 to disconnect capacitor 4C from C₂.

During the third iteration, capacitance module 122 may connect the third largest capacitor (i.e., 2C) to C₂ in response to an instruction (e.g., 0110) from control module 102. During the third iteration, capacitance comparison module 104 determines that the combination of C₂ and 4C and 2C (i.e., 9.5C) is less than unselected capacitance C₁. Control module 102, therefore, does not instruct capacitance module 122 to disconnect capacitor 2C from C₂.

During the fourth iteration, capacitance module 122 may connect the fourth largest capacitor (i.e., C) to C₂ in response to an instruction (e.g., 0111) from control module 102. During the fourth iteration, capacitance comparison module 104 determines that the combination of C₂ and 7C (i.e., 10.5C) is greater than unselected capacitance C₁. Capacitance module 122, in response to instruction from control module 102 (e.g., 0110), may then disconnect the fourth largest capacitor (i.e., C).

In the example of FIG. 8, the predetermined number of iterations stored by control module 102 may be 4, and accordingly, the fourth iteration may be the final iteration of the iterative approximation method. In other words, control module 102 may end the iterative approximation method after 4 iterations. Four iterations for the example of FIG. 8 may be sufficient for the approximation of ΔC since each of the 4 different capacitors included in the capacitance module 122 was connected during the approximation. In other implementations in which capacitance module 122 includes more or less capacitors, the predetermined number of iterations may be more or less. For example, if capacitance module 122 included 7 capacitors, the predetermined number of iterations may be 7, i.e., one iteration for connecting each of the capacitors. As an additional example, if capacitance module 122 included 3 capacitors, the predetermined number of iterations may be 3, i.e., one iteration for connecting each of the capacitors.

In the example of FIGS. 8 and 9, control module 102 may determine ΔC_approx based on which capacitors were connected after the predetermined number (i.e., 4) of iterations. In other words, control module 102 may determine ΔC_approx based on the maximum amount of capacitance that may be connected to the selected capacitance without causing the selected capacitance to be greater than the unselected capacitance. In the example of FIG. 8 and FIG. 9, control module 102 may determine that ΔC is approximately equal to 6C (i.e., ΔC_approx=6C) since the connection of 4C and 2C may be the largest capacitance that may be connected to the selected capacitance without causing the selected capacitance (C₂) to be greater than the unselected capacitance (C₁). In other words, since a final instruction (e.g., 0110) of control module 102 instructed capacitance module 122 to connect 4C and 2C to the selected capacitance, control module 102 may determine that ΔC_approx is equal to 6C.

Referring now to FIG. 10, an example iterative approximation method 400 implemented using a capacitor approximation bank that comprises an array of capacitors having predetermined values is shown. The example illustrated in FIGS. 8-9 is referenced when describing method 400 in order to illustrate one example implementation of the method 400.

Initially, control module 102 instructs capacitance comparison module 104 to determine which of C₁ and C₂ is smaller. Capacitance comparison module 104 charges C₁ and C₂ in response to the instruction (402). Capacitance comparison module 104 then determines which of C₁ and C₂ is smaller (404). The smaller of C₁ and C₂ may be referred to as the “selected capacitance.” In examples where control module 102 actuates selection module 120 using a binary value (e.g., 0 or 1) that represents which of C₁ and C₂ are connected, the binary value may indicate the relative magnitude of C₁ and C₂. Accordingly, the binary value may be used as a sign bit that indicates the sign of ΔC_approx.

Control module 102 instructs capacitance module 122 to connect the largest capacitor of capacitance module 122 in parallel with the selected capacitance. For example, in FIG. 8, control module 102 would instruct capacitance module 122 to connect capacitor 8C in parallel with C₂. Control module 102 then instructs capacitance comparison module 104 to determine whether the selected capacitance in parallel with the largest capacitor is still smaller than the unselected capacitance (408). For example, in FIG. 8, control module 102 would instruct capacitance comparison module 104 to determine whether C₂ in parallel with 8C is less than 10C. If comparison module 104 determines that the selected capacitance in parallel with the largest capacitor is larger than the unselected capacitance, capacitance module 122 disconnects the largest capacitor, in response to an instruction from control module 102 (410). Disconnection of the largest capacitance (i.e., 8C) was illustrated in the example of FIG. 8. If capacitance comparison module 104 determines that the selected capacitance in parallel with the largest capacitor is smaller, capacitance module 122 connects the next largest capacitor in parallel with the selected capacitance (412). In the example of FIG. 8, the largest capacitance (i.e., 8C) was disconnected and the next largest capacitance (i.e., 4C) was connected according to blocks (410) and (412).

Capacitance comparison module 104 then compares the relative magnitude of the selected capacitance with the unselected capacitance after connection of the next largest capacitance (414). In the example of FIG. 8, capacitance comparison module 104 compared capacitance C₁ to capacitance C₂ in parallel with 4C. If capacitance comparison module 104 determines that the selected capacitance is smaller than the unselected capacitance, control module 102 determines whether to end the iterative approximation in block (416). If capacitance comparison module 104 determines that the selected capacitance is not smaller than the unselected capacitance, control module 102 determines whether to end the iterative approximation in block (418). For example, control module 102 may determine whether to end the iterative approximation in blocks (416) or (418) based on whether a predetermined number of iterations have been performed. In the example of FIG. 8, the predetermined number of iterations may be 4, since 4 iterations may be required to connect and compare each of the 4 capacitors.

If control module 102 decides not to end the iterative approximation, the method 400 may continue in either block (412) or block (410), depending on whether the selected capacitance, as modified by the capacitor connected in parallel, was greater than or less than the unselected capacitance in block (414). In the example of FIG. 8, the method 400 would continue in block (412), where capacitor 2C would be connected in parallel with C₂ and 4C.

If control module 102 decides to end the iterative approximation in either block (416) or block (418), control module 102 approximates the difference between C₂ and C₁ (420). Control module 102 may determine ΔC_approx based on the final instruction (e.g., binary instruction) set to control capacitance module 122. In the example of FIG. 8, since a final instruction (e.g., 0110) of control module 102 instructed capacitance module 122 to connect 4C and 2C to the selected capacitance, control module 102 may determine that ΔC_approx is equal to 6C. Stated another way, control module 102 may approximate ΔC based on which capacitors are connected to the selected capacitance after the predetermined number of iterations.

FIGS. 11-12 illustrate another capacitance approximation system 130 which is similar to capacitance approximation system 100 of FIGS. 1 and 2, except that capacitance approximation system 130 of FIG. 11 includes a zeroing module 132, and C₁ and C₂ are illustrated as included in a capacitive sensor 134. Zeroing module 132 may be used in capacitance approximation system 130 to set an initial difference (e.g., due to tolerances) between C₁ and C₂ to approximately zero. For example, zeroing module 132 may include a capacitor approximation bank that includes an array of capacitors, similar to capacitance adjustment module 106 that may be added in parallel with the smaller of C₁ and C₂ to set the difference between C₁ and C₂ to zero. Use of zeroing module 132 to set the difference between C₁ and C₂ to approximately zero may be referred to as a “zeroing operation.”

In one example, when C₁ and C₂ are included in capacitive sensor 134, a zeroing operation may be used, e.g., to eliminate a ΔC value that is present in capacitive sensor 134 in the absence of input. For example, if the capacitive sensor 134 is an accelerometer, ΔC may indicate an amount of acceleration of the accelerometer, and accordingly, the zeroing operation may be used to eliminate a ΔC that may indicate acceleration, when in reality, the accelerometer is not subjected to acceleration. In some examples, ΔC may be on the order of 5 pF.

For purposes of illustration, it will be assumed hereinafter that capacitive sensor 134 is an accelerometer in which ΔC indicates an amount of acceleration experienced by capacitive sensor 134. Although capacitive sensor 134 is described hereinafter as an accelerometer, capacitive sensor 134 may include different types of capacitive sensors that measure parameters other than acceleration. For example, capacitive sensor 134 may include, but is not limited to, a sensor that detects temperature, humidity, pressure, position, or gases (e.g., mercury, hydrogen, carbon dioxide, carbon monoxide, etc.). Accordingly, capacitance approximation system 130 may approximate different sensed parameters depending on the type of parameter indicated by capacitive sensor 134.

Control module 102 may approximate the amount of acceleration experienced by capacitive sensor 134, i.e., may determine ΔC_appox, by implementing the iterative approximation method. However, if there is a difference (e.g., due to manufacturing tolerances) between C₁ and C₂ when the accelerometer is at rest, ΔC_approx determined during the iterative approximation method may not be an accurate representation of actual acceleration of the accelerometer, but instead may indicate both acceleration and initial offset.

Capacitance approximation system 130 may perform a zeroing operation on capacitive sensor 134 in the absence of input (e.g., zero acceleration) to capacitive sensor 134 in order to zero capacitive sensor 134. In the absence of input, any difference between C₁ and C₂ may be an amount of capacitance that does not indicate acceleration. Accordingly, the zeroing operation may be performed in order to eliminate any difference between C₁ and C₂, so that at rest (i.e., zero acceleration), ΔC is approximately 0.

In general, zeroing module 132, under control of control module 102 may add capacitance to the smaller of C₂ and C₁ in a manner similar to the iterative approximation method described above. For example, control module 102 may control zeroing module 132 to add an amount of capacitance to the smaller of C₁ and C₂ without causing the initially smaller capacitance of C₁ and C2 to be greater than the initially larger of C₁ and C₂. The capacitance that may be added by zeroing module 132 without causing the initially smaller of C₁ and C₂ to be greater than the initially larger of C₁ and C₂ may be referred to as a “zeroing capacitance (C_zero).”

Referring now to FIG. 12, a detailed view of an example zeroing module 132 is shown. Zeroing module 132 includes a zeroing selection module 136 and a zeroing capacitance module 138. Control module 102 may control zeroing selection module 136 and zeroing capacitance module 138 in a similar manner to selection module 120 and capacitance module 122 during the iterative approximation method. As illustrated in FIG. 12, selection module 120 may selectively connect either C₁ or C₂ to capacitance module 122 as described above. Independent of the selection made by selection module 120, zeroing selection module 136, under control of control module 102 may selectively connect either C₁ or C₂ to zeroing capacitance module 138 to connect C_zero in parallel with either C₁ or C₂.

Similarly to the iterative approximation method described above, capacitance approximation system 130 may perform an iterative zeroing method in order to reduce a difference between C₁ and C₂ (e.g., due to manufacturing tolerances). The iterative zeroing method may be performed when capacitive sensor 134 is not subjected to input. For example, when capacitive sensor 134 is an accelerometer, the iterative zeroing method may be performed when capacitive sensor 134 is at not subject to acceleration (e.g., at rest, or a constant velocity). Control module 102 may subsequently implement the iterative approximation method while the zeroing capacitance (c_zero) is connected in order to determine an amount of acceleration experienced by capacitive sensor 134. In this manner, implementation of the iterative approximation method subsequent to the iterative zeroing method may result in a determination of ΔC_approx that indicates a sensed parameter and does not indicate an initial offset between C₁ and C₂, due, for example, to a manufacturing tolerance error.

Referring now to FIG. 13, an example iterative zeroing method 500 implemented using a capacitor approximation bank that comprises an array of capacitors having predetermined values is shown. To illustrate the iterative zeroing method 500, it is assumed that zeroing capacitance module 138 includes an array of capacitors having the same values as capacitance module 122 in FIG. 8 (i.e., C, 2C, 4C, and 8C). For purposes of illustration, it may be assumed that C₁ and C₂ include offsets, e.g., due to manufacturing tolerances, such that in the absence of input, C₁=10C and C₂=8.9C.

At the start of the iterative zeroing method, initially, control module 102 instructs capacitance comparison module 104 to determine which of C₁ and C₂ is smaller. Capacitance comparison module 104 charges C₁ and C₂ in response to the instruction (502). Capacitance comparison module 104 then determines which of C₁ and C₂ is smaller (504). The smaller of C₁ and C₂ may be referred to as the “selected zeroing capacitance” since capacitors may be added to it in order to “zero” the difference between C₁ and C₂. The larger of C₁ and C₂ may be referred to as the “unselected zeroing capacitance.”

Control module 102 instructs zeroing module 132 to connect the largest capacitor of zeroing capacitance module 138 in parallel with the selected zeroing capacitance (506). For example, in FIG. 12, control module 102 would instruct zeroing capacitance module 122 to connect capacitor 8C in parallel with C₂. Control module 102 then instructs capacitance comparison module 104 to determine whether the selected zeroing capacitance in parallel with the largest capacitor is still smaller than the unselected zeroing capacitance (508). For example, in FIG. 12, control module 102 would instruct capacitance comparison module 104 to determine whether C₂ in parallel with 8C is less than 10C. If comparison module 104 determines that the selected zeroing capacitance in parallel with the largest capacitor is larger than the unselected zeroing capacitance, zeroing capacitance module 122 disconnects the largest capacitor, in response to an instruction from control module 102 (510). If capacitance comparison module 104 determines that the selected zeroing capacitance in parallel with the largest capacitor is smaller, zeroing capacitance module 122 connects the next largest capacitor in parallel with the selected capacitance (512). In the example of FIG. 12, the largest capacitance (i.e., 8C) would be disconnected and the next largest capacitance (i.e., 4C) would be connected according to blocks (510) and (512).

Capacitance comparison module 104 then compares the relative magnitude of the selected zeroing capacitance with the unselected zeroing capacitance after connection of the next largest capacitance (514). In the example of FIG. 12, capacitance comparison module 104 would compare capacitance C₁ to capacitance C₂ in parallel with 4C. If capacitance comparison module 104 determines that the selected zeroing capacitance is smaller than the unselected zeroing capacitance, control module 102 determines whether to end the iterative zeroing in block (516). If capacitance comparison module 104 determines that the selected zeroing capacitance is not smaller than the unselected zeroing capacitance, control module 102 determines whether to end the iterative zeroing in block (518). For example, control module 102 may determine whether to end the iterative zeroing in blocks (516) or (518) based on whether a predetermined number of iterations have been performed. In the example of FIG. 12, the predetermined number of iterations may be 4, since 4 iterations may be required to connect and compare each of the 4 capacitors of zeroing capacitance module 138.

If control module 102 decides not to end the iterative zeroing, the method may continue in either block (512) or block (510), depending on whether the selected zeroing capacitance, as modified by the capacitor connected in parallel, was greater than or less than the unselected zeroing capacitance in block (514). In the example of FIG. 12, the method 500 would continue in block (510), where capacitor 4C would be disconnected since 4C plus 8.9C is greater than 10C. Capacitor 2C would then be connected in parallel with C₂ in block (512).

After 4 iterations, control module 102 decides to end the iterative zeroing in either block (516) or block (518), when control module 102 has approximately zeroed the difference between C₁ and C₂. In other words, after 4 iterations, control module 102 has connected capacitors in parallel with the smaller of C₁ and C₂ such that the difference between C₁ and C₂ has been minimized. In the example of FIG. 12, a final instruction (e.g., 0001) of control module 102 would instruct zeroing capacitance module 138 to connect C to the selected zeroing capacitance (C₂) to form a capacitance of 9.9C. Accordingly, the difference between C₁ and C₂ with the zeroing capacitance of C connected to C₂ would be 0.1C. Since the iterative zeroing method 500 was performed in the absence of input, a capacitive difference in the absence of input may have been reduced from 1.1C to 0.1C. The iterative approximation method described above may then be performed while the connection of capacitor C is maintained by zeroing module 132 (520).

FIG. 14 illustrates a capacitance approximation system 140 that is similar to capacitance approximation system 100 except that capacitance approximation system 140 includes a compensation module 142. Compensation module 142 may adjust one of C₁ and C₂ in order to compensate, for example, for parasitic capacitances arising from switches of capacitance adjustment module 106. In some implementations, switches (e.g., S₀-S_N-1 of FIG. 7) of capacitance adjustment module 106 may give rise to parasitic capacitances that may add to the capacitors of capacitance adjustment module 106, and therefore add to the selected capacitance. For example, with respect to FIG. 7, switch S₀ may have an associated parasitic capacitance, such that when switch S₀ connects the capacitor having the value C to the selected capacitance, the total capacitance connected to the selected capacitance is modified by the parasitic capacitance associated with switch S₀. In some examples, switches of the present disclosure may include metal-oxide-semiconductor (MOS) transistors. Parasitic capacitances associated with the MOS transistors may include capacitances associated with the gate, bulk, drain, and source of the MOS transistors.

In order to compensate for the parasitic capacitances, e.g., associated with switches of capacitance adjustment module 106, compensation module 142 may add a capacitance to the unselected capacitance (i.e., a compensation capacitance) that is equal to the parasitic capacitance associated with capacitance adjustment module 106. For example, for each parasitic capacitance that may arise from a switch of capacitance adjustment module 106, compensation module 142 may include a similar capacitance that is equal in value. Compensation module 142 may add the similar capacitance to the unselected capacitance to balance the parasitic capacitance associated with capacitance adjustment module 106, so that a similar capacitance is added to both C₁ and C₂.

FIG. 15 illustrates an example compensation module 142. Compensation module 142 includes a compensation selection module 144 and a compensation capacitance module 146. Control module 102 instructs compensation selection module 144 to connect one of C₁ and C₂ to the compensation capacitance (C_comp) included in compensation capacitance module 146. C_comp may be implemented using a capacitor approximation bank that comprises an array of predetermined capacitors, similar to capacitance module 122. Control module 102 may control compensation selection module 144 to connect C_comp to the unselected capacitance so that C_comp may provide compensation for parasitics arising from capacitance adjustment module 106. The instructions from control module 102 that control which of C₁ and C₂ are connected to C_comp, and the value of C_comp are illustrated as “Unselected Capacitance” and “Compensation Capacitance,” respectively.

As described above, capacitance module 122 may include parasitic capacitances for which compensation capacitance C_comp may compensate. In one example, switches of capacitance module 122 that connect the N capacitors to the selected capacitance may give rise to parasitic capacitances when the switches are closed, i.e., connecting a capacitor to the selected capacitance. The parasitic capacitance arising from the closed switches may add to the selected capacitance, and therefore may affect the approximation of the difference between C₁ and C₂. In order to compensate for parasitics that may arise due to the switches of capacitance module 122, control module 102 may instruct compensation capacitance module 146 to connect a capacitance C_comp, that is equal to the parasitics, in parallel with the unselected capacitance. Accordingly, in some examples, each time a capacitor of capacitance module 122 is connected to the selected capacitance, which includes a parasitic capacitance, control module 102 may instruct compensation capacitance module 146 to connect an equivalent parasitic capacitance to the unselected capacitance in order to balance the amount of capacitance added to C₁ and C₂. In this manner, control module 102 may instruct compensation module 142 to compensate for parasitic capacitances that may arise during approximation.

FIG. 16 shows an example capacitance approximation system 150 in which capacitance adjustment module 106 includes an offset capacitor “C_Off.” C_Off is connected to C₁ at the start of the iterative approximation method, and stays connected to C₁ during the iterative approximation method. Capacitance module 122 includes an additional capacitance (i.e., 16C) used to compensate for the addition of C_Off during the iterative approximation method.

Capacitance C_Off is selected such that C_Off has a value that is greater than a difference that may be present between C₁ and C₂. Accordingly, regardless of the values of C₁ and C₂, the capacitance (either C₁ or C₂) to which C_Off is connected will be greater than the capacitance (the other of C₁ or C₂) to which C_Off is not connected. Since the connection of C_Off to C₁ assures that C₂ will be the smaller capacitance when C_Off is connected, capacitance approximation system 150 may eliminate the initial steps of the iterative approximation method in which the selected capacitance is determined. Instead, the iterative approximation method may begin by adding the largest capacitor (e.g., 16C) in parallel with C₂. Although C_Off is illustrated as connected in parallel with C₁, in other examples, C_Off may be connected in parallel with capacitance C₂ and the capacitance approximation system may selectively connect and disconnect capacitors from capacitance C₁.

The value of C_Off is chosen such that adding it to either capacitance C₁ or C₂ will cause the combination of C_Off and the capacitance to which it is added to be greater than the capacitance to which C_Off is not added. For example, in the case where C₁ and C₂ are included in a capacitive accelerometer, the value of C_Off may be chosen based on a maximum difference between capacitances C₁ and C₂ according to the specifications of the accelerometer.

Referring now to FIG. 18, an example iterative approximation method 700 implemented using an offset capacitor (C_Off) having a predetermined value is shown. Capacitance approximation system 150 of FIG. 16 and the table of FIG. 17 are referenced when describing method 700 in order to illustrate one example implementation of the method 700. The capacitance that is not connected to the offset capacitor C_Off (i.e., C₂) during the method 700 may be referred to as the “selected capacitance.”

Initially, control module 102 instructs capacitance module 122 to connect the largest capacitor of capacitance module 122 in parallel with the selected capacitance (702). For example, in FIG. 16, control module 102 would instruct capacitance module 122 to connect capacitor 16C in parallel with C₂. Control module 102 then instructs capacitance comparison module 104 to determine whether the selected capacitance in parallel with the largest capacitor is smaller than the unselected capacitance (704). For example, in FIG. 16, control module 102 would instruct capacitance comparison module 104 to determine whether C₂ in parallel with 16C is less than 26C. If comparison module 104 determines that the selected capacitance in parallel with the largest capacitor is larger than the unselected capacitance, capacitance module 122 disconnects the largest capacitor, in response to an instruction from control module 102 (706). If capacitance comparison module 104 determines that the selected capacitance in parallel with the largest capacitor is smaller, capacitance module 122 connects the next largest capacitor in parallel with the selected capacitance (708). In the example of FIG. 16, the largest capacitance (i.e., 16C) would remain connected to C₂ while the next largest capacitance (i.e., 8C) was connected to C₂ to form a capacitance of 27.5C.

Capacitance comparison module 104 then compares the relative magnitude of the selected capacitance with the unselected capacitance after connection of the next largest capacitance (710). In the example of FIG. 16, capacitance comparison module 104 compared capacitance C₁ to capacitance C₂ in parallel with 24C. If capacitance comparison module 104 determines that the selected capacitance is smaller than the unselected capacitance, control module 102 determines whether to end the iterative approximation in block (712). If capacitance comparison module 104 determines that the selected capacitance is not smaller than the unselected capacitance, control module 102 determines whether to end the iterative approximation in block (714). For example, control module 102 may determine whether to end the iterative approximation in blocks (712) or (714) based on whether a predetermined number of iterations have been performed. In the example of FIG. 16, the predetermined number of iterations may be equal to the number of iterations required to connect and compare each of the capacitors of capacitance module 122.

If control module 102 decides not to end the iterative approximation, the method 700 may continue in either block (706) or block (708), depending on whether the selected capacitance, as modified by the capacitor connected in parallel, was greater than or less than the unselected capacitance in block (710). In the example of FIG. 16, the method 700 would continue in block (706), where capacitor 4C would be connected in parallel with C₂ and 16C.

If control module 102 decides to end the iterative approximation in either block (712) or block (714), control module 102 approximates the difference between C₂ and C₁ (716). Control module 102 may determine ΔC_approx based on the final instruction (e.g., binary instruction) set to control capacitance module 122. In the example of FIG. 16, since a final instruction (e.g., 10110) of control module 102 instructed capacitance module 122 to connect 4C and 2C to the selected capacitance, control module 102 may determine that ΔC_approx is equal to 6C. Stated another way, control module 102 may approximate ΔC based on which capacitors are connected to the selected capacitance after the predetermined number of iterations. The most significant bit (i.e., the bit corresponding to 16C) may serve as a sign bit that indicates which of C₁ and C₂ is larger. When the most significant bit is set to 1, as in FIG. 16, it indicates that the capacitance connected to C_Off is larger than the capacitance not connected to C_Off.

Referring now to FIG. 19, an example capacitance approximation system 160 may approximate the capacitance of a single capacitance (C₁), referred to hereinafter as a “target capacitance.” FIG. 21 shows an example iterative approximation method 800 that approximates a capacitance of a single capacitance. Capacitance approximation system 160 of FIG. 19 and the table of FIG. 20 are referenced when describing method 800 in order to illustrate one example implementation of the method 800.

Initially, control module 102 instructs capacitance module 122 to connect the largest capacitor of capacitance module 122 in parallel with capacitance comparison module 104 (802). For example, in FIG. 19, control module 102 would instruct capacitance module 122 to connect capacitor 8C in parallel with capacitance comparison module 104. Control module 102 then instructs capacitance comparison module 104 to determine whether the connected capacitance (e.g., 8C) is smaller than the target capacitance C₁. For example, in FIG. 19, control module 102 would instruct capacitance comparison module 104 to determine whether 8C is less than 10.5C. If comparison module 104 determines that the connected capacitor is larger than the target capacitance, capacitance module 122 disconnects the connected capacitor, in response to an instruction from control module 102 (806). If capacitance comparison module 104 determines that the connected capacitance is smaller than the target capacitance, capacitance module 122 connects the next largest capacitor (e.g., 4C) in parallel with the capacitance comparison module 104 (808). In the example of FIG. 19, the largest capacitance (i.e., 8C) was not disconnected and the next largest capacitance (i.e., 4C) was connected according to blocks (806) and (808).

Capacitance comparison module 104 then compares the relative magnitude of the connected capacitors and the target capacitance (810). If capacitance comparison module 104 determines that the connected capacitor is smaller than the target capacitance, control module 102 determines whether to end the iterative approximation in block (812). If capacitance comparison module 104 determines that the connected capacitor is not smaller than the target capacitance, control module 102 determines whether to end the iterative approximation in block (814). For example, control module 102 may determine whether to end the iterative approximation in blocks (812) or (814) based on whether a predetermined number of iterations have been performed.

If control module 102 decides to end the iterative approximation in either block (812) or block (814), control module 102 approximates the target capacitance (816). Control module 102 may approximate the target capacitance based on the final instruction (e.g., binary instruction) set to control capacitance module 122. In the example of FIG. 19, since a final instruction (e.g., 1010) of control module 102 instructed capacitance module 122 to connect 8C and 2C to capacitance comparison module 104, control module 102 may determine that the target capacitance is approximately equal to 10C.

Although not illustrated in FIG. 19, in some examples, capacitance adjustment module 106 may include a capacitor having a predetermined value added in parallel with the nodes of capacitance module 122 in order to adjust a range of capacitance that may be determined by capacitance approximation system 160. In practice, C₁ may have a value that is larger than the sum of the capacitors included in capacitance module 122. When this is the case, a predetermined capacitor having a value slightly less than C₁ and added in parallel with capacitance module 122 may allow the capacitance approximation system 160 to determine the value of capacitance C₁. For example, when the predetermined capacitor is added in parallel with capacitance module 122, the resulting capacitance determined by the iterative approximation method may be added to the predetermined capacitance to determine the value of the target capacitance C₁.

FIG. 22 is a conceptual diagram of an example medical device system 610 that may be used to provide therapy to heart 612 of patient 614. System 610 includes an IMD 616, which is coupled to leads 618, 620, and 622. For example, IMD 616 may be an implantable pacemaker, cardioverter, and/or defibrillator that provides electrical signals to heart 612 using one or more of leads 618, 620, 622. Leads 618, 620, 622 extend into heart 612 of patient 614. Leads 618, 620, 622 sense electrical activity of heart 612 and/or deliver electrical stimulation to heart 612. In some examples, IMD 616 may implement capacitance approximation system 100, 130, 140 of the present disclosure as described hereinafter.

System 610 includes a programmer 624 that communicates wirelessly with IMD 616. Programmer 624 may be a handheld computing device, a desktop computing device, a networked computing device, etc. Programmer 624 may retrieve data stored in IMD 616 and/or program IMD 616 to provide various therapies. Accordingly, a user may retrieve data from IMD 616 and program IMD 616 using programmer 624. IMD 616 and programmer 624 may communicate via wireless communication using any techniques known in the art.

FIG. 23 is a functional block diagram that illustrates an example configuration of IMD 616. IMD 616 includes a processor 680, memory 682, a signal generator 684, an electrical sensing module 686, a telemetry module 688, a power source 698, and capacitive sensor 134. Memory 682 may include computer-readable instructions that, when executed by processor 680, cause IMD 616 and processor 680 to perform various functions attributed to IMD 616 and processor 680 herein. Memory 682 may include any volatile, non-volatile, magnetic, or electrical media, such as a random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), electrically-erasable programmable ROM (EEPROM), flash memory, or any other digital media.

Processor 680 may include any one or more of a microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or equivalent discrete or integrated logic circuitry. In some examples, processor 680 may include multiple components, such as any combination of one or more microprocessors, one or more microcontrollers, one or more DSPs, one or more ASICs, or one or more FPGAs, as well as other discrete or integrated logic circuitry. The functions attributed to processor 680 herein may be embodied as software, firmware, hardware or any combination thereof. Processor 680 may include capacitance approximation system 100, 130, 140 of the present disclosure. For example, processor 680 may include control module 102, capacitance comparison module 104, and capacitance adjustment module 106.

Signal generator 684 is electrically coupled to electrodes on leads 618, 620, 622. Signal generator 684 is configured to generate and deliver electrical stimulation therapy to heart 612 via the electrodes on leads 618, 620, 622. For example, signal generator 684 may deliver pacing pulses and/or defibrillation shocks to heart 612. Processor 680 controls signal generator 684 to deliver stimulation therapy to heart 612.

Electrical sensing module 686 monitors signals from electrodes of leads 618, 620, 622. Processor 680 monitors electrical activity of heart 612 based on data received from electrical sensing module 686. Processor 680 may store cardiac EGMs, marker channel data, and so on, for physiological episodes, such as tachyarrhythmias, within memory 682.

Telemetry module 688 includes any suitable hardware, firmware, software or any combination thereof for communicating with another device, such as programmer 624. Under control of processor 680, telemetry module 688 may receive downlink telemetry from and send uplink telemetry to programmer 624 with the aid of an antenna (not shown), which may be internal and/or external. The various components of IMD 616 are coupled to a power source 698, which may include a rechargeable or non-rechargeable battery.

Although illustrated as a component of IMD 616, capacitive sensor 134 may be positioned in various locations in system 610. For example, capacitive sensor 134 may be located within IMD 616, outside of IMD 616, or on or within one or more of leads 618, 620, 622. In some implementations, capacitive sensor 134 may be external (i.e., not implanted).

Capacitive sensor 134 may comprise a capacitive accelerometer as described above. Accordingly, capacitive sensor 134 may detect various physical parameters associated with patient 614. The various parameters may include physical activity associated with patient 614, e.g., contraction of the heart 612, activity of patient 614, posture of patient 614, and respiration of patient 614. Processor 680 may include capacitive approximation system 100 and may implement the iterative approximation method to approximate the various parameters indicated by capacitive sensor 134. Processor 680 may then store the approximated parameters in memory 682 and/or transmit the approximated parameters to programmer 624 via telemetry module 688, for example.

FIG. 24 illustrates an example capacitance approximation block diagram according to an exemplary embodiment. The various components of the capacitance approximation block diagram may be implemented as a single device system or as a multi-component system. In essence, the techniques of the exemplary embodiment of FIG. 24 are feedback based, akin to a servo system, such that the approximation is performed by continuously updating a conversion value indicated by the ΔC_approx based on stored C_adj value(s).

The capacitance approximation block diagram 20 includes a control module 102, a capacitance comparison module 104, a capacitance adjustment module 106, a selection module 120, and a memory module 22. The elements of capacitance approximation system 20 corresponding to those of capacitance approximation systems 100-160 are numbered with identical reference designators. The reader is referred to the preceding discussion for a full description pertaining to those components. Briefly, control module 102 manages the iterative approximation method by performing various processing operations in conjunction with, and with data supplied by, capacitance comparison module 104 and capacitance adjustment module 106 in order to determine ΔC_approx (i.e., approximate ΔC). The capacitance comparison module 104 determines which of the two capacitive components C₁ and C₂ is smaller. The control module 102 subsequently cooperates with the capacitance adjustment module 106 to determine the amount of capacitance that approximates the difference (or variance) between the capacitance of the capacitive components C₁ and C₂.

Memory 22 is a component that stores data for subsequent retrieval. For example, the ΔC_approx of a preceding iteration of capacitance approximation may be stored in memory 22 for retrieval by the capacitance adjustment module 106 in a subsequent assessment of the capacitance approximation. Control module 102 is coupled to memory 22 in such a manner that control module 102 can control writing of data directly to memory 22, erasing of data from memory 22, and retrieval of one or more segments of memory 22. While memory 22 is illustrated as a standalone component, those skilled in the art will appreciate that memory 22 may correspond to a segment of already existing memory of the IMD that permits the segment to be usable or addressable by the control module 102. As such, memory 22 may reside in any suitable location of the IMD.

In accordance with the present disclosure, the data stored in memory 22 may include an indication of the capacitance value or ΔC_approx that corresponds to one or more of recently used C_adj value(s). For instance, the indication stored in memory 22 may be the binary value indicating which capacitors of the array of capacitors were connected in a prior test cycle that precedes a given test cycle. Another example may be the storage in memory 22 of the switches of capacitance module 122 that are closed. As used in this application, the test cycle may correspond to the operations performed for a single sampling request—where the operations performed in the single sampling request result in an approximation of the difference between the selected and unselected capacitances. For example, a single sampling request may correspond to one iteration of the approximation method. In another example, the single sampling request may include multiple iterations that yield ΔC_approx. Furthermore, the reader is reminded that selected capacitance refers to the smaller of the capacitance components C₁ and C₂, including the components of the capacitance approximation bank that may be coupled to that smaller capacitance component whereas, the unselected capacitance refers to the larger of the capacitance components C₁ and C₂.

The inventors of the present disclosure have discovered that the incremental change in the differential capacitance value for a capacitive sensor is minimal in most instances. This is especially evident in situations where several sampling requests are made over a short period of time. Therefore, to reduce the processing time for approximating the difference/variation between the selected and unselected capacitances, the stored indication of the C_adj values that were used in a prior test cycle to determine ΔC_approx may be used in a given test cycle as the initial starting point. This abbreviated approximation test will among other things also reduce the power consumed by the capacitive sensing components of the IMD. In an exemplary embodiment, the approximation may be initiated with the C_adj values that provided the ΔC_approx in the immediately preceding test cycle. In another embodiment, the approximation may be initiated with the C_adj values that provided the ΔC_approx in a test cycle corresponding to a predetermined number of test cycles prior to the given test cycle. For example, the predetermined number of test cycles may correspond to any desired test cycle that occurred prior to a given (e.g., current) test cycle such, for instance, as the second or third or tenth test cycle preceding the given test cycle. By initiating the test in a given cycle with the C_adj values for a prior test cycle, the number of iterations to be performed in the given test cycle may be reduced. This is in comparison to initiating the approximation for each sampling request “with a clean slate,” i.e., initiating each given test from either end of the spectrum (smallest or largest) of the C_adj values. Accordingly, the present disclosure speeds up the approximation of the difference or variance between the selected and unselected capacitances in a given test cycle. Additionally, reducing the number of iterations to be performed in a given test cycle facilitates power conservation of the limited power source of the IMD.

Moreover, it may be the case that ΔC_approx will not change significantly (as defined relative to the specific implementation) from a prior sampling request to a given sampling request and therefore the ΔC_approx value obtained for a preceding test cycle will be an appropriate approximation for the given sampling request. This is especially applicable for embodiments where the approximation is performed continuously or within short intervals. By first determining whether the previous ΔC_approx value holds true for the given sampling request, additional computations may be eliminated. In accordance with an embodiment of the present disclosure, control module 102 retrieves from memory 22 an indication of the C_adj values that were used in a prior test cycle to determine ΔC_approx for that prior test cycle in response to a sampling request. Control module 102 may first evaluate whether the C_adj values that were used in a prior test cycle to determine ΔC_approx also provide an accurate approximation for the given cycle, and if so, the binary representation of the C_adj values for the prior test is reported as the result of the given test.

Memory 22 may be a volatile or non-volatile memory structure that includes memory sufficient for operation of the capacitance approximation system 20. In an embodiment, the memory 22 will include an appropriate storage capacity for storing an indication of the ΔC_approx for each of a predetermined number of test cycles preceding a given test cycle. For example, the predetermined number of test cycles may correspond to the immediately preceding test cycle, or any other desired preceding test cycle. As one non-limiting example, the third preceding test cycle may be chosen. Alternatively, a plurality of preceding test cycles may be stored, such as ten preceding test cycles. Examples of memory 22 may include conventional volatile Random Access Memory (RAM) such as Static RAM, or conventional Read-Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM) such as flash EEPROM, and register arrays configured on ASICs. Such memory 22 may have read/write capability, which is to say that data can be erased from or written to one or more of the memory's locations.

Turning now to FIG. 25 an iterative approximation method in accordance with the present disclosure is discussed. The iterative approximation method of FIG. 25 initially includes an abbreviated capacitance approximation, and is discussed with reference to FIG. 24 to illustrate one example implementation of the block diagram 20. In accordance with the present disclosure, the abbreviated approximation will first determine whether a ΔC_approx of a preceding test cycle approximates the difference between C₁ and C₂ in the current test cycle, the current test cycle being the given test cycle in this instance.

At the outset, the smaller of C₁ and C₂ or the larger of C₁ and C₂ is identified (32). In the method, it is assumed that C₂ is less than C₁ it being understood that the assumption is made here for ease of description and that in an actual implementation, the determination of the smaller capacitance would actually be performed. That determination (of the comparative difference between capacitive components C₂ and C₁) may be performed in accordance with the description in FIGS. 2-5.

The identification process may be handled by the control module 102 in conjunction with capacitance comparison module 104. Capacitance comparison module 104 may charge C₁ and C₂ in response to the instruction to identify the smaller or larger of C₁ and C₂. In embodiments where identification of the smaller capacitive component is desired, the smaller of C₁ and C₂ may be referred to as the “selected capacitance.” In examples where control module 102 actuates selection module 120 using a binary value (e.g., 0 or 1) that represents which of C₁ and C₂ are connected, the binary value may indicate the relative magnitude of C₁ and C₂.

Subsequently, the capacitance values corresponding to the C_adj values that resulted in the ΔC_approx of a preceding test cycle (or the switches that were closed) are connected in parallel to the selected capacitance (34). In accordance with the abbreviated approximation of FIG. 25, doing so provides a determination in the first instance of the difference between C₁ and C₂ for the current test cycle that is subsequent to the preceding test cycle. As used in this disclosure, the preceding cycle (tasks of the method of FIG. 25) from which the ΔC_approx is chosen may, in one embodiment, refer to the test sequence performed immediately preceding a given test cycle. In other embodiments, the preceding cycle may be selected from previous cycles randomly or it may be a predetermined/preselected cycle, such as the fifth preceding test cycle.

A difference between the unselected capacitance and the combination of the selected capacitance coupled to the ΔC_approx of the preceding cycle is measured (36). The unselected capacitance is the other of the two capacitances C₁ and C₂ that is not the selected capacitance. In various embodiments, a capacitance amount is predetermined as indicative of an acceptable threshold value for which the ΔC_approx of a preceding test cycle is deemed to be an appropriate approximation of the difference between C₁ and C₂ in the current cycle. The predetermined capacitance amount may be application specific thus being set based on the desired implementation. For example, in one exemplary implementation of an IMD accelerometer, the predetermined capacitance amount is in the range of approximately 0.5 femtofarad (fF) to approximately 1 picofarad (pF). In another example, the predetermined capacitance amount may be approximately 1 fF. In yet another example implementation, the predetermined capacitance amount may be approximately 0.5 pF. Moreover, multiple threshold values may be provided ranging from a minimum value to a maximum value, with any desired number of intermediate values therebetween, for execution of the approximation determination.

Subsequent to measuring the difference, a determination is made as to whether the difference between the unselected capacitance and the selected capacitance (coupled to the ΔC_approx of the preceding cycle) is within a predetermined capacitance amount (38). In one embodiment, the determination involves obtaining the absolute value of the difference between the selected and unselected capacitance. That absolute value is then compared to the predetermined capacitance amount. If the difference between the selected and unselected capacitance is less than or equal to the predetermined capacitance amount, the ΔC_approx that resulted from the connected C_adj components in the preceding test cycle is deemed to be an appropriate approximation of the difference between C₁ and C₂. In other words, responsive to determining that the difference between the selected capacitance and the unselected capacitance is less than or equal to ΔC_approx (plus or minus the predetermined capacitance amount), the ΔC_approx for the current test cycle remains equivalent to the connected C_adj values for the preceding test cycle. The result of the comparison may be reported to the controller (40). Additionally, the memory contents of the ΔC_approx of the previous cycle remain unchanged and any request for a capacitance approximation will be reported as the value of the memory contents.

However, if the difference between the selected capacitance and the unselected capacitance is greater than a predetermined capacitance amount (+/− the predetermined capacitance amount), the ΔC_approx of the preceding test cycle is deemed to be an unsuitable approximation of the difference between C₁ and C₂.

One of the benefits of the capacitance servo system of the present disclosure is that the capacitance approximation may be performed in a continual, on-going, basis. The continuous operation speeds up the turnaround time, i.e., the duration between a sampling requests and reporting of the difference in capacitance. This is attributed to the fact that an updated value is generally always available (stored in memory) or is quickly obtainable (owing to the fact that the present disclosure generally prevents large deviations in the C₁ and C₂ capacitance difference). In addition, the magnitude of the deviation between the threshold value and the measured difference may be utilized in a self-learning capacity. In other words, the magnitude of the deviation may inform adjustments that need to be performed in the capacitance approximation system. The self-learning may involve adjusting the interval between measurements or by modifying the magnitude of successive increments or decrements of the C_adj components.

Accordingly, if the difference between the selected capacitance and the unselected capacitance is greater than a predetermined capacitance amount, a determination is made as to whether a system overload has occurred (42). In some embodiments, a system overload may be evaluated as a function of the magnitude of the total capacitance of the capacitors of the C_adj components relative to the difference between the selected capacitance and the unselected capacitance. For example, a determination is made as to whether the measured difference between C₁ and C₂ (with the ΔC_approx of the preceding test cycle coupled to the selected capacitance) is greater or less than a threshold value such as a given percentage the total capacitance value of all the C_adj components. The given percentage may be a value ranging anywhere from 10% to 90% of the total capacitance value of all the C_adj components. The given percentage may also be based on the value of the single largest C_adj component, such as 50% of that component. The given percentage may simply be 100% of the smallest coupled C_adj component.

In any event, the threshold value indicates the greatest tolerable deviation in the magnitude of the difference between C₁ and C₂. If the difference between C₁ and C₂ is less than the threshold value, a change in the sampling interval or frequency may be performed (44). In other words, the interval between the present test cycle and a subsequent test cycle may be modulated as a function of the magnitude of the relative change in the differential capacitance.

A large magnitude of change in the capacitance difference from one cycle to the next cycle may indicate that the sampling is not being performed frequently enough or that the system is approaching the overloaded condition which may cause a cessation in tracking the sensor signal. These instances may affect the operation of a device to which the sensor is coupled. As a result, reducing the interval between sampling cycles so that more samples are obtained per unit time may be desired, depending on the application. The converse situation, where the magnitude of change is too small on a plurality of successive cycles, may also trigger a change in the sampling interval. That is, the interval may be increased so that fewer samples are obtained if the magnitude of the relative change in the differential capacitance is too small. Such a change would further contribute to conservation of the limited power resources of the IMD. As is further illustrated, the task of changing the sampling interval may also be performed if the difference is within a predetermined capacitance amount (48). For example, the interval may be extended to conserve the limited battery resources of the IMD power source 698.

In accordance with embodiments of this disclosure, one or more threshold values may be preselected as an indicator of the largest and smallest difference in the magnitude of differential capacitance change from one cycle to the next cycle, with the sampling interval being adjusted based on the threshold being exceeded. As an example, if the magnitude of the difference between the selected capacitance coupled to ΔC_approx and the unselected capacitance exceeds a first threshold value, e.g., 10 nF, the rate at which the sampling is performed may be increased by 50%. Of course the threshold values and the change in the sampling interval may be customized based on the actual implementation. For example, different threshold values may be provided for finer adjustments of the sampling interval with the values ranging from a maximum to a minimum and other intermediate values. The threshold value(s) and the different sampling intervals may be stored in a look-up table that is accessed by a controller that regulates operation of the approximation.

Additionally, if the magnitude of the difference is greater than the predetermined capacitance amount, one or more of the C_adj components may be connected to or disconnected from the selected capacitance (46). The selection of the one or more C_adj components to be connected to or disconnected from the selected capacitance may be based on the determination of whether the difference between the selected and the unselected capacitance is within a predetermined capacitance amount. Accordingly, in one implementation, the C_adj components may be grouped based upon their relative magnitude with the specific one or more C_adj component(s) to be connected being selected based upon the measured magnitude of the difference between the selected and the unselected capacitance. For example, a lower limit value and an upper limit value may be defined in a sliding scale manner for a plurality of ranges from zero up to several microfarads, with the C_adj components beings grouped based on the defined plurality of ranges. In that example, the approximation is initiated with the iterative addition of a suitable C_adj component(s) based upon the value of the magnitude of the difference in relation to the defined plurality of ranges. As such, C_adj component(s) with smaller values would be selected for addition if the magnitude of the difference falls on the lower end of the plurality of ranges in comparison to the values of the C_adj component(s) that would be selected if the magnitude of the difference is on the higher end of the plurality of ranges (that indicates a larger magnitude and hence warranting larger C_adj components). In another implementation, the C_adj components may be grouped as a function of the percentage of the difference between the selected capacitance and the unselected capacitance. A benefit of utilizing the embodiments that permit selection of C_adj components to be connected or disconnected based upon the relative magnitude of the difference between the selected capacitance and unselected capacitance is that the number of iterations required to obtain the approximation of the difference is also reduced.

In an embodiment, tasks 44 and 46 may be performed in concert so that as the frequency is adjusted, the values of the components being coupled may also be adjusted. For example, if each iteration results in a minimal magnitude of the difference, the frequency may be increased and larger C_adj component(s) may be utilized.

Responsive to the coupling or decoupling of each additional (one or more) C_adj components in an iteration for the current test cycle, the total ΔC_approx is reported to the controller and the memory is updated with the value of the currently coupled C_adj components (40). In the abbreviated approximation, the C_adj component(s) are iteratively added to the C_adj values that provided the ΔC_approx of the chosen preceding test cycle with each successive iteration resulting in connection of additional C_adj component(s) until the difference between the selected capacitance and the unselected capacitance is less than a desired threshold.

The abbreviated approximation may be deemed to be appropriate provided that there remain C_adj components that can be coupled in a successive iteration of the test or that the magnitude of the difference does not exceed a threshold such that an undesired number of iterations would be required for a successful approximation.

Returning to task 42, the system is deemed to have failed to keep up with the sensor signal if the difference between C₁ and C₂ is greater than the threshold value. In such situations, the abbreviated approximation test is temporarily terminated (48). Accordingly, the C_adj components that were connected as part of the test including those for the ΔC_approx of the chosen preceding test cycle are disconnected. Although not shown in FIG. 25 to avoid duplication, the system may proceed to perform a successive iterative approximation (SAR) of the capacitance by performing the tasks outlined in the method of, for example, FIGS. 6, 10, 13, 18, and/or 21. As such, the reader is referred to the description of those figures for a full discussion of the steps involved therein. In an implementation, the successive iterative approximation may be repeated until the difference between the selected capacitance and the unselected capacitance is less than the threshold value following which the system resumes at task 32 to perform the abbreviated approximation.

It is contemplated that the iterative approximation method of FIG. 25 may be performed in response to a request for determination by the capacitive sensor of an approximate difference in capacitance between and C₁ and C₂. As examples, the capacitive sensor may provide an indication of parameters that include as examples physical activity, posture, position, vibration, movement, acceleration, pressure, and/or other forms of displacement of an object. In one example embodiment with the method of FIG. 25 being implemented in an accelerometer, the differential capacitance value obtained by measuring the sensing elements will provide the indication of one or more such parameters.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A device for approximating a difference between two capacitive components, comprising: a first capacitive component and a second capacitive component;a capacitance approximation bank including a plurality of approximation capacitors;a capacitance adjustment module configured to connect one or more of the approximation capacitors in parallel with one of the first and second capacitive components;a memory location for storage of an indication of a first set of approximation capacitors that was previously connected in a preceding approximation test;a control module that identifies the smaller of the first and second capacitive components, that identifies the larger of the first and second capacitive components, that retrieves the indication of the first set of approximation capacitors and connects the one or more capacitors of the first set of capacitors to the smaller capacitive component, and computes a variation between the value of the larger capacitive component and the value of the smaller capacitive component connected to the first set of approximation capacitors, wherein the difference between the first and second capacitive components is determined to be equivalent to the value of the first set of approximation capacitors in response to the variation being less than or equal to a first predefined value.

2. The device of claim 1, wherein the capacitance approximation bank comprises a plurality of capacitors each of which is individually connectable to the smaller of the first and second capacitive components.

3. The device of claim 2, wherein each of the plurality of capacitors in the capacitance approximation bank may have a capacitance value different from the other capacitors in the capacitance approximation bank.

4. The device of claim 1, wherein the control module in response to the variation being greater than the first predefined value and less than or equal to a second predefined value performs an iterative search of the one or more capacitors of the capacitance approximation bank to obtain an approximate match of the capacitive difference between the first capacitive component and the second capacitive component.

5. The device of claim 4, wherein performing the iterative search comprises the control module performing a predetermined number of iterations with each iteration comprising: connecting at least one approximation capacitor in parallel to the identified smaller capacitive component;computing the difference between the value of the larger capacitive component and the combined value associated with the smaller capacitive component and the connected approximation capacitors;repeating the step of connecting and the step of computing for a plurality of iterations, a different set of one or more approximation capacitors being utilized for each iteration;responsive to performing the plurality of iterations, approximating the difference between the first and second capacitive components based on the value of the one or more approximation capacitors that are connected to the smaller capacitive component.

6. The device of claim 5, wherein a capacitance value of the selected at least one approximation capacitor is based on the level of the variation from the first predefined value.

7. The device of claim 5, further comprising defining a number of iterations based on predefined criteria and performing the step of connecting and the step of computing for each of the defined number of iterations.

8. The device of claim 7, wherein the predefined criteria includes the number of capacitors in the capacitance approximation bank.

9. The device of claim 1, wherein the control module in response to the variation being greater than the second predefined value: disconnects the first set of approximation capacitors from the smaller capacitive component; andperforms an iterative search of the one or more capacitors of the capacitance approximation bank that provides an approximate match of the capacitive difference between the first capacitive component and the second capacitive component.

10. The device of claim 1, wherein the first set of approximation capacitors comprises at least one capacitor selected from the plurality of approximation capacitors in the capacitance approximation bank.

11. The device of claim 1, wherein the control module identifies the smaller of the first and second capacitive components based on a result of a comparison of a duration of time to charge the first capacitive component and a duration of time to charge the second capacitive component.

12. The device of claim 1, wherein the control module identifies the larger of the first and second capacitive components based on a result of a comparison of power supplied to charge the first capacitive component to a first threshold and power supplied to charge the second capacitive component to a second threshold.

13. The device of claim 1, wherein the control module in response to the variation being greater than the first predefined value adjusts an interval between the current approximation test and a subsequent approximation test.

14. A method of performing an approximation test of a difference between two capacitive components, the approximation test comprising: obtaining a first value of a first capacitive component;obtaining a second value of a second capacitive component;comparing the first value to the second value, wherein the result of the comparison identifies the smaller of the first and second values corresponding to the smaller of the first and second capacitive component and identifies the larger of the first and second values corresponding to the larger of the first and second capacitive component;connecting a first set of approximation capacitors to the identified smaller capacitive component in parallel responsive to the difference between the first value and the second value exceeding a predetermined value, wherein the first set of approximation capacitors include the capacitors previously connected in a preceding approximation test;computing a variation between the value of the larger capacitive component and the combined value associated with the smaller capacitive component and the first set of approximation capacitors; anddetermining the difference between the first and second capacitive components to be equivalent to the value of the first set of approximation capacitors in response to the variation being less than a predefined value.

15. The method of claim 14, further comprising retrieving from a storage location an indication of the first set of approximation capacitors that were connected in the preceding test.

16. The method of claim 14, wherein the preceding approximation test is the test immediately prior to the current test.

17. The method of claim 14, wherein the first set of approximation capacitors comprises at least one capacitor selected from a plurality of approximation capacitors in a capacitance approximation bank.

18. The method of claim 14, wherein responsive to the variation being greater than the predefined value: disconnecting the one or more capacitors in the first set of approximation capacitors;performing an iterative search of the one or more approximation capacitors of the capacitance approximation bank that provides an approximate match of the capacitive difference between the first capacitive component and the second capacitive component.

19. The method of claim 18, wherein performing the iterative search comprises performing a plurality of iterations comprising: connecting at least one approximation capacitor in parallel to the identified smaller capacitive component;computing the difference between the value of the larger capacitive component and the value associated with the smaller capacitive component and the connected approximation capacitors;repeating the step of connecting at least one approximation capacitor and the step of computing the difference in each of the plurality of iterations using a different set of the one or more approximation capacitors; andresponsive to performing each of the iterations, approximating the difference between the first and second capacitive components based on the value of the one or more approximation capacitors that are connected to the smaller capacitive component.

20. The method of claim 19, further comprising selecting the at least one approximation capacitor to be connected based on the variation being greater than the predefined value.

21. The method of claim 18, wherein performing the iterative search comprises identifying a lowest value of one or more of the approximation capacitors that generates the smallest difference between the value of the larger capacitive component and the combined value associated with the smaller capacitive component and the connected one or more approximation capacitors.

22. The method of claim 14, wherein the first value comprises a measurement of the capacitance of the first capacitive component and the second value comprises a measurement of the capacitance of the second capacitive component.

23. The method of claim 14, wherein the first value comprises a measurement of the power supplied to charge the first capacitive component to a first predetermined value and the second value comprises a measurement of the power supplied to charge the second capacitive component to a second predetermined value.

24. The method of claim 23, wherein the measurement of the power supplied to charge the first capacitive component and the measurement of the power supplied to charge the second capacitive component comprise evaluating an amount of current supplied to the first capacitive component and the second capacitive component respectively.

25. The method of claim 14, wherein the first value comprises a duration of time to charge the first capacitive component and the second value comprises a duration of time to charge the second capacitive component.

26. The method of claim 14, further comprising adjusting an interval between the current approximation test and a subsequent approximation test responsive to the variation being greater than the predefined value.