Patent Application
20250015083
Non-Applicable
The present invention relates generally to integrated circuit wafer production through CMOS (Complementary Metal Oxide Semiconductor) fabrication, using PWELL technology, whereby a Shallow Buried Guard Ring (SBGR) structure is created using multiple boron implants, masked over a photoresist, to form a high concentration P+ doped region within each PWELL region. Specifically, this manufacturing process uses masking and multiple ion implants, implanted with high and lower implant energies suitable for forming low resistivity (P-type) doping regions, that reduce silicon resistivity in PWELL regions formed in CMOS integrated circuit layouts and minimizes (i.e., controls) ion implant defects, thereby forming a high current conduction region, low R current divider within the PWELL region, enabling high current conduction thus preventing excess transient current from biasing the local potential more positively within the PWELL region.
Shallow Buried Guard Ring (SBGR) relates to forming novel P-type doping regions (multiple structural shapes and sizes) within P-type doping regions or into PWELL regions of any distinct shape related to implementation into the CMOS or COS-MOS (complementary-symmetry metal-oxide-semiconductor) integrated circuit layout (non-invasively) by implementing high dose/high energy ion implants, using masking and high temperature annealing, to dissolve implant defects. This can be done only during the wafer manufacturing process at a CMOS generation node. SBGR can be implemented into all types of integrated circuit (IC) devices and will make each type of CMOS IC device latchup immune to both overvoltage and radiation transient upsets while operating in high or low temperature extreme environments within a wide range of temperatures (−55° C. TO >250° C.) and ambient radiation environments simultaneously. IC devices with SBGR implemented will not permanently upset and cannot be destructively “latched up” (i.e., short circuited via the creation of a low-impedance path between the power supply rails of a MOSFET circuit) which can be a single latchup event or a plurality of events leading to malfunction or complete destruction due to overcurrent.
SBGR can be (non-invasively) integrated into any CMOS device type, subcircuit or inverter design layouts in P-type silicon regions. The Shallow Buried Guard Ring (SBGR) is implemented into a silicon wafer and IC device during the manufacturing process using masking and multiple ion implants that are implanted with (high and lower implant energies) boron implant dosing suitable for forming low resistivity (P-type) doping regions that reduce silicon resistivity in PWELL regions formed in any CMOS integrated circuit layouts and minimize (controls) ion implant defects.
The SBGR structure is formed using multiple boron implants, with masking for each boron implant, to form a high concentration P+ doped region within PWELL regions in order to lower resistivity in specific regions (e.g., low doped isolation PWELL regions) that are non-invasive to NMOS transistor doping specifically forming a high current conduction region that lower the resistivity below the other PWELL regions even with decreased and increased temperatures. SBGR forms a low resistivity conducive shunt region and forms a low R current divider within the PWELL which enables high current conduction to PWELL VSS preventing excess transient current from biasing the local potential more positively within the PWELL region due to self-bias (dV)=(dI)*R where the forward bias of the N+/P− diode is proportional to the Resistivity (current path) to the VSS (supply ground voltage) terminal in PWELL and will thereby preventing activation of the Thyristor and latch up triggering in CMOS devices of any generation at low temperature and extreme high temperatures >250° C. where all preventing permanent radiation transient upset at temperatures >25° C. to >250° C. is proven.
Implementing the SBGR doping structure non-invasively into the PWELL region either below the NWELL bottom Xj (or above) will lower the silicon resistivity (within P+ doping masked regions) within the inverter PWELL region and any other IC device for selected PWELL regions in different IC layouts. SBGR is implemented with ion implantation, implant masking which can be implemented into any shape or regions below STI such as, for example, isolation regions. PTAP spacing regions is proven in TCAD simulation characterizations to prevents the forward bias of N+/P− diode from any PTAP and PWELL geometric layout location with or without use of HDBL.
SBGR can be implemented into any silicon Integrated Circuits (IC) type to create a family of high temperature IC devices, CMOS logic, microprocessors, microcontrollers, SRAM, NV memory, BCD, DRAM, FRAM, MRAM, flash, sensors, solar (photovoltaic) cells, solar inverters, ASIC devices of any ITRS generation which use either MOSFET (metal-oxide-semiconductor field-effect transistor) transistors (planar) or finFET (fin field-effect transistor) generation reducing resistivity in PWELL regions increasing hole current conduction especially when operating at high temperature ambient >250° C. to all IC ground terminals (VSS) preventing forward bias of the (N+/P−) diode and activation of the CMOS parasitic thyristor.
Silicon is atomic element #14 and is classified as a semiconductor material because undoped silicon resistivity (ρ) is very high and silicon is therefore a poor conductor. But this can be modified by implementing N and P type dopants (i.e., doping agents) into silicon to create doping regions which can be high or low concentrations and are used to further modify electrical current properties.
Silicon resistivity (doped or undoped) is described in terms of sheet resistance in units of ohm-cm2. Intrinsic silicon resistivity is too high for efficient current conduction but can be made conductive by introducing doping into silicon regions that are N-type dopants (electron negative charge carries) or P type dopants for (positive charge hole mobile carriers) to reduce this resistivity. Doping regions (differential layout regions) are accomplished by masking where dopants are implemented to control where and how much dopant is introduced into silicon regions. Doping can be implemented by chemical deposition diffusions or ion implantation which can be varied to any doping type, concentration or depth as needed to achieve electrical current conduction and/or isolation behavior proportionate to doping density and doping location.
Current conduction in silicon doped regions without diode blocking is in 3 dimensions. Any conduction in PWELL silicon regions depends on doping concentration to lower resistivity and physical sizing (volume) (L×W×H). The electrical current conductance is proportional to doping resistivity, area and length with units of (OHMS/sq) which can be converted to ohmic resistance (magnitude) as proportional to the doping regions length (X). Sheet Resistance refers to electrical current conducted in thin films used by Semiconductor wafer process engineers to measure doping regions during wafer manufacturing to control wafer doping concentrations and is measured to control the dopant uniformity (Sheet RHO) AREA regions (A)=(L*W)=Resistivity expressed as OHMS−SQ.
The patterned three-dimensional doped region that conducts electrical current through a silicon doped region is resistance (R) which is the product of sheet Rho multiplied by length (L) and divided by the width of the doping region with units of OHMS wherein R=ρ(L/A). See
The silicon resistivity in semiconductor devices is controlled by atomic doping implemented during the wafer manufacturing process using various doping methods (deposition+ diffusion or ion implantation) wherein doped regions can be uniquely tailored to create a range of resistivities. NWELL are doped with n-type phosphorous impurities or PWELL doping regions will be doped with P-type boron impurities at lower doped concentrations and MOSFET source/drain diffusions (N+ or P+) diffusion will be highly doped with resistivities closer to metal conductors for MOSFET transistors.
Below are some examples:
CMOS isolation wells (i.e., PWELL or NWELL regions) are categorized as “lightly doped regions” wherein, if current is conducted in PWELL regions, it would be characterized as high impedance (resistive to current conductions). Well doping is used to form P/N diodes for MOSFET transistor diffusions and are the electrical active area isolation regions diodes critically important to electrical conductivity as there is no other way to electrically isolate voltage and current without P/N diodes to control shorting and reduce static leakage for the MOSFET transistor or bipolar transistors.
Whenever, a transient upset event occurs (either by electrical overvoltage or an atomic particle passing thru the silicon device) the interaction with silicon causes the release of “excess”+/− mobile charge carriers that create instantaneous current that will flow to the anode or cathode electrical terminal (VDD)/(VSS). Electrons are subatomic and move thru both silicon and silicon dioxide regions and are negative charge carriers. Positive charge carriers are atomic+charge vacancy and are not mobile. Positive current require charge exchanged to migrate positive charge to the ground terminal constituting a much slower process.
Electrical current flow in silicon in electrically charged segments wherein +/− charge carries are polarized (hall current flow) with strong interactions between the charge carrying negative charge (−) carriers (electrons) and positive charge (+) carriers (holes) which seek to recombine and neutralize the excess charge. See
PWELL regions are formed in Silicon with P-type dopants at low doping concentrations which yield high resistivity values where PWELL regions are used for two main reasons:
Positive current (hole current) mobility will be slower to conduct and slower to recover due to high resistivity and poor current conduction in the PWELL regions.
High PWELL resistivity is the critical factor that contributes to latchup triggering in CMOS Integrated Circuits (ICs).
Pointedly, resistivity also increases with temperature and, when combined with low doping (high resistivity at 25° C.), further increases the conduction impedance. This effect reduces the latchup trigger current (increasing risk of latchup). All CMOS devices that operate at temperatures >25° C. are at higher risk of latching up (defined by a short circuit in the IC).
The CMOS inverter is a switch that enables resetting voltage states that can be changed by input bias to set to the output to (0V=VSS) representing a binary “0” data bit value or to supply voltage (VDD) to depicted as binary “1” data bit value and can be written or read by switching the input voltage between VSS to VDD. Multiple inverters are used in CMOS digital devices to form larger logic gates and operating instructions executed by the CPU as digital bytes or 64 bit (word) code which creates instruction commands based on Boolean logic to create the software operating systems and instruction code for programing logic processors controlled and executed by microelectronic circuits and devices. See
CMOS IC circuits however are implemented in bulk silicon material (wafers) and cannot be fully enabled with metal interconnect (alone) layout or described by voltage, current behavior and spice models.
CMOS inverters include many different silicon discrete components such as (transistors (MOSFET or bipolar), isolation well regions (NWELL and PWELL) by dopant type, transistor diffusion regions, gate electrodes, contact regions for power and ground, capacitors, inductors, resistors, and P/N diodes withing the inverter layouts which are used in larger cells implemented from a cell library which describes subcircuits made from the inverters forming subcircuits layouts that make up for the IC design and are connected with the metal interconnects.
“Latchup” or “Latching-up” is an electrical short circuit within silicon doping regions which can electrically connect power (VDD) and ground (VSS) which is caused by electrical transients that accidentally forward bias the 3 critical blocking diodes (highlighted in
Well isolation regions are formed from opposite dopants (P+ and N− and N+ and P−) wherein doping types are used to form the MOSFET diffusion regions in the “Active Areas” (i.e., silicon regions) surrounded by dielectric oxide regions (Shallow Trench Isolation (STI)) which dielectrically isolate the silicon active electrical biased areas where the MOSFET transistors are formed from other integrated circuits into device layouts connected to power and ground terminals by metal interconnect layers to form the CMOS inverter and Integrated Circuits.
CMOS digital architecture is based on inverter switching (0 and 1) data in a silicon active area which are biased well regions to keep the junction diodes in reverse bias blocking current leakage to maintain reverse static bias. VDD is the symbolic used for Positive bias and VSS refers to the ground terminal (V=0).
NWELL and PWELL regions are lightly doped to form P-type and N-type doping regions that are butted diodes (n−/p−) formed by low doping concentrations which are suitable for static biasing but with doping insufficient for current conduction. As well, silicon regions are high resistivity regions and a poor current conductors.
The three critical diodes (P+/N−, or N−/P− or N+/P−) in
The CMOS inverter is used in a digital circuit to switch voltage states at the inverter reference node from (digital 1=high voltage to a digital 0=ground voltage) that represent digital data clocked within the IC logic subcircuits that are integrated and implemented in IC devices. All inverters forming the PNPNP parasitic can trigger into latchup due to overvoltage upset or radiation transient upset at any time that will either destroy the IC device or corrupt the digital data when upset by a signal overvoltage clocking error or when exposed to “extreme environments” such as radiation and/or extreme (low or high) temperatures. Increasing temperature causes the silicon resistivity to increase which leads to local potential biasing of the well regions differentially within the well regions. This is the cause of diode forward biasing and is the main failure mechanism in all CMOS devices. The only solution possible to minimize permanent transient upsets and overvoltage failure is to address resistivity within the inverter layouts and fix it.
The invention of CMOS integrated circuits has vastly modernized society and revolutionized global communications. CMOS offers highspeed, low power microelectronic semiconductor devices which are the electronic platform for creating systems level devices like computers which can run automated logic, memory, and power management that can be integrated to create vastly automated functionality making up electrical systems on earth and in space for many applications. The IC devices used in these networks require a wide range of semiconductor IC device types, logic, memory, RF, power controller, microprocessors, microcontrollers and other related components to create modern electronic systems.
The CMOS inverter (invented in 1963) was initially used by RCA to manufacture the first integrated circuit used in the “Space Race” in the 1960S and the 1970's. Since that time the semiconductor industry has advanced IC devices by following “Moore's scaling law” with each generation reducing feature size to increase logic gate density. By 2021 leading edge IC devices (e.g., the FINFET transistor) feature sizes having reached 3 nM which are manufactured on 300 mm bulk silicon wafers. CMOS logic still depends on the CMOS inverter which continues to employ a parasitic thyristor (PNPN) and latchup remains a reliability issue in all CMOS devices to this day. Voltage scaling has eliminated destructive latchup, but the persistent non-recovery upsets persist.
High resistivity is the physical property of lightly doped silicon regions (WELLS or well regions) that make PWELLs a poor current conductor that oppose electrical current flow. In Physics materials (atomic elements), electrical properties are classified as related to electrical conduction, insulators, conductors or semiconductors. “Undoped” silicon electrical properties are classified as a semiconductor.
The CMOS inverter details, first presented in 1963, showed a common gate electrode configuration with complementary (two different) MOSFET transistors (PMOS and NMOS) connected in series which could be programed by a single common gate electrode. This common gate electrode would change the voltage state (Vin) of the inverter data node (P+ source and N+ drain) diffusions to equal VDD positive voltage or VSS zero voltage which was related to a digital value of either 1=VDD or 0=VSS corresponding to the inverter switch state. This inverter enabled developers a way to create digital data values (0 or 1) that could be combined into larger data sets, single bits, (bytes=8 bits and words=multiple bytes) which were volatile but could be written or read into the inverter data node to transmit data.
CMOS inverters are used to program voltage state which are then used to represent digital data (0 or 1) to code a digital bit combining multiple bits to form word data which forms the digital coding matrixed by electrical bit switching signals to create instructions used with Boolean logic to write data or instruction code clocked into and out of CMOS devices forming the basis of the global internet and all mass communications.
The inverter itself is used as a digital data switch, enabling electronic programmability which became the basis of new low power digital logic (complimentary MOSFETS) or CMOS. Using multiple bit logic values in multiples of 4, 8, 16, 32 and 64-bit logic (bit words), instruction code could be written which enabled complex digital control software coding for CMOS electrical devices and systems that could operate at very low power since the inverter standby power (inactive switch) is nearly zero.
CMOS devices are manufactured on bulk silicon wafers and are electrically isolated by P/N diodes. The CMOS inverter (design) inadvertently implements a parasitic thyristor which can be upset under certain conditions that activates a complementary bipolar transistor (NPN and PNP) formed as a thyristor (PNPN) within the inverter layout which could be destructive if inadvertently upset.
Activation of the thyristor is caused by external electrical stimulus which can trigger latchup, for example (1) overvoltage upsets caused by inverter signal switching or mistiming, (2) radiation particle strikes that inject mobile electron/hole carriers (e/h carriers) and/or (3) voltage supply variation (either high or low).
The CMOS inverter layout shown in
One example is Power supply (voltage) variation, Radiation particle strikes, photo carriers (sunlight exposure) and off chip high current signals in the IO's (that case ESD events) can spread to the core circuit region. These are the external stimuluses that inject current and forward bias the thyristor diodes which are further amplified (made worse) by parasitic currents sourced and amplified by the parasitic bipolar pair (either PNP, NPN, or both transistors).
Higher temperature (HT) increases silicon resistivity which exacerbates body bias in PWELL and causes the reduction in latchup trigger current (See
Activating the thyristor requires forward biasing of 3 discrete diodes (J1) P+/N−), (J2) N−/P−) and (J3) N+/P− (represented as J1, J2 and J3 in
Expressly, in
High resistivity in the N and P well regions cause a dV local potential (voltage) shift that acts to forward bias the N+/P− diode (last thyristor diode3). The initial overvoltage or radiation events are the initial activating electrical stimulus events in and of themselves are not sufficient to cause latchup in the IC device. Either stimulus will generate excess mobile charge carriers which create excess currents that interact and forward bias the thyristor diodes that activate the parasitic current flow between the blocking diodes, but in time will recombine and recover to the voltage state without causing latchup trigger. However, any increase in the operating temperature increases silicon resistivity which increases the PWELL region resistivity and causes a dV body volt potential shift that reduces the trigger current making latchup more likely to occur during operations when temperature increases above 25° C. The silicon resistivity plot vs temperature plot shown in
The current path for the thyristor displayed as curved, dashed lines from VDD=+V to VSS=OV in
Once the PNPN thyristor is activated (current mode), the only way to recover and clear the latchup state is to cycle the IC device power (on/off) before the latchup short destroys the IC device.
And while strides have been made in the field of semiconductors and integrated circuits to address the infirmities detailed above, it remains that there are inadequacies that persist in terms of constructing and maintaining a semiconductor, especially in the area of CMOS fabrication and P− well technology, to reduce resistivities in certain silicon regions and enable and facilitate current conduction and allow for operations in the presence of radiation and temperature extremes.
It is therefore the goal of inventor to remediate the deficiencies herein entailed and to provide for a new, novel device and means of overcoming these shortcomings in the prior art as detailed herein.
Although the novel features and method of use of the application are set forth above, the application itself, as well as a preferred modes of use, and advantages thereof, will best be understood by referencing to the following detailed description when read in conjunction with the accompanying drawings in view of the appended claims, wherein:
And while the invention itself and method of use are amendable to various modifications and alternative configurations, specific embodiments thereof have been shown by way of example in the drawings and are herein described in adequate detail to teach those having skill in the art how to make and practice the same. It should, however, be understood that the above description and preferred embodiments disclosed, are not intended to limit the invention to the particular embodiment disclosed, but on the contrary, the invention disclosure is intended to cover all modifications, alternatives and equivalents falling within the spirit and scope of the invention as defined within the claim's broadest reasonable interpretation consistent with the specification.
Although there are described certain features, dimensions, configurations, tolerances, and parameters constituting the present invention, and examples set forth for illustrative purposes, iterations are included without surrendering any subject matter or departing from the invention's intent. And, although the following detailed description contains specific references to several preferred embodiments, one having skill in the art will certainly appreciate that modifications, alterations and variations are within the scope of the present invention. Accordingly, the following embodiments of the invention are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention. While preferred embodiments are described in connection with the description herein, there is no intent to limit the scope to the embodiments disclosed below. On the contrary, the intent is to cover all equivalents.
As such bulk CMOS inverters that implement the SBGR doping region will be immune to latchup and destructive radiation effects. SBGR CMOS devices thereafter will operate reliably without failure due to upset events like overvoltage triggering and radiation single event effect and will operate reliably at extreme temperatures >250° C. without latching up.
Expressly,
SBGR is implemented using multiple boron ion implants that create a continuous high concentration of P-type doping region that are masked and implanted with multiple ion implants at different implant energies with boron doses tailored to minimize implant defects within the implemented SBGR structure.
The SBGR structure is an improvement (in stack juxtaposition to the commercial CMOS inverter prior art) which can be implemented non-invasively into any CMOS device type without interfering with other electrical features or doping regions.
Also, SBGR can be fully implemented (implanted and annealed) before the NWELL or PWELL implants are implanted into the commercial wafer manufacturing process making the addition of SBGR non-invasive to other doping regions formed in the CMOS wafer process. The SBGR implementation could be done remotely from the silicon foundry with wafers shipped back to the foundry ready to continue the commercial manufacturing process to final wafer processing and passivation.
The SBGR structure also enables a means to authenticate silicon wafers and die to physically validate authentic and correctly verify processes or steps of the silicon foundry production to guarantee identity, authenticity, provenance and quality.
The implementation of SBGR masking regions is implemented using the same mask overlay alignment markers formed by STI and transistor active area regions that are planarized (already patterned) and are customarily used for well implants. This optimizes SBGR implementation as the doping is completed and annealed at high temperatures using rapid annealing tailored for dissolving silicon lattice implant defects and excess silicon interstitials before other inverter doping regions (NWELL and PWELL implants) are implemented thereby avoiding interfering or counter doping the other region in the commercial wafer manufacturing process.
The SBGR structure having been implemented and annealed to remove excess interstitials, quenching is completed before well implementation enables ideal “non-invasive” integration of the SBGR structure with no thermal Dt (time and temperature) added to the baseline commercial wafer manufacturing process (which affects other doping regions). This methodology is new and more novel and is a significant improvement over prior art. It is in the contemplation of inventor of prior art that SBGR shunt method is novel and superior to BGR implementation by adding different masking methods to stop high energy implant penetrations invents new structures improve, simplifies process integration that enables integration into all IC device types, which was limitation of prior art.
SBGR can be implemented more deeply in the same layout, if desired, that would extend below NWELL junctions and deeper masked areas as suitable. In either case, the shallow or deep SBGR Pilar structure is non-invasive to the inverter diffusion diodes and MOSFET channel doping regions.
As shown in
This can be compared with commercial STI isolation in
The NWL/PWL diode breakdown voltage is high and best suited for voltage biasing to create the diode types needed for voltage isolation, transistor diffusion isolation and inverter voltage switching. The MOSFET diffusion regions (P+ diffusion) for PMOS transistor and (N+ diffusions) for NMOS transistors are connected to metal 1 (patterned layout) that make an ohmic contact with the IC metal interconnect and form the CMOS inverter. The dashed lines highlight the 3 discrete (thyristor diodes) locations (1) (Pdiff/Nwl), (2) (Nwl/Pwl) and (3) (Ndiff/Pwl) which collectively form the parasitic thyristor diode network which causes latchup trigger and failures in CMOS digital devices.
PWELL regions are lightly doped P− regions with doping concentrations wherein approximately (5e13 ions/cm3) is typical. At this concentration the PWELL is at high resistivity and is a poor conductor of current. A 1st derivative of Ohms Law (dV=dI*R) shows for commercial PWELL regions a small current magnitude causes voltage shift more positive which shows a self-biasing effect observed in PWELL regions. A small amount of current sourced from the NWELL forward biased diode (N−/P− parasitic) forward biases the PWELL local potential and this causes the N+/P− diode to forward bias, activating the NPN parasitic and triggering into full latchup following any upset event. For PWELL regions doping at 5e17 the Hole carrier mobility (+charge) is approx. 190 cm2/V−s at 25° C. and resistivity=7.2e-2 (ohms). If certain PWELL regions' boron doping concentration is increased to SBGR concentration levels (3e19) and Hole mobility is 58 cm2/V−s., current conductance is the product of (carrier mobility)*(carrier concentration) with RHO units (ohm-cm) for a 1M×1M unit area where the length of the unit area is layout spacing for the inverter. For commercial PWELL doping, the current conductivity (5e17*190)=9.5e19 ohm-cm. for SBGR the conductance is =(58*3e19)=1.7e21. SBGR is current conductivity is 17.96× higher conductance than PWELL doping.
Hole conductance depends on temperature, lower doping=higher resistivity, higher temperature=higher resistivity. Higher doping concentration=lower resistivity*(unit area) is resistance. Current conductivity (as illustrated in commercially available vs. SBGR inverter Pwell type in
SBGR implements low resistivity doping column in the center region of the PWELL which acts as a buried VSS doping terminal to extending a P+ doping regions lowering PWELL series resistance below PWELL contact regions to VSS and also increases the negative voltage potential in the silicon regions below the PWELL contact regions. Upset currents that arise from all transient upsets will be collected by the SBGR low Resistivity region and this prevents forward bias of PWELL regions during excess current conduction and blocks forward bias of the N+/p− diode with remains in a reverse bias off state. With SBGR implemented, the J3 diode can't be forward biased and latchup triggering is permanently eliminated and CMOS devices will not latchup.
The N+/P− diode (3rd diode in thyristor) is self-biasing due to high resistivity in the PWELL region which induces a dV bias (local PWELL potential) shift >0V is the key diode which activates the NPN bi-polar which initiates latchup trigger and shorts VDD to VSS. Transient upset failures (overvolt) cause bit errors as overvolt transient upsets due to timing failures will persist as a reliability risk for CMOS devices executing cause code errors.
SBGR implemented in PWELL reduces the resistivity within the PWELL region with masked ion implantation of boron to create a high concentration region that increases current conductivity to terminate the mobile and upset currents by eliminating the forward biasing of the PWELL regions during a transient upset. Prior art architecture implements a blanket HDBL boron doping layer which implants the whole wafer and was connected to surface terminals via multiple masked implants that were integrated into the wafer manufacturing process at multiple steps. While this was moderately effective, the prior art BGR structure invention was invasive to both isowells, deep NWELLS and NWELL regions (causing counter doping of n-type regions) which decreased NWELL breakdown voltage and causes shorting to VDD could not be integrated into other types of CMOS device types such as.
By modifying the doping to reduce resistivity in CMOS PWELL regions for all layouts, advanced CMOS devices will not trigger into latchup and can be operated in extreme environments like high radiation and high temperature (>25° C.). While transient upsets are unavoidable (as radiation strike or overvoltage transient conditions will still cause upset events), with SBGR implemented the upset will latchup and will not persist and allow for recovery of the upset regions to normal operation more quickly and without fear of permanent latchup.
Following the particle strike, all the thyristor diodes are forward biased #1 (P+/N−), #2 (N−/P−), #3 (N+/P) and initiate a latchup trigger event. At 3 nS the parasitic currents are increasing in magnitude. The IV plot in
The SBGR implementation forms a new type of PWELL which can support both inverter switching performance and implementation of a low resistivity region preventing latchup in operation in extreme environments such as high temperature >250° C. and radiation at the same time.
The SBGR region enables significantly higher current conduction across the PWELL region from the N/P well junction to the VSS metal terminal and high current density conduction shown in
The SBGR implementation layout example (
The novelty of the SBGR region is this region can be formed non-invasively within the inverter layout using masked implantation without use of the blanket boron layer of prior art (BGR patents) thus making it possible to control SBGR implant doping regions and doping profile depth to enable integration without interfering with other doping regions used in modern CMOS devices (deep NWELL regions for flash memory, BCD doping regions for power devices, analog devices, RF devices without degrading or electrical shorting or a combination thereof.
The depth of the boron doping region is much shallower than prior art making the SBGR far more effective (closer to upset regions) than any prior art. The SBGR doping region (shown in
The PWELL doping region can be polygon, square, rectangular, L shaped doping, or any similar or like regions, which is along the length (longer length than in width). The SBGR doping region is centered in the inverter center PWELL width region and extending below STI maximum depth and extensions alone PWELL length within the PWELL regions (parallel to NWELL Xj) and can extend its length between PWELL spacing PTAPS, (PTAP to PTAP) or any to other Pwell layout regions as shown in
SBGR doping can be short or long extended regions below STI or LOCOS regions utilized continuous doping region between PTAP region termination and other PTAPS (contracting metal) or can be implemented as a single pillar structure at the PWELL minimum VSS spacing taps spacing (or individual P+ doping regions) to form minority carrier guard rings deeper (i.e., below the silicon) to form recombination centers for minority carriers and terminate mobile electrons (lifetimes).
SBGR doping is a continuously doped region implemented below the STI extending between the PTAP regions and below STI or LOCOS dielectric regions which is implemented in all CMOS inverter PWELL regions in the CMOS IC chip design to create a low resistivity PWELL region that can be implemented into the manufacturing process and existing IC design inverter layouts consisting of a non-invasive novel CMOS doping structure that can be implemented into a CMOS device without redesign and integrated into multiple wafer manufacturing fabs.
As evidenced in the below figure,
In
SBGR implants are masked to not counter doped PWELL channel regions or other any PWELL isolation regions (shown in
The SBGR region (shown in
SBGR acts as current divider (low resistive shunt) which redirects the excess current to VSS and prevents PWELL body biasing (dV), which in turn prevents the forward biasing the N+/P− diode thus preventing the parasitic thyristor from activation. SBGR low resistivity redirects upset current away from the NMOS transistor (N+ diffusions) and prevents latchup.
Current conduction density will vary in silicon with doping concentration and spacing to the well taps (PWELL/Metal 1) ohmic contact region. Commercial CMOS inverters are contacted to VSS thru PWELL doping where uniformly low doping density (<5e13 ions/cm3) is nominal and spacing to the VSS PWELL tap can be several micros. The current resistance then relates to area and doping density as R=(rho)*(resistivity)*(L/W). The only way to reduce resistances is to increase local doping concentration (add SBGR region) that reduces the resistance in PWELL regions between PTAP gaps to distant AA region spacing. Transient upset and recovery time is proportional to current conduction, reducing resistivity minimized recovery time.
The high concentration boron doping implemented to form SBGR region can be implemented before the NWELL and PWELL regions are implanted (an abbreviated wafer processing example is described below) and is a non-invasive process integration.
Previously shown in
SBGR structure is implemented closer to the active area which makes current conducted to VSS higher and more effective in withstanding SEU upsets far superior to prior art inventions because SBGR provides the following which prior art BGR shunt does not.
The SBGR manufacturability represents a simplified process modification vs prior art as follows:
SBGR solves the CHIP/sub-circuit integration problem and enabling reliable operation in extreme environments for all multifunctional CMOS IC device types such as BCD, mixed signal, Analog, RF, high voltage IO and ASIC logic, microprocessors with embedded (Flash) memory, and the like, which can be protected from latching up in extreme environments (e.g., high temperature and radiation).
SBGR structure implements a low resistor discrete region in PWELL (which behaves as a low R component) as an improved CMOS inverter that will not latchup and can operate reliably for thousands of hours at clock without failing. This represents the “technical breakthrough needed” as called for in SCR2 DECADAL-PLAN for “Extreme Environment IoT generation” as the use of CMOS expands beyond legacy CMOS device applications, PC's, cell phones and other existing CMOS devices can be “re-purposed” and could operate in extreme environments and new applications without re-designing the IC device itself.
TCAD data shows that, with identical layout and identical PWELL doping of the CMOS inverter implemented with SBGR (special masked doping), the 130 nM CMOS inverter (
SBGR can be integrated into the commercial wafer manufacturing process for 40 nM using the same architecture as described for 130 nm with the smaller layout rules to implement SBGR in the 40 nm inverter layout below the PWELL contact region. SBGR is implemented into the PWELL region of 40 nmM CMOS inverter layouts and reduces resistivity in the 40 nm PWELL contact region non-invasively to avoid PWELL self-biasing thereby deactivates the parasitic thyristor. In this case a CMOS latchup structure is used for both overvoltage and SEU transient upset recovery.
All 40 nm SBGR CMOS devices will be latchup immune and operate at 250° C. without latching up. All 40 nm commercial CMOS devices, conversely, will latchup even at 25° C.
For each plot in
As can be seen in the recovery plots shown in
SBGR also acts to offset increased temperature effects by increasing P+ doping in certain PWELL and other masked regions which that shifts p− region potential more negatively and lower resistivity which increase upset current conduction and speeds potential recovery. The characterization of SBGR (i.e., short recover times, operation at extreme temperatures, and no latchup is observed at 250° C.), shown for 130 nm and 40 nm in the claims and figures in this disclosure, consistently show that CMOS latchup can be prevented my modifying the CMOS wafer manufacturing process to add the SBGR doping regions (using masking) into PWELL select regions and can be done “non-invasively” enabling the use of SBGR to manufacture new types of CMOS IC devices that are capable of operation (latchup immune functionality) in both (1) low and high temperature settings and (2) high radiation environments thereby decreasing transient upsets and avoiding permanent failures in many different IC device applications. SBGR technology can be implemented into smaller CMOS generations also and can make 28 nm and FINFET CMOS generations latchup immune to radiation effects and operate more reliably at high temperature capable as shown in this disclosure.
SBGR is the solution and “a technology breakthrough” needed for future IOT applications that require more robust electronic devices which can operate in higher temperature and radiation environments without failure. This is possible for a least the following:
As highlighted for CMOS generations 130 nm and below is the potential for non-destructive permanent latchup that will destroy digital data or digital control to the electronic system that can't be recovered except by power cycle. As such this is disruptive event and risk to fail safe operations for automation in the IoT generation. SBGR has in this spec shown proofs of the benefits of avoiding latchup trigging in that any CMOS system will not require “power recycle and rebooting” to restore control and performance. SBGR recovery times are orders of magnitude faster with SBGR implemented and prevents latchup triggering.
SBGR prevents latchup triggering by either overvoltage and radiation upset transients for any bias for both core and IO voltages bulk for all CMOS generations, legacy >10 μm to FinFET nodes that operate at extreme temperatures >85° C. to >than 250° C. will not trigger and will not latchup thus providing the highest reliability.
Various industries will benefit from the advancements above for all CMOS device types including: Automotive electronics HT_IC with SBGR, Space satellites RH_IC with SBGR, Missile defense RH_IC with SBGR, Aviation electronics HT_IC with SBGR, and/or High Temperature industrial electronics with SBGR that operate >125 C.
SBGR applied to solar PVC apps to increase both current and power outputs by reducing mobile carrier losses caused by recombination effects, will add to an overall increases the PVC power efficiency
A semiconductor device comprising a substrate region with first type doping impurity with high resistivity and an active area layout region for CMOS inverter that includes shallow trench dielectric isolation and two well contact regions with (1) a first and second photo mask wherein a first SBGR photo mask is aligned to integrated circuit patterned silicon active areas and dielectric regions layout with ion implantation of first p-type impurity to expressly implement a high concentration of p-type impurity with an implant concentration greater than first well impurity concentration in first well contact regions, implemented below dielectric isolation regions and at peak depth extending below dielectric isolation regions and implemented into first well silicon substrate layout regions before first well is implemented and (2) a second SBGR photo mask having a mask opening width smaller than first SBGR mask width which is aligned to first well active area layout regions and dielectric region in first well contact regions and is implanted with p-type impurity at high implant dose implementing a SBGR p-type impurity concentration greater than 1st well impurity concentration and below first well contact regions extending from the silicon surface and below dielectric isolation regions and forming ohmic doping contact with the first SBGR impurity region, below the first well contact regions and select dielectric regions, before first well is implemented that may exceed first well depth and maximum concentration doping level into the silicon substrate concentration region The first well implant mask aligned to first well active area regions where implantations of first impurity type implements a first well impurity region in silicon substrate which includes a shallow buried guard ring fully implemented in first well contact regions and a second well implant mask aligned to first well region active area with multiple implantations of second impurity type implements in the second well region with shallow buried guard ring implemented in first well contact regions.
This Example 1 of a semiconductor device where a shallow buried guard ring (SBGR) impurity structure expressly implemented in first well regions creating a uniquely low resistivity doping shunt region below said first well contact region that acts to prevent forward bias of the 1st well region keeping the thyristor J3 (N+/p− diode) in first well active areas in a reverse bias state by shunting excess hole currents throughout the low resistivity SBGR bypass low R regions to the first well contact region and VSS terminal ground and keeping the J3 diode in reverse bias block state throughout the transient upset thereby deactivating the CMOS parasitic THYRISTOR permanently and preventing latchup while operating in any extreme environment (e.g., radiation particle strike and high temperatures) without permanent failures where the SBGR type 1 conductive region comprises a unique low resistivity vertical implanted region not otherwise present within the first well and where the semiconductor (CMOS inverter) may, but does not necessarily include the following features:
Additionally, the semiconductor device as recited in claim above in Example 1 wherein the unique SBGR low resistivity shunt region (i.e., conductive region) comprises a vertical impurity region of the first conductivity type having an impurity concentration that may increase with implantation depth to a local maximum width and length below STI regions in first well and may vary with increasing depth, to form a retrograde impurity concentration of higher magnitude than first well impurity concentration.
The semiconductor device as recited above wherein the SBGR type 1 impurity conductive region implemented in first well contact regions is manufactured using bulk silicon wafers of different diameters.
The SBGR type 1 impurity region described above in Example 1 forming a low resistive, low impedance current bypass path below first well contact regions of a CMOS inverter that conducts excess transient upset currents to the VSS ground terminal thereby preventing latchup triggering, normally caused by high resistivity body biasing in first well, that causes the forward bias of the J3 thyristor diode regions during electrical overvoltage stress in CMOS inverter devices.
This same semiconductor device further exhibiting a SBGR type 1 impurity region forms a low resistive low impedance current path below first well contact regions of a CMOS inverters that conducts excess transient upset currents to the VSS ground terminal thereby preventing latchup triggering normally caused by high resistivity body biasing in first well causing a forward bias of the J3 thyristor diodes during a radiation particle strikes in CMOS inverters devices.
The same semiconductor device further displaying an SBGR type 1 impurity region forming a low resistive low impedance current path below first well contact regions of a CMOS inverters that conducts excess transient upset currents to the VSS ground terminal thereby preventing latchup triggering normally caused by the high resistivity body biasing in first that causes a forward bias of the J3 thyristor diodes operating at higher temperatures greater than 25° C. up to 250° C. and temperatures below −55 C.
A semiconductor device comprising a silicon substrate of first P-type conductivity and including active area regions and dielectric regions exhibiting a first and second photo mask well wherein (a) said first well photo mask is aligned to active areas and with P− impurity type ion implantation implements in a first well impurity doping concentration region that is greater than the silicon substrate which includes a first well contract region where said a first SBGR photo mask is aligned to a first well active area contact regions implanted with P type impurity ions which expressly implements a low resistivity SBGR impurity region that extends below the first well contact region, and below dielectric regions at silicon depth greater than dielectric region depths, implementing an SBGR impurity concentration greater than the first well impurity regions which is extendable below said first well maximum concentration to the silicon substrate concentration region and (b) the second SBGR photo mask has a mask opening diameter width greater than the first SBGR mask diameter width and is aligned to first well active area regions and multi implantations of first impurity that extends the high concentration p-type impurity region within first well contact region silicon surface to deep SBGR doping regions to make ohmic doping contact below the first well contact regions and select dielectric regions. Expressly the second well PR mask is aligned to first well active area and with implantation of n-second impurity type to implements in the second n-well region that is butted to first well and forms the CMOS twin well inverter layout which includes a first well region with a first well contact region that includes a SBGR doping region below first well contact region. Said SBGR doping region may be implemented into all CMOS generations and will prevent latchup triggering and permanent electrical failures in bulk CMOS inverter devices thereafter enabling reliable CMOS inverters and devices that can operate in extreme radiation environments and high temperatures greater than 25 C to 250 C.
The semiconductor device, specifically, illustrates a shallow buried guard ring (SBGR) impurity structure expressly implemented in first well regions creating a uniquely low resistivity doping shunt region below first well contact region that acts to prevent forward bias of the 1st well region that keeping the thyristor J3 (N+/p− diode) in first well active areas in a reverse bias state by shunting excess hole currents throughout the low resistivity SBGR bypass low R regions to the first well contact region and VSS terminal ground and keeping the J3 diode in reverse bias block state throughout the transient upset thereby deactivating the CMOS parasitic thyristor permanently and preventing latchup while operating in any extreme environment without permanent failures.
This SBGR type 1 conductive region comprises a unique low resistivity vertical implanted region not otherwise, present within the first well wherein the unique low resistivity conductive region is comprised with ohmic fill materials where the shallow buried guard ring conductive regions exists below a first well contact which comprises a conductance over its entire vertical and horizontal extent corresponding to a p-type impurity region concentration greater than 3E17 ions/cm-3 through-out its length
The first and second well regions with a SBGR impurity region implemented in first well contact regions are normally manufactured with bulk silicon substrate wafers but may be alternatively manufactured with silicon epitaxial layer grown on a bulk silicon wafer and therein formed in the silicon epitaxy layer to manufacture the CMOS inverter devices wherein the silicon substrate material with a suitable silicon layer thickness is bonded to a dielectric insulating material to form a Silicon on Insulator (SOI) wafer substrate does include a shallow buried guard ring impurity region in the first well region.
As in Example 1, one or all the second well contact regions at the substrate surface terminal may be electrically coupled to a positive voltage rail, a negative voltage rail, or a combination of both. In one embodiment of Example 2, at least one of the Shallow buried guard ring vertical layer impurity regions may be formed by high-energy ion implantation (e.g., boron). Further, the unique SBGR low resistivity shunt region conductive region may also comprises a vertical impurity region of the first conductivity type having an impurity concentration that may increase with implantation depth to a local maximum width and length below STI regions in first well, and varies with increasing depth, forms a retrograde impurity concentration of higher magnitude than first well impurity concentration.
In terms of manufacturing, the SBGR type 1 impurity conductive region implemented in first well contact regions may additionally be manufactured using bulk silicon wafers of different diameters
In operation, the SBGR type 1 impurity region forms a low resistive low impedance current by pass path below first well contact regions of a CMOS inverters that conducts excess transient upset currents to the VSS ground terminal thereby prevents latchup triggering normally caused by high resistivity body biasing in first well that causes the forward bias of the J3 thyristor diode regions during electrical overvoltage stress in CMOS inverter devices and the SBGR impurity region forms a low resistive low impedance current path below first well contact regions of a CMOS inverters that conducts excess transient upset currents to the VSS ground terminal thereby preventing latchup triggering normally caused by high resistivity body biasing in first well that causes a forward bias of the J3 thyristor diodes during a radiation particle strikes in CMOS inverters devices.
Importantly, the SBGR type 1 impurity region forms a low resistive low impedance current path below first well contact regions of a CMOS inverters that conducts excess transient upset currents to the VSS ground terminal thereby preventing latchup triggering normally caused by the high resistivity body biasing in first that causes a forward bias of the J3 thyristor diodes operating at higher temperatures greater than 25° C. up to 250° C. and temperatures below −55° C.
The silicon substrate of first P-type conductivity that includes dielectric oxide regions of certain widths, lengths and depth may be used to form at the silicon substrate surface a photovoltaic (PVC) layout with an anode contact region formed at the silicon surface exhibiting a first photo mask, a second phot mask and a third photo mask. The first photo mask is aligned to an anode contact region and multiple ion implantation of P-type ion impurity to implement a shallow buried guard ring (SBGR) p-type doping region into silicon region or regions below the anode contact region that extends continuously from the silicon surface to or below the maximum depth of the dielectric isolation regions that implements a SBGR region comprising a high concentration p-type doping region, below the PVC anode contact region, with P-type doping impurity concentration >5e17 and, following mask strip and clean, is thermally annealed. The second photo mask aligned to PVC cathode regions and with ion implantation of n-type doping impurity into a PVC cathode layout regions of which some are butted to the anode dielectric regions and extend across the surface to the cathode contact region implementing an n-type doping impurity within the PVC cathode layout regions and forming a junction diode with electric field depletion region between opposite dopant types. The anode and cathode contact regions etch and with metal deposition layer across the PVC wafer. The third photo mask is aligned to anode and cathode contact regions with a metal etch forming the PVC metal layout regions which includes an SBGR PVC low resistivity doping region below the PVC anode contact regions not otherwise present in PVC anode contact regions that increases hole carrier lifetime by forming a low resistivity low hole current impedance transport path to anode metal contact regions with an SBGR PVC.
In this third example, the silicon SBGR PVC device exhibits a shallow buried guard ring (SBGR) impurity structure which is expressly implemented below the anode contact regions at the top of the wafer thereby creating a uniquely low resistivity doping shunt region below the PVC anode contact regions that may extend below the dielectric isolation regions which increases the negative local potential of SBGR silicon doping region, below the anode contact regions, thereby increasing hole current density that is transported to anode metal contact and increases the cathode reverse bias breakdown voltage.
The SBGR PVC silicon device described herein in Example 3 exists wherein the SBGR type 1 conductive region comprises a unique low resistivity vertical implanted region not otherwise, present within PVC devices containing a unique low resistivity conductive region is comprised with multiple or mixture of different ohmic fill materials where conductive regions are present below the PVC anode contact regions further comprising a conductance over its entire vertical and horizontal extent corresponding to a p-type impurity region concentration greater than 3E17 ions/cm-3 through-out its vertical depth extension and layout lengths.
As is seen in Example 1 and 2, the SBGR PVC device of Example 3 may exhibit one or more cathode contact regions located at the substrate surface terminal regions are electrically coupled to a positive voltage rail, one or more anode contact regions at the substrate surface terminal are electrically coupled to a negative voltage rail, or a combination thereof.
The SBGR PVC device described has at least one of the Shallow Buried Guard Ring vertical impurity regions formed by a high-energy ion implant (e.g., boron) where the first conductivity type has an impurity concentration that may increase with implantation depth to a local maximum widths and lengths below dielectric isolation regions below anode contract regions, and may vary with increasing depth, forming a retrograde p-type impurity concentration. Moreover, the SBGR PVC device as s exemplified is made to exhibit the SBGR p-type impurity conductive region implemented below anode contact regions can be manufactured using bulk silicon wafers with multiple diameters, is effective in collecting mobile hole vacancy carriers at depths greater than 8 microns below the silicon surface and forms a low resistive low impedance current path below the PVC anode contact regions that increases current collection for solar spectrum wavelengths greater than 700 nm and high quantum efficiency (as shown in
The SBGR PVC device as disclosed forms a low resistive low impedance current path below the PVC anode contact region that (1) increases Pmax peak power output by more than 26% and shown in
This Example 3 is defined and described below.
Firstly, the SBGR doping structure combined with processing architecture can be applied a new type of PVC that increases both PVC short circuit current and cathode voltage biasing. Larger wafers (increasing silicon area) can used to manufactured SBGR PVC using silicon wafer manufacturing conventional processing to implement the SBGR structure and make a higher performance PVC that is implements below the anode contact region similar to SBGR latchup structure. SBGR increases mobile carrier current by reducing recombination losses from high resistivity effects. Mobile hole charge carriers can be recombined and causes shorter lifetimes which then increases current losses during mobile charge current transport to the anode/cathode metal terminals. Electrons are high mobility charge carriers and flow to nearest positive charge terminal. Hole carriers are “vacancy carriers” and charge transport requires atomic P-type dopants activated into silicon regions to enable increased carrier mobility (transport current) within the silicon lattice by P-type vacancy carriers (hopping). By increasing mobility using SBGR doping impurity implemented below anodes both mobility and voltage biasing is increased to yield more “WATTS” from the SBGR PVC device. Once the charge carrier is collected in metal, recombination ceases and current losses are minimized.
Conventional PVC currents decrease at larger wavelengths >700 nm (IR spectrum) which then shortens the PVC sunlight energy duty cycle as the afternoon solar spectrum shifts to IR wavelengths. SBGR PVC architecture aforementioned (reduces recombination effects) that enables increase current at IR wavelengths to yield more current collection at wavelengths >700 nm and TCAD simulation show increases quantum efficiency of the SBGR PVC vs Conventional PVC. SBGR doping combined with PVC top side dielectric isolation structures increases the PVC diode break down voltage. With the anode PVC terminal increased more negatively (−0.2V) by SBGR doping effect higher hole currents is observed at wavelengths >600 nM. The TCAD simulation also shows the electron current is increased at longer wavelengths (vs conventional that is not increased) due to negative potential in anode and closer proximity acts by field deflection of electrons (oppositely charged HALL effects) to increase transport to cathode terminal within lifetime losses at wavelengths >700 nM figure S3 shows electron current is near 100% overlapped with available current from B1 beam (red) for SBGR case and not for Commercial PVC case.
The Silicon substrate thickness used for manufactured semiconductor devices is approximately 725 microns. For PVC applications the silicon substrate thickness is thinned to 160 microns. Thinning decreases the hole carrier transport distance to the anode contacts formed at the back side of the PVC substrate. PVC substrates are intrinsic which is low p-type doping with high resistivity and imparts low hole carrier mobility that increases hole recombination rate.
The solar spectrum peak intensity is near 800 nM that has a penetration depth of (10 uM), the deepest absorption depth is 1000 nm at IR wavelengths. This means hole carrier transport from the P/N diode generation region to the back side anode contact is transporting thru absorption layers where electrons are being generated that hole carriers would recombine with and not optimum.
Firstly, the SBGR doping structure can be combined with wafer processing techniques used in semiconductors to implement SBGR doping regions below the anode contact region formed at the top of the PVC with a dielectric isolation region that would decrease carrier transport distance to the anode.
Combining the SBGR doping with a dielectrically isolated top side anode contact region increases the hole current collection volume (area) more than 46% and anode hole current magnitude by more than 260% (1.87e-6 A vs 5.12e-7 A) as is compared in
The photoelectric effect first explained and published by A. Einstein stated electron/hole pair emission will occur in materials whenever irradiated by light or energetic photons. This is also true for heavy ions shown in
For PVC, the material used is silicon and a single photon can be absorbed with energy transfer that generates a Positive and Negative charge pair in which the negative charge carriers are electrons and mobile positive charge carriers are “vacancy carriers”. Hole charge transport in silicon requires atomic P-type dopants activated in the silicon lattice that increases doping carrier density needed to enhance mobile charge conduction (hole current). By placing the anode contact at the surface, this reduces the hole transport distance between the hole photo generation regions that are collected by the anode terminal contact region before they are recombined with electrons, becoming a neutral charge and reduces PVC hole current losses.
Conventional PVC current output decrease at larger wavelengths >700 nm (IR spectrum) which shortens the PVC sunlight duty cycle as the peak solar spectrum shifts to longer wavelengths. SBGR PVC architecture is shown increase anode current by decreasing transport current path to top side anode and increasing extraction volume regions.
This detailed description refers to specific examples in the drawings and illustrations. These examples are described in sufficient detail to enable those skilled in the art to practice the inventive subject matter. These examples also serve to illustrate how the inventive subject matter can be applied and amendable to various purposes or embodiments. Other embodiments are included within the inventive subject matter, as logical, mechanical, electrical, and other changes can be made to the example embodiments described herein. Features of various embodiments described above, however essential to the example embodiments in which they are incorporated, do not limit the inventive subject matter as a whole, and any reference to the invention, its elements, operation, and application are not limiting as a whole, but serve only to define these example embodiments. Thus, the scope of this disclosure should be determined by the appended claims, in light of the present disclosure, along with their legal equivalents. All structural and functional equivalents to the elements of the above-described invention(s) will be known to a person having ordinary skill in the art and are expressly incorporated herein by reference as is to be read into the present claims. This detailed description does not, therefore, limit embodiments of the invention, which are defined only by the appended claims. Each of the embodiments described herein are contemplated as falling within the inventive subject matter, which is set forth in the following claims.
U.S. Provisional Patent Application No. 63/274,363 filed Nov. 1, 2021 PCT Application No. PCT/US22/79006 filed Oct. 31, 2022
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US22/79006 | 10/31/2022 | WO |
