Claims
- 1. An isolation member embedded in a silicon layer of an integrated circuit comprising:
- a silicon layer on a substrate having at least one isolation trench;
- a conformal layer in said at least one isolation trench, said conformal layer consisting of a first layer of silicon nitride followed by a second layer of silicon oxide and has a thickness of 5 to 10 nm.; and
- an oxide filler over said conformal layer and having a thickness sufficient to fill said at least one isolation trench.
- 2. The isolation member of claim 1 further comprising a thermal oxide layer between said conformal layer and said trench.
- 3. An isolation member embedded in a silicon layer of an integrated circuit comprising:
- a silicon layer on a substrate having at least one isolation trench;
- a conformal layer in said at least one isolation trench, said conformal layer consisting of a first layer of silicon nitride followed by a second layer of silicon oxynitride and has a thickness of 5 to 10 nm.; and
- an oxide filler over said conformal layer and having a thickness sufficient to fill said at least one isolation trench.
- 4. The isolation member of claim 3 further comprising a thermal oxide layer between said conformal layer and said trench.
Parent Case Info
This is a division of application Ser. No. 08/790,226, filed Jan. 28, 1997, now U.S. Pat. No. 5,763,315.
US Referenced Citations (14)
Non-Patent Literature Citations (1)
Entry |
M. R. Poponiak and P. J. Tsang, "Formation of Thick Si.sub.3 N.sub.4 or Si.sub.x O.sub.y N.sub.z On Substrate By Anodnitridization", IBM Technical Disclosure Bulletin, vol. 19, No. 03, Aug. 1976, p. 905. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
790266 |
Jan 1997 |
|