Patent Application
20070217247
Embodiments of the invention relate generally to the field of integrated circuit design, specifically to methods, apparatuses, and systems associated with and/or having fuse cells.
Microprocessor speed is ever-increasing to keep pace with consumer and competitive demands. In order to provide the volume of data required to productively exploit the increased speed, larger and larger caches are being incorporated into the new generation of microprocessors. In addition, due to the increasing cost of chip manufacturing, redundancies of the large caches, sometimes using fuse technology, are further incorporated to improve yield by replacing defective elements with spare elements.
Although larger cache with spare elements has the benefit of more effectively taking advantage of increased microprocessor speed, of particular concern with larger cache size and redundancy is the accompanying decrease in area-efficiency.
Embodiments of the present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings. Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof wherein like numerals designate like parts throughout, and in which is shown by way of illustration embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of embodiments in accordance with the present invention is defined by the appended claims and their equivalents.
Various operations may be described as multiple discrete operations in turn, in a manner that may be helpful in understanding embodiments of the present invention; however, the order of description should not be construed to imply that these operations are order dependent.
The description may use perspective-based descriptions such as up/down, back/front, and top/bottom. Such descriptions are merely used to facilitate the discussion and are not intended to restrict the application of embodiments of the present invention.
For the purposes of the present invention, the phrase “A/B” means A or B. For the purposes of the present invention, the phrase “A and/or B” means “(A), (B), or (A and B)”. For the purposes of the present invention, the phrase “at least one of A, B, and C” means “(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C)”. For the purposes of the present invention, the phrase “(A)B” means “(B) or (AB)” that is, A is an optional element.
The description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present invention, are synonymous.
In various embodiments, plurality of fuse cells 12 may comprise one or more fuse devices 18. A fuse cell 12 in accordance with various embodiments of the present invention is shown in
In various embodiments, sense amplifier 14 may be variously formed and/or configured. For example, sense amplifier 14 may be a generic current mirror-based sense amplifier with one reference branch as a current source, and one or more current mirror branches as a repeater.
Depending on the application, sharing sense amplifier 14 may require scheduling of voltage output from plurality of fuse cells 12 in order for sense amplifier 14 to generate an accurate signal based on received voltage(s) from fuse cells 12. Put another way, sensing one fuse cell 12 at a time may be done in order to accurately read each fuse cell 12 because a sense amplifier 14 may not be able to parse through voltages to determine which fuse cell 12 output which voltage(s). Thus, in various embodiments, sense amplifier 14 may be coupled to plurality of fuse cells 12 to asynchronously sense one or more voltages output by plurality of fuse cells 12 so that one fuse cell 12 at a time may be selected for outputting voltage(s) to sense amplifier 14. For instance, a first of plurality of fuse cells 12 may be selected to output a first one or more voltages during a first time period, the first one or more voltage(s) being sensed by sense amplifier 14 and the unselected fuse cells 12 not outputting any voltage during the same first time period. Then, a second of plurality of fuse cells 12 may be selected to output a second one or more voltages during a second (different) time period, which is then sensed by sense amplifier 14 and the unselected fuse cells 12 not outputting any voltage during the second time period. A method in accordance with various embodiments of the present invention may continue these operations as necessary and/or desired.
Scheduling of voltage output from plurality of fuse cells 12 may comprise providing a cell select signal to one of plurality of fuse cells 12. In various ones of these embodiments, fuse array 1 may comprise cell select signal source 26, an embodiment of which is shown in
With respect to fuse cells 12, fuse cells 12 may be variously configured in any manner known in the art. For instance, in various embodiments plurality of fuse cells 12 may comprise any number of fuse devices 18, depending on the application. An embodiment of a fuse cell 12 having two fuse devices 18 is shown in
Fuse array 1 may comprise a programming circuitry 22, depending on the application. In various ones of these embodiments, programming circuitry 22 may be coupled to one of the fuse cells 12 and configured to program one or more of fuse devices 18 of fuse cells 12. For instance, in various embodiments and as shown in
Still referring to programming circuitry 22, in various embodiments one or more of programming circuitry 22 may include one or more switchable conductive path devices 38, 40, 42, 44. Depending on the application, switchable conductive path devices 38, 40, 42, 44 may be arranged in serial or parallel. Further, switchable conductive path devices 38, 40, 42, 44 may be PMOS or NMOS devices. In some of these embodiments, one or more PMOS or NMOS devices may have different threshold voltages from other PMOS or NMOS devices of fuse cell 12. In various embodiments, serially-arranging switchable conductive path devices 38, 40, 42, 44 may accrue certain benefits, including, for example, increased tolerance to high voltages. A programming circuitry 22 comprising serially-arranged switchable conductive path devices 38, 40, 42, 44 is shown in
Fuse cell 12 may comprise other circuitry or devices in various embodiments in accordance with the present invention. In various embodiments, fuse cell 12 may comprise circuitry including, for example, any one or more of additional sense amplifier circuitry, high voltage protection circuitry, various control signal sources, one or more flip-flop circuits to store the sensed data from sense amplifier 14, etc. In alternate embodiments, other various circuitry devices and/or design topologies may be enlisted, depending on the desired use and function of fuse cell 12.
Illustrated in
Fuse blocks 6 incorporating fuse arrays 1 in accordance with the present invention may be variously configured. For instance, a fuse block 6 may incorporate different types of fuse cells 12, including, for example, single-ended and/or double-ended fuse cells 12. In embodiments in which both single-ended and double-ended fuse cells 12 are enlisted, single-ended fuse cells 12 and double-ended fuse cells 12 may be separated into different fuse arrays 1 within a fuse block 6 thereby using different sense amplifiers 14, i.e., each fuse array 1 comprises a single type of fuse cell 12, either single-ended fuse cells 12 or double-ended fuse cells 12. Further, in various embodiments, a fuse array 1 of fuse block 6 may have a different number of fuse cells 12 than other fuse arrays 1 in fuse block 6. However, in various other embodiments, all fuse arrays 1 within fuse block 6 may include the same number of fuse cells 12.
As shown in
Although certain embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent embodiments or implementations calculated to achieve the same purposes may be substituted for the embodiments shown and described without departing from the scope of the present invention. Those with skill in the art will readily appreciate that embodiments in accordance with the present invention may be implemented in a very wide variety of ways. This application is intended to cover any adaptations or variations of the embodiments discussed herein. Therefore, it is manifestly intended that embodiments in accordance with the present invention be limited only by the claims and the equivalents thereof.
