Patent Application
20080260090
This application claims the benefit of Taiwan application Serial No. 96114165, filed Apr. 20, 2007, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The invention relates in general to a shift register for a data driver and more particularly to a shift register with power saving capability.
2. Description of the Related Art
For the internal flip-flops of the shift register, both the flip-flop outputting the enabled data signal and the flip-flop receiving this signal need to operate. Inevitably, the flip-flops operate in response to the clock signal and thus consume energy, which may be unnecessary, regardless of whether the flip-flop receives or outputs the enabled data signal.
The invention is directed to a shift register. For each shift registering unit of the shift register, selection circuitry is used to individually control whether to output a clock signal to a flip-flop of each shift registering unit. For the shift registering unit which will receive the enabled data signal, the selection circuitry sends the clock signal CK to the flip-flop of the shift registering unit so that the flip-flop of the shift registering unit can receive the enabled data signal. After the flip-flops of the shift registering unit all output the enabled data signals or when it is still early for the flip-flop of the shift registering unit to receive the enabled data signal, the selection circuitry stops sending the clock signal CK to the flip-flop of the shift registering unit so that the flip-flop of the shift registering unit is disabled. In this way, power saving can be achieved.
According to a first aspect of the invention, a shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to the flip-flop according to a first selection signal, wherein before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the flip-flop according to the first selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal.
According to a second aspect of the invention, a shift register apparatus is provided for use in a data driver. The shift registering apparatus includes a shift register. The shift register selectively receives a clock signal. The shift register includes a first selection circuit and a shift registering unit. The first selection circuit selectively sends the clock signal according to a first selection signal. The shift registering unit includes a flip-flop and a second selection circuit. The second selection circuit selectively sends the clock signal sent from the first selection signal to the flip-flop according to a second selection signal. Before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the second selection circuit according to the first selection signal. Before the flip-flop receives the data signal that is enabled, the second selection circuit sends the clock signal to the flip-flop according to the second selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal.
The invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
An embodiment of the invention is directed to a shift registering apparatus for use in a data driver. The shift registering apparatus includes a shift register for selectively receiving a clock signal. The shift register includes a first selection circuit and a shift registering unit. The first selection circuit selectively sends the clock signal according to a first selection signal. The shift registering unit includes a flip-flop and a second selection circuit. The second selection circuit selectively sends the clock signal sent from the first selection signal to the flip-flop according to a second selection signal. Specifically, before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the second selection circuit according to the first selection signal. In addition, before the flip-flop receives the data signal that is enabled, the second selection circuit sends the clock signal to the flip-flop according to the second selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal.
A shift registering apparatus 200 in
A partial structure of the shift register 210, as indicated in
The shift registering unit 310 includes FFs 311, 312 to 31N and a second selection circuit 330. The shift registering unit 320 includes FFs 321, 322 to 32N and a second selection circuit 340.
The first selection circuit 350 selectively outputs the clock signal CK to the second selection circuits 330 and 340 according to a selection signal CS1. When the first selection circuit 350 outputs the clock signal CK to the second selection circuits 330 and 340, the second selection circuits 330 and 340 sends the clock signal CK to the two groups of FFs 311 to 31N and 321 to 32N according to the selection signals BS1 and BS2, respectively. In this embodiment, the first selection circuit 350, second selection circuits 330 and 340 can be implemented as logical circuitry such as AND gates, for example.
An example of the operation of the first selection circuit 350 of the shift register is described. Before the first FF 311 of the first shift registering unit 310 of the shift register 210 will or is about to receive the enabled data signal DT, the selection signal CS1 is at a logic level of “1”. As a result, the first selection circuit 350 is enabled to output the clock signal CK to the second selection circuits 330 and 340 so that all of the FFs of the shift register 210 can correctly output the enabled data signals.
After the last FF of the last shift registering unit of the shift register 210 outputs the enabled data signal D1, the FFs of the shift register 210 will not need operation any longer. The selection signal CS1 is then set to a logic level of “0”. As such, the first selection circuit 350 stops outputting the clock signal CK to the second selection circuits 330 and 340 so as to disable the FFs of the shift register 210, resulting in saving power.
Similar to the operation of the first selection circuit 350, before the first FF (not shown) of the first shift registering unit of the shift register 220 receives the enabled data signal D1, a first selection signal CS2 (not shown) is set to a logic level of “1”. Thus, the first selection circuit (not shown) of the shift register 220 is enabled to output the clock signal CK to the second selection circuit (not shown) of the shift register 220 so that all of the FFs of the shift register 220 correctly output the enabled data signals.
An example of the operation of the shift registering unit 310 and shift registering unit 320 is depicted here. Before the first FF 311 of the shift registering unit 310 receives the enabled data signal DT, the first selection circuit 350 of the shift register 210 sends the clock signal CK to the second selection circuit of the FFs of the shift register 210.
After the first selection circuit 350 outputs the clock signal CK to the second selection circuit of each shift registering unit and before the FF 311 of the shift registering unit 310 receives the enabled data signal DT, the second selection circuit 330 of the shift registering unit 310 sends the clock signal CK to the FFs 311 to 31N according to the selection signal BS1. As a result, the FF 311 is able to correctly receive the enabled data signal DT, and output an enabled data signal Q11 to the next FF 312. The other FFs of the shift registering unit 310 operate likewise.
Thus, when receiving an enabled data signal orderly, the FFs 311 to 31N can output the enabled data signals correctly according to the clock signal CK. In this embodiment, the selection signal BS1 is at a logic level of “1” and thus the second selection circuit 330 outputs the clock signal CK.
After the last FF 31N of the shift registering unit 310 outputs an enabled data signal Q1N, the FFs 311 to 31N all have outputted their enabled data signals and thus the FFs 311 to 31N will not need operation any longer. As a result, the second selection circuit 330 of the shift registering unit 310 stops sending the clock signal CK to the FFs 311 to 31N according to the selection signal BS1 so as to disable the FFs 311 to 31N, thereby saving power. In this embodiment, the selection signal BS1 is at a logic level of “0” then and the second selection circuit 330 stops outputting the clock signal CK.
For example, the enabled data signal Q1N is the enabled data signal D1 in
With respect to the shift registering unit 320, before the FF 321 receives the enabled data signal Q1N sent from the FF 31N, the second selection circuit 340 sends the clock signal CK to the FFs 321 to 32N of the shift registering unit 320. The selection signal BS2 is at a logic level of “1” then so that the second selection circuit 340 outputs the clock signal CK.
Thus, when receiving the enabled data signal Q1N, the first FF 321 of the shift registering unit 320 can send an enabled data signal Q21 to the next FF 322 correctly. Similarly, the other FFs of the shift registering unit 320 also send the enabled data signals to the respective next FFs.
For the shift register as in this embodiment, the following approach can be employed to control whether to output a clock signal to FFs of each shift registering unit. The control approach is exemplified by the operation of the shift registering unit 310 and shift registering unit 320 as follows.
Before the j-th FF of the shift registering unit 310, such as the (N−1)th FF, receives an enabled data signal, the selection signal BS2 is at a logic level of “0”. The second selection circuit 340 of the shift registering unit 320, according to the selection signal BS2, does not output the clock signal CK to the shift registering unit 320 so that the FFs 321 to 32N of the shift registering unit 320 are disabled, thereby saving power.
When the j-th FF of the shift registering unit 310 receives an enabled data signal, the selection signal BS2 is switched to a logic level of “1”. The second selection circuit 340 of the shift registering unit 320, according to the selection signal BS2, sends the clock signal CK to the FFs 321 to 32N of the shift registering unit 320. As a result, the FF 321 is enabled to, after receiving the enabled data signal Q1N, correctly output the enabled data signal Q21 to the next FF 322, according to the clock signal CK. The other FFs of the shift registering unit 320 can operate in a similar manner as mentioned above and thus their operation will not repeated for the sake of brevity.
When the y-th FF of the shift registering unit 320, such as the second FF 322, receives an enabled data signal, all FFs of the shift registering unit 310 have outputted their enabled data signals and then all FFs will not need to operation any longer. Thus, the selection signal BS1 is switched to a logic level of “0”. The second selection circuit 330 of the shift registering unit 310 stops sending the clock signal CK to the FFs 311 to 31N of the shift registering unit 310 according to the selection signal BS1 so as to disable the FFs 311 to 31N, thereby saving power.
The structure and operation of the shift register 210 are illustrated as above. The structure and operation of the shift register 220 and second selection circuit 330 are similar to those of the shift register 210, and thus details will not be repeated for the sake of brevity.
In the embodiment, the selection signals CS1, BS1, and BS2 for the shift register 210 are enabled or disabled according to the clock signal CK. For example, the shift registering apparatus 200 includes three shift registers, each shift register includes M shift registering units, and each shift registering unit includes N FFs. Each FF receives or outputs the enabled data signal for the same period of the clock signal CK. The selection signal CS1 is enabled before the first FF of the first shift registering unit of the shift register 210 receives an enabled data signal. Conversely, the selection signal CS1 is switched to be disabled after the last FF of the last shift registering unit outputs the enabled data signal D1. Therefore, the selection signal CS1 is enabled for M×N periods every 3×M×N periods. The selection signal BS1 is enabled before the first FF 311 of the shift registering unit 310 receives an enabled data signal. Conversely, the selection signal BS1 is switched to be disabled after the last FF 31N outputs the enabled data signal. Therefore, the selection signal BS1 is enabled for N periods every 3×M×N periods. For the other shift registers and shift registering units, their selection signals are enabled or disabled according to the clock signal CK likewise.
In one embodiment, a signal detector is employed to generate the selection signals CS1, BS1, and BS2 for the shift register 210. The signal detector detects whether the selection signals selection signals CS1, BS1, and BS2 are enabled or not. For the other shift register, the signal detectors can also be used to output their selection signals and detect whether the selection signals are enabled or not.
In the above embodiment, the shift registering apparatus has three shift registers, for example. In practical applications, the apparatus may employ shift registers more than three ones. In other embodiments, a shift registering apparatus includes at least one shift register or more than three ones, and each shift register employs a selection circuit to determine whether to output a clock signal to its internal shift registering unit, according to a received or outputted enabled data signal, thereby saving power; all of these embodiments are also within the scope of the invention
The following discusses the advantage of the shift registering apparatus of the above embodiment. As compared to the conventional one, the shift registering apparatus according to the embodiment of this invention has the advantage of power saving. In this regard, it is noticed that conventionally, the clock signal is always provided to the registers regardless of whether the registers do receive an enabled data signal or not. Specifically, even if all FFs of the register have not received or outputted enabled data signals, the FFs is still operating and consuming power unnecessarily.
By contrast, the shift registering apparatus according to the above embodiment includes a number of registers, each of which corresponds to a first selection circuit to individually control whether to output a clock signal to internal shift registering units. For each shift register, the first selection circuit outputs the clock signal to the second selection circuit of the shift registering unit when the FFs will or is about to receive or output enabled data signals. When the FFs have not outputted enabled data signals or it is still early for the FFs to receive the enabled data signals, the first selection circuit stops outputting the clock signal to the second selection circuit. In this way, the shift registering apparatus according to the embodiment can save power as compared to the conventional one.
In addition, in the shift register, for each shift registering unit, the second selection circuit is employed to individually control whether to output the clock signal to the FFs of each shift registering unit. For the shift registering unit, its second selection circuit begins to send the clock signal to the internal FFs of the shift registering unit until the shift registering unit will or is about to receive the enabled data signal so that the FFs of the shift registering unit is able to receive the enabled data signals. When the FFs of the shift registering unit have outputted enabled data signals or it is still early for the FFs of the shift registering unit to receive the enabled data signals, the second selection circuit stops sending the clock signal to the FFs of the shift registering unit so that the FFs of the shift registering unit are disabled, thus resulting in saving power further.
In another embodiment, a shift registering apparatus can be designed as a bi-directional shift registering apparatus including at least one bi-directional shift register. Each bi-directional shift register includes at least one shift registering unit.
In addition, every FF receives a control signal SHL. The control signal SHL is employed to select the direction by which the data signal is sent. Each specific FF receives the data signal from the FF connected left or right to the specific FF.
Further, the first selection circuit 450 of the shift register 400 and the second selection circuits 430 and 440 operate in a manner similar to that mentioned above. For the sake of brevity, their operation will not be repeated.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 096114165 | Apr 2007 | TW | national |
