SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR CONVERTING AN ANALOG INPUT SIGNAL TO A DIGITAL OUTPUT SIGNAL AT A SAMPLING FREQUENCY

Abstract

The present disclosure proposes a sigma-delta analog-to-digital converter for converting an analog input signal to a digital output signal at a sampling frequency (fs). The sigma-delta analog-to-digital converter includes a chopper circuit configured to shift the analog input signal from an original frequency to a chopper frequency (fchop=fs/N) to generate a chopped analog signal, where N is a positive integer with N≥1. A chopper period includes a first chopper phase and a second chopper phase. The sigma-delta analog-to-digital converter also includes a timing circuit configured to adjust at least one of a duration of the first chopper phase or a duration of the second chopper phases according to (N/2−k)·Ts, with k being an odd integer equal to or larger than 1, and Ts being a sampling period 1/fs of the sigma-delta analog-to-digital converter.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to German Patent Application No. 102023101437.4 filed on Jan. 20, 2023, the content of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present disclosure generally relates to analog-to-digital converters (ADCs) and, more particularly, to chopped sigma-delta analog-to-digital converters (ΣΔ-ADCs).

BACKGROUND

Many modern devices, such as vehicles, for example, include a plurality of sensors. Such sensors may be “fast switching” to provide information about an operation of a device to a digital control unit, which can take an action based upon the information. For example, the control unit of a vehicle may be configured to control fuel injection components based on a position of a camshaft. To this end, a toothed wheel may be affixed to the camshaft and a magnetic sensor, e.g., Hall sensor, may be arranged to detect teeth on the wheel. The sensor may output an analog signal that indicates the presence (or absence) of a tooth. The sensor's analog signal may be converted to a digital signal by an ADC to enable digital processing components in the control unit to determine the position of the camshaft. Both ADCs and digital-to-analog converters (DACs) can employ sigma-delta (ΣΔ) modulation. A ΣΔ ADC may first encode an analog signal using high-frequency ΣΔ modulation, and then apply a digital filter to form a higher-resolution but lower sample-frequency digital output. A ΣΔ DAC may encode a high-resolution digital input signal into a lower-resolution but higher sample-frequency signal that may be mapped to voltages, and then may be smoothed with an analog filter. In both cases, the temporary use of a lower-resolution signal may simplify circuit design and improve efficiency.

ΣΔ ADCs and ΣΔ DACs may be combined with chopping. Chopping refers to a technique that can be used to cancel offset voltages and other low frequency errors. Chopper circuits are a type of electrical circuit in which a signal to be amplified is modulated (chopped), amplified and demodulated again. By using such a technique, a zero-point error (or offset error) and a so-called 1/f noise of an amplifier can be shifted to a frequency band which is not of interest. Chopper circuits can be used, for example, in bandgap circuits that provide a defined reference voltage, but can also be used in other applications where a signal needs to be processed, such as in ΣΔ-ADCs. An offset that arises within various amplifiers of a 24 modulator can generally be nulled out, either by local chopping or auto-zeroing an amplifier. However, other offset errors cannot be removed by these means. A solution implemented on these ADCs may be to chop an entire analog signal chain within the ADC. This may remove any offset and low frequency errors, giving extremely low offset errors and drift.

Aliasing of quantization noise may be a problem, especially for chopping frequencies lower than a ΣΔ modulator's sampling frequency. Thus, the use of conventional chopping in a ΣΔ-ADC may lead to undesired quantization noise effects.

SUMMARY

Thus, there may be a desire to improve the noise behavior of chopped ΣΔ-ADCs. This need is addressed by apparatuses and methods in accordance with the independent claims. Possibly advantageous implementations are addressed by the dependent claims.

According to a first aspect, the present disclosure provides a ΣΔ-ADC for converting an analog input signal to a digital output signal at a sampling frequency f_s. The ΣΔ-ADC includes a chopper circuit which is configured to shift the analog input signal from an original frequency to a chopping frequency f_chop to generate a chopped analog signal. The chopping frequency can be expressed as f_chop=f/N, wherein N is a positive integer with N≥1. A chopping period includes a first chopping phase and a second chopping phase. The ΣΔ-ADC also includes a timing circuit which is configured to adjust a duration of at least one of the first and the second chopping phases according to (N/2−k)·T_s, with k being an odd integer equal to or larger than 1, e.g., k=1, 3, 5, 7, . . . (2n−1), with n=1, 2, 3, 4, 5 . . . .

T_s=1/f_s denotes a sampling period of the ΣΔ-ADC. By adjusting the duration of at least one of the first and the second chopping phases (or chopper windows) according to (N/2−k)·T_s, an integrator and the chopping phases may be desynchronized, leading to an improved quantization noise behavior of ΣΔ-ADCs in accordance with implementations of the present disclosure.

In some implementations, the timing circuit of the ΣΔ-ADC is configured to adjust the duration of both the first and the second chopping phase according to (N/2−k)·T_s. As the first and the second chopping phase together form the chopping period, a duration of the chopping period may then correspond to T_chop=(N−2k)·T_s.

In some implementations, the timing circuit is configured to adjust the duration of the first chopping phase according to (N/2−k)·T_s and the duration of the second chopping phase according to N/2 T_s. As the first and the second chopping phase together form the chopping period, the duration of the chopping period may then correspond to T_chop=(N−k)·T_s.

In some implementations, k=1, such that the duration of the chopping period may then correspond to T_chop=(N−2)·T_s or T_chop=(N−1)·T_s.

In some implementations, the ΣΔ-ADC further includes a spinning Hall-sensor coupled to an input of the ΣΔ-ADC. A spinning period of the spinning Hall-sensor includes a first spinning phase, a second spinning phase, a third spinning phase, and a fourth spinning phase. The timing circuit may be configured to adjust respective durations of two of the four spinning phases according to an odd number of sampling periods and respective durations of the other two of the four spinning phases according to an even number of sampling periods of the ΣΔ-ADC.

In some implementations, the timing circuit is configured to adjust the duration of the first spinning phase according to (N/4−1)·T_s, the duration of the second spinning phase according to (N/4)·T_s, the duration of the third spinning phase according to (N/4−1)·T_s, and the duration of the fourth spinning phase according to (N/4)·T_s. As the first to fourth spinning phases together form the spinning period, the duration of the spinning period may then correspond to T_spin=(N−2k)·T_s (e.g., k=1).

In some implementations, the ΣΔ-ADC includes a first chopper circuit which is configured to shift the analog input signal from the original frequency to the chopping frequency to generate the chopped analog signal, a difference amplifier (e.g., an operational transconductance amplifier, OTA) which is configured to amplify the chopped analog signal to generate an amplified analog signal, and a second chopper circuit which is configured to demodulate the amplified analog signal to generate a demodulated analog signal having a signal component at the original frequency. The second chopper circuit may thus be coupled to the output of the difference amplifier.

In some implementations, ΣΔ-ADC further includes an integrator circuit coupled to an output of the second chopper circuit, and a coarse ADC (e.g., 1-bit ADC) configured to convert an output of the integrator to the digital output signal.

In some implementations, the ΣΔ-ADC further includes a feedback path coupled between an output of the coarse (e.g., 1-bit) ADC (e.g., comparator) and an output of the difference amplifier or an input of the second chopper circuit. The feedback path may include a chopped digital-to-analog converter (DAC). In the time domain, the analog input signal and the output of the DAC are differentiated, providing a differentiated signal. This differentiated signal is presented to the integrator, whose output progresses in a negative or positive direction. The slope and direction of the output of the integrator is dependent on the sign and magnitude of its input signal. At the time the output of the integrator equals a comparator reference signal, the output of the coarse ADC (e.g., comparator) switches from negative to positive, or positive to negative.

According to a second aspect, the present disclosure provides an ΣΔ-ADC for converting an analog input signal to a digital output signal at a sampling frequency f_s. The ΣΔ-ADC includes a chopper circuit which is configured to shift the analog input signal from an original frequency to a chopping frequency to generate a chopped analog signal. A chopping period includes a first chopping phase and a second chopping phase. The ΣΔ-ADC includes also includes a timing circuit which is configured to adjust a duration of at least one of the first and the second chopping phases according to (4n−1)·T_s, with n being an integer equal to or larger than 1, and T_s being a sampling period 1/f_s of the ΣΔ-ADC.

In some implementations, the timing circuit is configured to adjust the duration of both the first and the second chopping phases according to (4n−1)·T_s. As the first and the second chopping phase together form the chopping period, a duration of the chopping period may then correspond to T_chop=(8n−2)·T_s.

In some implementations, the timing circuit is configured to adjust the duration of the first chopping phase according to (4n−1)·T_s and the duration of the second chopping phase according to (4n)·T_s. As the first and the second chopping phase together form the chopping period, a duration of the chopping period may then correspond to T_chop=(8n−1)·T_s.

In some implementations, the ΣΔ-ADC further includes a spinning Hall-sensor coupled to an input of the ΣΔ-ADC. A spinning period of the spinning Hall-sensor includes a first spinning phase, a second spinning phase, a third spinning phase, and a fourth spinning phase. The timing circuit may be configured to adjust the duration of the first spinning phase according to (2n−1)·T_s, the duration of the second spinning phase according to 2n·T_s, the duration of the third spinning phase according to (2n−1)·T_s, and the duration of the fourth spinning phase according to 2n·T_s. As the first and the second spinning phase together may form the first chopping phase, a duration of the first chopping phase may then correspond to T_ph1=(4n−1)·T_s. As the third and the fourth spinning phase together may form the second chopping phase, a duration of the second chopping phase may then also correspond to T_ph2=(4n−1)·T_s.

According to a yet a further aspect, the present disclosure provides method for converting an analog input signal to a digital output signal at a sampling frequency, f_s. The method includes an act of shifting the analog input signal from an original frequency to a chopping frequency to generate a chopped analog signal, wherein a chopping period includes a first chopping phase and a second chopping phase; and an act of adjusting a duration of at least one of the first and the second chopping phases according to (4n−1)·T_s, with n being an integer equal to or larger than 1, and T_s being a sampling period 1/f_s of the ΣΔ-ADC.

BRIEF DESCRIPTION OF THE DRAWINGS

Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

FIG. 1 illustrates a schematic block diagram of a sensor system that comprises a chopped ΣΔ-ADC for converting an analog input signal at an original frequency to a digital output signal;

FIG. 2 shows a block diagram of an example implementation of a chopped ΣΔ-ADC circuit;

FIGS. 3A and 3B illustrate further implementations of chopped integrators that may be used inside ΣΔ-ADCs;

FIG. 4A illustrates a timing of a sampling clock signal and a chopping clock signal; and

FIG. 4B illustrates a timing of a sampling clock signal, a chopping clock signal, and a spinning clock signal.

DETAILED DESCRIPTION

Some examples are now described in more detail with reference to the enclosed figures. However, other possible examples are not limited to the features of these implementations described in detail. Other examples may include modifications of the features as well as equivalents and alternatives to the features. Furthermore, the terminology used herein to describe certain examples should not be restrictive of further possible examples.

Throughout the description of the figures same or similar reference numerals refer to same or similar elements and/or features, which may be identical or implemented in a modified form while providing the same or a similar function. The thickness of lines, layers and/or areas in the figures may also be exaggerated for clarification.

When two elements A and B are combined using an “or”, this is to be understood as disclosing all possible combinations, e.g., only A, only B as well as A and B, unless expressly defined otherwise in the individual case. As an alternative wording for the same combinations, “at least one of A and B” or “A and/or B” may be used. This applies equivalently to combinations of more than two elements.

If a singular form, such as “a”, “an” and “the” is used and the use of only a single element is not defined as mandatory either explicitly or implicitly, further examples may also use several elements to implement the same function. If a function is described below as implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity. It is further understood that the terms “include”, “including”, “comprise” and/or “comprising”, when used, describe the presence of the specified features, integers, steps, operations, processes, elements, components and/or a group thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and/or a group thereof.

Sensors often introduce errors into an analog signal they output due to intrinsic characteristics of the sensors themselves. For example, an offset error may be included in an analog signal output by a Hall sensor. However, spinning current techniques may help to distinguish between the error and the sensor signal as will be described in more detail below. The spinning technique may transform the offset error component in the Hall sensor signal into a high frequency error (called offset ripple) while the sensor signal remains low frequency or DC.

ADCs may include amplifiers and/or integrators that may also introduce an offset error into the signals they process. The amplifier or integrator offset error may add to the offset error introduced by the Hall sensor. To compensate for the sensor's offset error and/or amplifier offset error, some ADCs include choppers. Choppers are circuits that modulate the sensor signal to a higher frequency, which shifts the sensor output signal to a higher frequency range (e.g., the chopping frequency f_chop) while the offset error component remains in a lower frequency range, making the offset error component easier to distinguish from the signal component. For the purposes of this description, the modulated sensor signal at the chopping frequency output by chopper circuit will be referred to as being “chopped” or “at the chopping frequency” to be contrasted with sensor signals that have not been modulated or have been re-modulated to the original frequency of the sensor signal, which will be referred to as having “the original frequency.”

FIG. 1 illustrates a schematic block diagram of a sensor system that comprises an ADC circuit 100 for converting an analog input signal VIN (e.g., a sensor signal) at an original frequency to a digital output signal DOUT.

The analog input signal VIN may be assumed to be band-limited, and the signal bandwidth may be assumed to be much lower than a sampling frequency f_s of the ADC circuit 100. The analog input signal VIN may include a signal component and an offset error component that may be introduced by a sensor (not shown) measuring a physical quantity (e.g., a Hall sensor to measure a magnetic field). To account for the offset error component in the analog input signal VIN, the ADC circuit 100 comprises a chopper circuit 110 coupled between an input terminal 102 for the analog input signal VIN and an input terminal of a chopped ΣΔ-ADC circuit 120 (i.e., a chopped SD-ADC circuit). The chopper circuit 110 may be considered external to the chopped ΣΔ-ADC circuit 120 and comprises a modulator circuit which is clocked at a chopping frequency f_chop. The chopping frequency f_chop may be lower than the sampling frequency f_s of the ADC circuit 100. A chopping clock signal at chopping frequency f_chop may be derived from a sampling clock signal at sampling frequency f_s using a timing circuit 130. Timing circuit 130 may be configured to perform a frequency division of the sampling frequency f_s to obtain the chopping clock signal at chopping frequency f_chop. For example, this may be done via a counter which triggers a state transition (from low to high, or from high to low) of the chopping clock signal after j sampling clock pulses. The chopper or modulator circuit 110 is configured to shift the analog input signal VIN from its original frequency (which may be DC) to the chopping frequency f_chop to generate a chopped analog signal 112 at the input of chopped ΣΔ-ADC circuit 120.

In accordance with various example implementations, the ΔΣ-ADC circuit 120 may include an amplifier circuit for the chopped analog signal 112 to generate an amplified analog signal, a demodulator circuit clocked at the chopping frequency f_chop and configured to demodulate the amplified analog signal to generate a demodulated analog signal having a signal component at the original frequency. The ΣΔ-ADC circuit 120 may further include a ΣΔ modulator and a digital/decimation filter to convert the analog input signal VIN to a digital output signal 122 (DOUT). The ΣΔ modulator may coarsely sample the analog input signal VIN at a very high rate into a 1-bit stream. The digital/decimation filter may then take this sampled data and convert it into a high-resolution, slower digital code. While most converters have one sampling rate, a ΣΔ-ADC has two—the input sampling rate/frequency f_s and an output data rate (f_D).

A block diagram of an example implementation of ADC circuit 100 for converting an analog input signal VIN at an original frequency to a digital output signal DOUT is shown in FIG. 2.

The chopped ΣΔ-ADC circuit comprises a (oversampling) ΣΔ-modulator 220. The ΣΔ-modulator 220 includes a forward path 221 and a feedback path 225. The forward path 221 may include a pair of analog chopper circuits 110A/110B, a voltage to current converter (OTA) 222 which contains an offset of its own, an integrator 223, and a coarse ADC (e.g., 1-bit comparator) 224 clocked at the sampling frequency/rate f_s. The integrator 223 has the effect of shaping quantization noise to higher frequencies. OTA 222 may convert the differential voltage VIN between its non-inverting and inverting input to currents at its outputs. OTA 222 may also be referred to as difference (or differential) amplifier. Recall that the sensor signal VIN from the Hall sensor (or another sensor type) may be a very small nearly DC signal with an offset error that is caused by intrinsic characteristics of the Hall sensor. The analog chopper 110A multiplies the analog sensor signal VIN by a square wave having the chopping frequency f_chop and amplitudes of +1 and −1. The resulting chopped analog input signal 112 has a signal component corresponding to a square wave having period T_chop=1/f_chop and an offset error component that is DC.

The OTA 222 may then be used to amplify the chopped analog input signal 112. The OTA 222 may also introduce a DC amplifier offset error that adds to the DC offset error of the Hall sensor. After the chopped analog input signal 112 is amplified, the amplified signal at the output of OTA 222 may be demodulated by the second analog chopper circuit 110B to generate a signal in which the sensor component of the signal component has its original low frequency while the offset component (including both the Hall and amplifier offset) is an AC signal at the chopping frequency f_chop. The coarse ADC 224 converts the output of the integrator 223 to a digital value, which is the digital output signal DOUT of the ΣΔ-modulator 220.

The feedback path 225 of the ΣΔ-modulator 220 may include a (chopped) DAC (also called ΣΔ-DAC) 226 to convert the digital output signal DOUT to analog for combination with the output signal of OTA 222. The combination may be a difference between the amplified signal at the output of OTA 222 and the output signal of chopped-DAC 226. Thus, a difference may be obtained in current domain at the output of OTA 222. The chopped analog input signal 112 may thus be differentiated in current domain at the output of OTA 222. This differentiated signal (difference between the amplified signal at the output of OTA 222 and the output signal of chopped-DAC 226) is presented to the second analog chopper circuit 110 and to integrator 223, whose output progresses in a negative or positive direction. The slope and direction of the output of the integrator 223 is dependent on the sign and magnitude of the differentiated signal. At the time the differentiated signal equals the coarse ADC's (comparator's) 224 reference voltage, the output of the coarse ADC 224 switches from negative to positive, or positive to negative, depending on its original state. The output value DOUT of the coarse ADC 224 is clocked back into the 1-bit DAC 226, as well as clocked out to a digital filter stage (not shown).

When the choppers 110 change state at its half periods (chopping phases) (changing amplitudes from 1→−1, or from 1→−1), the chopped analog input signal 112 changes its polarity, causing a current spike due to the charging of parasitic capacitors (not shown) at the input of the OTA 222. The differential chopped analog input signal 112 is mostly provided by the OTA 222 via integration capacitors. However, the feedback signal is chopped again, making it independent of chopping edge direction. The feedback signal is then integrated on the integration capacitors (C_int), resulting in a sampled input-referred error signal. Any mismatch of the parasitic or integration capacitors will result in sampling of quantization noise also at f_chop.

The skilled person having benefit from the present disclosure will appreciate that ΣΔ-ADC circuit designs are not limited to the example of FIG. 2. Further options of chopped integrators that may be used in ΣΔ-ADCs are sketched in FIGS. 3A and 3B.

The chopping frequency f_chop for chopper circuit(s) 110 in ΣΔ-ADCs may be derived from the input sampling rate/frequency f_s of the coarse ADC 224 using timing circuit 130. The chopping frequency f_chop may be higher than the original frequency of the analog input signal VIN (which may even be DC) but lower than the input sampling frequency f_s. As shown in the example of FIG. 4A, the chopping rate/frequency may correspond to f_chop=f/N, where N denotes an integer larger than 1. In the present disclosure, the following notation will be applied: T_chop=1/f_chop denotes the chopping period, T_ph denotes the duration of a chopping phase Φ, and T_s=1/f_s denotes the sampling period (FIG. 2). A chopping period T_chop usually comprises a first chopping phase Φ₁ (here: low) of duration T_ph1 and a second chopping phase Φ₂ (here: high) of duration T_ph2 with T_ph1+T_ph2=T_chop. During the first chopping phase Φ₁ the input of the chopped ΣΔ-ADC circuit 120 may be coupled to a first pair of (Hall) sensor terminals, during the second chopping phase Φ₂, the input of the chopped ΣΔ-ADC circuit 120 may be coupled to a different second pair of (Hall) sensor terminals.

As shown in FIG. 4A, the chopping period may conventionally correspond to T_chop=N·T_s, where N is 2i (e.g., an even number, i=1, 2, 3, 4, 5, . . . ). Sometimes, the chopping period T_chop may correspond to (2^m+1)·T_s. The durations T_ph1, T_ph2 may conventionally equally correspond to T_chop/2=N/2·T_s, where N/2 may also be an even number. Sometimes, N/2 may correspond to 2 ml. Such a conventional relationship between chopping periods and sampling period T_s may lead to undesired aliasing of quantization noise. High frequency quantization noise may fold-back into the signal band.

Conventionally, the durations T_ph1, T_ph2 of the chopping phases Φ₁, Φ₂ are adjusted equally such that T_ph1=T_ph2=N/2·T_s. According to implementations of the present disclosure, however, timing circuit 130 may be configured to adjust a duration of at least one of the two chopping phases Φ₁, Φ₂ different from N/2·T_s. In accordance with implementations of the present disclosure, the timing circuit 130 may be configured to adjust a duration T_ph1, T_ph2 of at least one of the first and the second chopping phases Φ₁, Φ₂ according to (N/2−k)·T_s, with k being an odd integer equal to or larger than 1, e.g., k=1, 3, 5, 7, 9, . . . . In some implementations, N/2 may correspond to 2^m (e.g., N=2^m+1), m being an integer equal to or larger than 1. This is, in contrast to conventional ΣΔ-ADC designs, where the durations T_ph1, T_ph2 of the first and the second chopping phases Φ₁, Φ₂ are set according to (N/2)·T_s, implementations of the present disclosure propose to set the duration of at least one of the first and the second chopping phases Φ₁, Φ₂ according to (N/2−k)·T_s, e.g., T_ph1=(N/2−k)·T_s and/or T_ph2=(N/2−k)·T_s. This may desynchronize the integrator 223 of the ΣΔ-ADC circuit 120, 224 and the chopping phases Φ₁, Φ₂, which may lead to an improved noise behavior of ΣΔ-ADCs in accordance with implementations of the present disclosure.

In one example implementation, the timing circuit 130 of the ΣΔ-ADC 120 may be configured to adjust the durations T_ph1, T_ph2 of both the first and the second chopping phase Φ₁, Φ₂ according to (N/2−k)·T_s, e.g., T_ph1=(N/2−k)·T_s and T_ph2=(N/2−k)·T_s. As the first and the second chopping phase Φ₁, Φ₂ together form the chopping period T_chop, a duration of the chopping period may then correspond to T_chop=(N−2k)·T_s. That is, the proposed chopping period T_chop is shorter than N·T_s. In the example of FIG. 4A, j may correspond to (N/2−k). That is, the counter of timing circuit 130 may trigger a state transition between the first chopping phase Φ₁ and the second chopping phase Φ₂ (or vice versa) after j=(N/2−k) sampling periods. In the example of FIG. 4B, k1+k2 may correspond to (N/2−k). That is, the counter of timing circuit 130 may trigger a state transition between the first chopping phase Φ₁ and the second chopping phase Φ₂ (or vice versa) after k1+k2=(N/2−k) sampling periods.

In another example implementation, the timing circuit 130 of the ΣΔ-ADC 120 may be configured to adjust the duration of the first chopping phase Φ₁ according to T_ph1=(N/2−k)·T_s and the duration of the second chopping phase Φ₂ according to T_ph2=N/2·T_s. As the first and the second chopping phase together form the chopping period, the duration of the chopping period may then correspond to T_chop=(N−k)·T_s. Also in such implementations, the chopping period T_chop is shorter than N·T_s. In the example of FIG. 4B, k1+k2 may correspond to (N/2−k) and k3+k4 may correspond to N/2. That is, the counter of timing circuit 130 may trigger a state transition between the first chopping phase di and the second chopping phase Φ₂ (or vice versa) after k1+k2=(N/2−k) sampling periods and the state transition between the second chopping phase Φ₂ and the first chopping phase Φ₁ (or vice versa) after another k3+k4=N/2 sampling periods.

Implementations of the present disclosure may optionally also be combined with a spinning Hall-sensor coupled to the input 102 of the ADC circuit 100. Hall sensors typically have an offset drift, which leads to an unpredictable and time-varying output error. Such offsets in Hall sensors can be reduced using a spinning current scheme, in which a bias current of a Hall sensor is spatially rotated around the Hall sensor while the output signals are time-averaged. This can reduce offset and offset drift. As can be seen in FIG. 4B, the chopping period T_chop may comprise four spinning phases: a first spinning phase T_sp1, a second spinning phase T_sp2, a third spinning phase T_sp3, and a fourth spinning phase T_sp4. That is, T_chop=T_sp1+T_sp2+T_sp3+T_sp4. The first and second spinning phases T_sp1, T_sp2 take place during the first chopping phase Φ₁, e.g., T_ph1=T_sp1+T_sp2. The third and fourth spinning phase T_sp3, T_sp4 take place during the second chopping phase Φ₂, e.g., T_ph2=T_sp3+T_sp4.

During the first spinning phase T_sp1 (during first chopping phase Φ₁), current flows across first terminals of the Hall sensor, so that a Hall voltage can be tapped at second terminals of the Hall sensor. During the second spinning phase T_sp2 (during first chopping phase Φ₁), current flows across second terminals of the Hall sensor, so that a Hall voltage can be tapped at the first terminals of the Hall sensor. During the third spinning phase T_sp3 (during second chopping phase Φ₂), current flows across the first terminals of the Hall sensor, so that a Hall voltage can be tapped at the second terminals of the Hall sensor. During the fourth spinning phase T_sp4 (during second chopping phase Φ₂), current flows across the second terminals of the Hall sensor, so that a Hall voltage can be tapped at the first terminals of the Hall sensor.

Conventionally, durations of the four spinning phases are adjusted equally. For example, T_sp1=T_sp2=T_sp3=T_sp4=N/4·T_s. According to implementations of the present disclosure, however, timing circuit 130 may be configured to adjust durations of the four spinning phases differently. That is, at least one duration of at least one of the four spinning phases T_sp1, T_sp2, T_sp3, T_sp4 may differ from another duration of another one of the four spinning phases T_sp1, T_sp2, T_sp3, T_sp4. The timing circuit 130 may be configured to adjust a duration of at least one of the four spinning phases T_sp1, T_sp2, T_sp3, T_sp4, according to an odd number of sampling periods T_s while others are adjusted according to even numbers of sampling periods T_s.

For example, timing circuit 130 may be configured to adjust respective durations of two of the four spinning phases T_sp1, T_sp2, T_sp3, T_sp4 according to an odd number of sampling periods T_s and respective durations of the other two of the four spinning phases according to an even number of sampling periods T_s. In an example implementation, the timing circuit 130 may be configured to adjust the duration of the first spinning phase according to T_sp1=(N/4−k)·T_s (with k=1, 3, 5, 7, 9, . . . ), the duration of the second spinning phase according to T_sp2=(N/4)·T_s, the duration of the third spinning phase according to T_sp3=(N/4−k)·T_s, and the duration of the fourth spinning phase according to T_sp4=(N/4)·T_s. This is under the assumption that N/4 is an equal number (e.g., N/4=2^m−1, with m≥2). In this case, T_ph1=T_sp1+T_sp2=(N/4−k)·T_s+N/4·T_s=(N/2−k)·T_s and T_ph2=T_sp3+T_sp4=(N/4−k)·T_s+N/4·T_s=(N/2−k)·T_s. This results in a chopping period of T_chop=(N−2k)·T_s. In the example of FIG. 4A, k1 may correspond to (N/4−k). That is, the counter of timing circuit 130 may trigger a first state transition (from low to high, or from high to low) of the spinning clock signal after k1=(N/4−k) sampling periods. The counter of timing circuit 130 may then trigger a second state transition (from low to high, or from high to low) of the spinning clock signal after further k2=N/4 sampling periods. The counter of timing circuit 130 may then trigger a third state transition (from low to high, or from high to low) of the spinning clock signal after further k3=(N/4−k) sampling periods. The counter of timing circuit 130 may then trigger a fourth state transition (from low to high, or from high to low) of the spinning clock signal after further k4=N/4 sampling periods. Then the whole chopping/spinning cycle may be repeated.

For another example, the timing circuit 130 may be configured to adjust the duration of the first spinning phase according to T_sp1=(N/4−k)·T_s (with k=1, 3, 5, 7, 9, . . . ), the duration of the second spinning phase according to T_sp2=N/4·T_s, the duration of the third spinning phase according to T_sp3=N/4·T_s, and the duration of the fourth spinning phase according to T_sp4=N/4·T_s. In this case, T_ph1=T_sp1+T_sp2=(N/4−k)·T_s+N/4·T_s=(N/2−k)·T_s and T_ph2=T_sp3+T_sp4=N/4·T_s+N/4·T_s=N/2 T_s. This results in a chopping period of T_chop=(N−k)·T_s.

The proposed modifications to the timing of chopping and/or spinning may lead to an improved quantization noise behavior of ΣΔ-ADCs in accordance with implementations of the present disclosure.

ASPECTS

The following provides an overview of some Aspects of the present disclosure:

Aspect 1: A sigma-delta analog-to-digital converter (ΣΔ-ADC) configured to convert an analog input signal to a digital output signal at a sampling frequency (f_s), the ΣΔ-ADC comprising: a chopper circuit configured to shift the analog input signal from an original frequency to a chopper frequency (f_chop) to generate a chopped analog signal, wherein f_chop=f_s/N, and N is a positive integer with N≥1, wherein a chopper period comprises a first chopper phase and a second chopper phase; and a timing circuit configured to adjust at least one of a duration of the first chopper phase or a duration of the second chopper phase according to (N/2−k)·T_s, with k being an odd integer equal to or larger than 1, and T_s being a sampling period 1/f_s of the ΣΔ-ADC.

Aspect 2: The ΣΔ-ADC of Aspect 1, wherein the timing circuit is configured to adjust the duration of both the first chopper phase and the duration of the second chopper phase according to (N/2−k)·T_s.

Aspect 3: The ΣΔ-ADC of any of Aspects 1-2, wherein the timing circuit is configured to adjust the duration of the first chopper phase according to (N/2−k)·T_s and adjust the duration of the second chopper phase according to (N/2)·T_s.

Aspect 4: The ΣΔ-ADC of any of Aspects 1-3, wherein k=1.

Aspect 5: The ΣΔ-ADC of any of Aspects 1-4, further comprising: a spinning Hall-sensor coupled to an input of the ΣΔ-ADC, wherein a spinning period comprises four spinning phases, including a first spinning phase, a second spinning phase, a third spinning phase, and a fourth spinning phase, wherein the timing circuit is configured to adjust respective durations of a first two of the four spinning phases according to an odd number of sampling periods T_s and adjust respective durations of a second two of the four spinning phases according to an even number of sampling periods T_s.

Aspect 6: The ΣΔ-ADC of Aspect 5, wherein the timing circuit is configured to adjust the duration of the first spinning phase according to (N/4−k)·T_s, adjust the duration of the second spinning phase according to (N/4)·T_s, adjust the duration of the third spinning phase according to (N/4−k)·T_s, and adjust the duration of the fourth spinning phase according to (N/4)·T_s.

Aspect 7: The ΣΔ-ADC of any of Aspects 1-6, comprising: a first chopper circuit configured to shift the analog input signal from the original frequency to the chopper frequency to generate the chopped analog signal; a difference amplifier configured to amplify the chopped analog signal to generate an amplified analog signal; and a second chopper circuit configured to demodulate the amplified analog signal to generate a demodulated analog signal having a signal component at the original frequency.

Aspect 8: The ΣΔ-ADC of Aspect 7, further comprising: an integrator coupled to an output of the second chopper circuit; and a coarse ADC configured to convert an output of the integrator into the digital output signal.

Aspect 9: The ΣΔ-ADC of Aspect 8, further comprising: a feedback path coupled between an output of the coarse ADC and an input of the of the second chopper circuit, the feedback path comprising a chopped digital-to-analog converter (DAC).

Aspect 10: A sigma-delta analog-to-digital converter (ΣΔ-ADC) configured to convert an analog input signal to a digital output signal at a sampling frequency (f_s), the ΣΔ-ADC comprising: a chopper circuit configured to shift the analog input signal from an original frequency to a chopper frequency to generate a chopped analog signal, wherein a chopper period comprises a first chopper phase and a second chopper phase; and a timing circuit configured to adjust at least one of a duration of the first chopper phase or a duration of the second chopper phase according to (4n−1)·T_s, with n being an integer equal to or greater than 1, and T_s being a sampling period 1/f_s of the ΣΔ-ADC.

Aspect 11: The ΣΔ-ADC of Aspect 10, wherein the timing circuit is configured to adjust the duration of the first chopper phase and the duration of the second chopper phase according to (4n−1)·T_s.

Aspect 12: The ΣΔ-ADC of any of Aspects 10-11, wherein the timing circuit is configured to adjust the duration of the first chopper phase according to (4n−1)·T_s and adjust the duration of the second chopper phase according to 4n·T_s.

Aspect 13: The ΣΔ-ADC of Aspect 11, further comprising: a spinning Hall-sensor coupled to an input of the ΣΔ-ADC, wherein a spinning period comprises a first spinning phase, a second spinning phase, a third spinning phase, and a fourth spinning phase, wherein the timing circuit is configured to adjust a duration of the first spinning phase according to (2n−1)·T_s, adjust a duration of the second spinning phase according to 2n·T_s, adjust a duration of the third spinning phase according to (2n−1)·T_s, and adjust a duration of the fourth spinning phase according to 2n·T_s.

Aspect 14: A method for converting an analog input signal to a digital output signal at a sampling frequency (f_s) of a sigma-delta analog-to-digital converter (ΣΔ-ADC), the method comprising: shifting the analog input signal from an original frequency to a chopper frequency to generate a chopped analog signal, wherein a chopper period comprises a first chopper phase and a second chopper phase; and adjusting a duration of at least one of the first chopper phase or the second chopper phase according to (4n−1)·T_s, with n being an integer equal to or greater than 1, and T_s being a sampling period 1/f_s of the ΣΔ-ADC.

Aspect 15: A system configured to perform one or more operations recited in one or more of Aspects 1-14.

Aspect 16: An apparatus comprising means for performing one or more operations recited in one or more of Aspects 1-14.

The aspects and features described in relation to a particular one of the previous examples may also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the features into the further example.

Examples may further be or relate to a (computer) program including a program code to execute one or more of the above methods when the program is executed on a computer, processor or other programmable hardware component. Thus, steps, operations or processes of different ones of the methods described above may also be executed by programmed computers, processors or other programmable hardware components. Examples may also cover program storage devices, such as digital data storage media, which are machine-, processor- or computer-readable and encode and/or contain machine-executable, processor-executable or computer-executable programs and instructions. Program storage devices may include or be digital storage devices, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media, for example. Other examples may also include computers, processors, control units, (field) programmable logic arrays ((F)PLAs), (field) programmable gate arrays ((F)PGAs), graphics processor units (GPU), application-specific integrated circuits (ASICs), integrated circuits (ICs) or system-on-a-chip (SoCs) systems programmed to execute the steps of the methods described above.

It is further understood that the disclosure of several steps, processes, operations or functions disclosed in the description or claims shall not be construed to imply that these operations are necessarily dependent on the order described, unless explicitly stated in the individual case or necessary for technical reasons. Therefore, the previous description does not limit the execution of several steps or functions to a certain order. Furthermore, in further examples, a single step, function, process or operation may include and/or be broken up into several sub-steps, -functions, -processes or -operations.

If some aspects have been described in relation to a device or system, these aspects should also be understood as a description of the corresponding method. For example, a block, device or functional aspect of the device or system may correspond to a feature, such as a method step, of the corresponding method. Accordingly, aspects described in relation to a method shall also be understood as a description of a corresponding block, a corresponding element, a property or a functional feature of a corresponding device or a corresponding system.

The following claims are hereby incorporated in the detailed description, wherein each claim may stand on its own as a separate example. It should also be noted that although in the claims a dependent claim refers to a particular combination with one or more other claims, other examples may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly proposed, unless it is stated in the individual case that a particular combination is not intended. Furthermore, features of a claim should also be included for any other independent claim, even if that claim is not directly defined as dependent on that other independent claim.

Claims

1. A sigma-delta analog-to-digital converter (ΣΔ-ADC) configured to convert an analog input signal to a digital output signal at a sampling frequency (fs), the ΣΔ-ADC comprising: a chopper circuit configured to shift the analog input signal from an original frequency to a chopper frequency (fchop) to generate a chopped analog signal, wherein fchop=fs/N, and N is a positive integer with N≥1,wherein a chopper period comprises a first chopper phase and a second chopper phase; anda timing circuit configured to adjust at least one of a duration of the first chopper phase or a duration of the second chopper phase according to (N/2−k)·Ts, with k being an odd integer equal to or larger than 1, and Ts being a sampling period 1/fs of the ΣΔ-ADC.

2. The ΣΔ-ADC of claim 1, wherein the timing circuit is configured to adjust the duration of both the first chopper phase and the duration of the second chopper phase according to (N/2−k)·Ts.

3. The ΣΔ-ADC of claim 1, wherein the timing circuit is configured to adjust the duration of the first chopper phase according to (N/2−k)·Ts and adjust the duration of the second chopper phase according to (N/2−k)·Ts.

4. The ΣΔ-ADC of claim 1, wherein k=1.

5. The ΣΔ-ADC of claim 1, further comprising: a spinning Hall-sensor coupled to an input of the ΣΔ-ADC, wherein a spinning period comprises four spinning phases, including a first spinning phase, a second spinning phase, a third spinning phase, and a fourth spinning phase,wherein the timing circuit is configured to adjust respective durations of a first two of the four spinning phases according to an odd number of sampling periods Ts and adjust respective durations of a second two of the four spinning phases according to an even number of sampling periods Ts.

6. The ΣΔ-ADC of claim 5, wherein the timing circuit is configured to adjust the duration of the first spinning phase according to (N/4−k)·Ts, adjust the duration of the second spinning phase according to (N/4−k)·Ts, adjust the duration of the third spinning phase according to (N/4−k)·Ts, and adjust the duration of the fourth spinning phase according to (N/4−k)·Ts.

7. The ΣΔ-ADC of claim 1, comprising: a first chopper circuit configured to shift the analog input signal from the original frequency to the chopper frequency to generate the chopped analog signal;a difference amplifier configured to amplify the chopped analog signal to generate an amplified analog signal; anda second chopper circuit configured to demodulate the amplified analog signal to generate a demodulated analog signal having a signal component at the original frequency.

8. The ΣΔ-ADC of claim 7, further comprising: an integrator coupled to an output of the second chopper circuit; anda coarse ADC configured to convert an output of the integrator into the digital output signal.

9. The ΣΔ-ADC of claim 8, further comprising: a feedback path coupled between an output of the coarse ADC and an input of the of the second chopper circuit, the feedback path comprising a chopped digital-to-analog converter (DAC).

10. A sigma-delta analog-to-digital converter (ΣΔ-ADC) configured to convert an analog input signal to a digital output signal at a sampling frequency (fs), the ΣΔ-ADC comprising: a chopper circuit configured to shift the analog input signal from an original frequency to a chopper frequency to generate a chopped analog signal, wherein a chopper period comprises a first chopper phase and a second chopper phase; anda timing circuit configured to adjust at least one of a duration of the first chopper phase or a duration of the second chopper phase according to (4n−1)·Ts, with n being an integer equal to or greater than 1, and Ts being a sampling period 1/fs of the ΣΔ-ADC.

11. The ΣΔ-ADC of claim 10, wherein the timing circuit is configured to adjust the duration of the first chopper phase and the duration of the second chopper phase according to (4n−1)·Ts.

12. The ΣΔ-ADC of claim 10, wherein the timing circuit is configured to adjust the duration of the first chopper phase according to (4n−1)·Ts and adjust the duration of the second chopper phase according to 4n·Ts.

13. The ΣΔ-ADC of claim 11, further comprising: a spinning Hall-sensor coupled to an input of the ΣΔ-ADC, wherein a spinning period comprises a first spinning phase, a second spinning phase, a third spinning phase, and a fourth spinning phase,wherein the timing circuit is configured to adjust a duration of the first spinning phase according to (2n−1)·Ts, adjust a duration of the second spinning phase according to 2n·Ts, adjust a duration of the third spinning phase according to (2n−1)·Ts, and adjust a duration of the fourth spinning phase according to 2n·Ts.

14. A method for converting an analog input signal to a digital output signal at a sampling frequency (fs) of a sigma-delta analog-to-digital converter (ΣΔ-ADC), the method comprising: shifting the analog input signal from an original frequency to a chopper frequency to generate a chopped analog signal, wherein a chopper period comprises a first chopper phase and a second chopper phase; andadjusting at least one of a duration of the first chopper phase or a duration of the second chopper phase according to (4n−1)·Ts, with n being an integer equal to or greater than 1, and Ts being a sampling period 1/fs of the ΣΔ-ADC.