Claims
- 1. A signal phase adjustment circuit, comprising:
a clock phase modification circuit to modify a phase of an input clock signal and to output a phase modified clock signal; an input signal adjustment circuit to receive an input data signal and to transmit the data signal, and which operates based on the phase modified clock signal output from the clock phase modification circuit; a reception determination unit to determine a reception status of the data signal transmitted from the input signal adjustment circuit based on a pre-set fixed pattern signal and the data signal transmitted from the input signal adjustment circuit; and a control unit to control an amount of phase modification of the clock phase modification circuit based on the determination results of the reception determination unit, wherein the control unit determines an amount of phase modification from upper and lower limits of an amount of phase modification of a region, among stable phase regions, having a continuous region width of a specified value or more.
- 2. A signal phase adjustment circuit as recited in claim 1, wherein the reception determination unit determines that the reception status of the data signal is normal if the pre-set fixed pattern signal and the data signal transmitted from the input signal adjustment circuit agree, and the control unit selects the amount of phase modification based on the normal status of received pattern signals.
- 3. A signal phase adjustment circuit as recited in claim 1, wherein a plurality of data signals are input to the input signal adjustment circuit, and the input signal adjustment circuit further comprises an input delay circuit to delay the respective input data signals by a specified amount,
wherein the control unit detects stable phase regions of the respective input data signals having a continuous region width of a specified value or more, and wherein the control unit comprises an amount of delay modification determination device and a device to determine the amount of phase modification, wherein the amount of delay modification determination device determines a phase modification standard value as a maximum value from among minimum amounts of phase modification of continuous regions, wherein the amount of delay modification determination device establishes an amount of delay for each input data signal, such that a minimum amount of phase modification of a region, among the stable phase regions, having a continuous region width of the specified value or more agrees with the phase modification standard value, wherein the device to determine the amount of phase modification determines the optimum amount of sampling phase modification from a lower limit and an upper limit of the amount of phase modification of a location that can receive all signals normally, among the continuous regions wherein all the signals are the same, and having a continuous region width of a specified value or more.
- 4. A signal phase adjustment circuit as recited in claim 2, wherein the control unit comprises a phase modification designation unit to designate an amount of phase modification in ascending or descending order from a first value to a second value in relation to the clock phase modification circuit, and to detect a minimum amount of phase modification and a maximum amount of phase modification of the stable phase regions having a continuous region width that can receive signals normally of a specified value or more.
- 5. A signal phase adjustment circuit as recited in claim 2, wherein the reception determination unit comprises a selection circuit to select a signal from the plurality of input signals, and to determine that a reception state is normal when the selected signal agrees with a signal having a predetermined fixed pattern, and wherein the control unit detects, for each signal selected by the selection circuit, a region having a continuous region width of a specified value or more, from among the regions having an amount of phase modification that can be received normally.
- 6. A signal phase adjustment circuit as recited in claim 1, wherein instead of determining the amount of phase modification from the lower limit and upper limits of the amount of phase modification of a region, among stable phase regions, having a continuous region width of a specified value or more, rather, the amount of phase modification is determined from the lower limit and upper limit amounts of the amount of phase modification of a location that can receive all signals normally, among the continuous regions wherein all the signals are the same, and having a largest continuous region width.
- 7. A signal synchronization transmission system, comprising:
a transmission device to output specified pattern signals; a transmission route to transmit the pattern signals; and a reception device to receive signals propagated from the transmission route, wherein the transmission device transmits pre-set specified pattern signals to the transmission route, and the reception device comprises a signal phase adjustment circuit generating a fixed pattern signal which is the same as the pre-set specified pattern signals transmitted by the transmission device.
- 8. A signal synchronization transmission system as recited in claim 7, wherein the signal phase adjustment circuit comprises:
a clock phase modification circuit to modify a phase of an input clock signal and to output a phase modified clock signal; an input signal adjustment circuit to receive an input data signal and to transmit the data signal, and which operates based on the phase modified clock signal output from the clock phase modification circuit; a reception determination unit to determine a reception status of the data signal transmitted from the input signal adjustment circuit based on a pre-set fixed pattern signal and the data signal transmitted from the input signal adjustment circuit; and a control unit to control an amount of phase modification of the clock phase modification circuit based on the determination results of the reception determination unit, wherein the control unit determines an amount of phase modification from upper and lower limits of an amount of phase modification of a region, among stable phase regions, having a continuous region width of a specified value or more.
- 9. A signal synchronization transmission system as recited in claim 8, wherein a plurality of data signals are input to the input signal adjustment circuit, and the input signal adjustment circuit further comprises an input delay circuit to delay the respective input data signals by a specified amount,
wherein the control unit detects stable phase regions of the respective input data signals having a continuous region width of a specified value or more, and wherein the control unit comprises an amount of delay modification determination device and a device to determine the amount of phase modification, wherein the amount of delay modification determination device determines a phase modification standard value as a maximum value from among minimum amounts of phase modification of continuous regions, wherein the amount of delay modification determination device establishes an amount of delay for each input data signal, such that a minimum amount of phase modification of a region, among the stable phase regions, having a continuous region width of the specified value or more agrees with the phase modification standard value, wherein the device to determine the amount of phase modification determines the optimum amount of sampling phase modification from a lower limit and an upper limit of the amount of phase modification of a location that can receive all signals normally, among the continuous regions wherein all the signals are the same, and having a continuous region width of a specified value or more.
- 10. A signal synchronization transmission system as recited in claim 8, wherein the control unit comprises a phase modification designation unit to designate an amount of phase modification in ascending or descending order from a first value to a second value in relation to the clock phase modification circuit, and to detect a minimum amount of phase modification and a maximum amount of phase modification of the stable phase regions having a continuous region width that can receive signals normally of a specified value or more.
- 11. A signal synchronization transmission system as recited in claim 8, wherein the reception determination unit comprises a selection circuit to select a signal from the plurality of input signals, and to determine that a reception state is normal when the selected signal agrees with a signal having a predetermined fixed pattern, and wherein the control unit detects, for each signal selected by the selection circuit, a region having a continuous region width of a specified value or more, from among the regions having an amount of phase modification that can be received normally.
- 12. A signal synchronization transmission system as recited in claim 8,wherein instead of determining the amount of phase modification from the lower limit and upper limits of the amount of phase modification of a region, among stable phase regions, having a continuous region width of a specified value or more, rather, the amount of phase modification is determined from the lower limit and upper limit amounts of the amount of phase modification of a location that can receive all signals normally, among the continuous regions wherein all the signals are the same, and having a largest continuous region width.
- 13. A signal phase adjustment device for adjusting phase of a plurality of received signals, comprising:
a phase adjustment standard value determination device to determine a standard value for adjusting phase of the received signals; a delay modification device to adjust an amount of delay of the received signals.
- 14. A signal phase adjustment device as recited in claim 13, wherein the phase adjustment standard value determination device derives stable phase regions for each signal, the stable phase regions being regions that can receive signals normally.
- 15. A signal phase adjustment device as recited in claim 14, wherein the phase adjustment standard value determination device determines the stable phase regions for each signal by determining a minimum amount of phase modification for which normal signal reception is possible, gradually increasing the amount of phase modification to determine a maximum amount of phase modification for which normal signal reception is not possible.
- 16. A signal phase adjustment device as recited in claim 15, wherein the phase adjustment standard value determination device determines whether widths of the stable phase regions are greater than a predetermined value, and sets the phase adjustment standard value as the largest value of the minimum amounts of phase modification of the stable phase regions.
- 17. A signal phase adjustment device as recited in claim 13, wherein the delay modification device modifies the delay of respective received signals such that a minimum amount of phase modification and the standard value for adjusting phase are the same for all signals.
- 18. A signal phase adjustment device as recited in claim 14, further comprising a final phase adjustment device to set an amount of phase adjustment based on the narrowest stable phase region.
Priority Claims (1)
Number |
Date |
Country |
Kind |
11-351589 |
Dec 1999 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is is a divisional application of U.S. Ser. No. 09/732,718 filed Dec. 11, 2000, now allowed, which, in turn, is based upon and claims priority of Japanese Patent Application No. 11-351589, filed Dec. 10, 1999, the contents being incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09732718 |
Dec 2000 |
US |
Child |
10102768 |
Mar 2002 |
US |