SIGNAL PROCESSING INTEGRATED CIRCUIT, IMAGE READING DEVICE, AND IMAGE FORMING APPARATUS

Abstract

A signal processing IC that receives analog signals each corresponding to one of three colors from a color linear image sensor includes two systems of input-signal processing for each color each including at least a sample-and-hold circuit, a multiplexer circuit, a variable gain amplifier, and an A/D converter circuit. The sample-and-hold circuit samples and holds an analog signal. The multiplexer circuit multiplexes analog signals of the two systems subjected to sampling and holding into a signal of one system. The variable gain amplifier amplifies the signal output from the multiplexer circuit. The A/D converter circuit converts the amplified signal to digital data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an image signal processing IC according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of an example of a scanning optical system of an image reading device according to an embodiment of the present invention;

FIG. 3 is a block diagram of an image signal processing IC according to a second embodiment of the present invention;

FIG. 4 is a timing chart of signals in a normal operation mode of the image signal processing IC shown in FIG. 3;

FIG. 5 is a timing chart of signals in a mode in which input of each color signal of only one system is effective;

FIG. 6 is a block diagram of an image signal processing IC according to a third embodiment of the present invention;

FIG. 7 is a block diagram of an image signal processing IC according to a fourth embodiment of the present invention;

FIG. 8 is a timing chart of signals in the image signal processing IC shown in FIG. 7;

FIG. 9 is a schematic diagram of an exclusive OR circuit that generates an internal signal SAMPLE_I from a sampling start signal SAMPLE and an external input signal POL_S according to a modification of the fourth embodiment;

FIG. 10 is a schematic diagram of another exclusive OR circuit that generates an internal signal HOLD_I from a hold start signal HOLD and the external input signal POL_S;

FIG. 11 is a block diagram of an image signal processing IC according to a fifth embodiment of the present invention;

FIG. 12 is a block diagram of an image signal processing IC according to a sixth embodiment of the present invention;

FIG. 13 is a timing chart of signals representing the operation of a subtraction/integration (SUB&INTG) circuit shown in FIG. 12;

FIG. 14 is a block diagram of an image signal processing IC according to a seventh embodiment of the present invention;

FIG. 15 is a timing chart of signals in the image signal processing IC shown in FIG. 14;

FIG. 16 is a block diagram of an image signal processing IC according to an eighth embodiment of the present invention;

FIG. 17 is a timing chart of signals in the image signal processing IC shown in FIG. 16;

FIG. 18 is a block diagram of an image signal processing IC according to a ninth embodiment of the present invention;

FIG. 19 is a block diagram of an image signal processing IC according to a tenth embodiment of the present invention;

FIG. 20 is a block diagram of an image signal processing IC according to an eleventh embodiment of the present invention;

FIG. 21 is a block diagram of an image signal processing IC according to a twelfth embodiment of the present invention;

FIG. 22 is a block diagram of an image signal processing IC according to a thirteenth embodiment of the present invention;

FIG. 23 is a block diagram of an image reading device including the image signal processing IC according to any one of the embodiments;

FIG. 24 is a schematic diagram of a hardware configuration of an image forming apparatus including the image reading device shown in FIG. 23;

FIG. 25 is a block diagram of an image signal processing IC according to a conventional technology; and

FIG. 26 is a timing chart of signals in the image signal processing IC shown in FIG. 23.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Exemplary embodiments of the present invention are explained in detail below with reference to the accompanying drawings.

FIG. 2 is a schematic diagram of a scanning optical system according to an embodiment of the present invention. The scanning optical system includes a lighting optical system that is arranged below a document glass 1 and includes a light source 7. An original 2 placed on the document glass 1 is illuminated by the lighting optical system. The light reflected from the original 2 is reflected and deflected by a first mirror 3a of a moving body 3, and then, sequentially reflected and deflected by a first mirror 4a and a second mirror 4b of a second moving body 4 to an imaging lens 5. The imaging lens 5 forms a reduced image on a light-receiving surface of a CCD 6 as a color linear image sensor.

The CCD 6 includes three types of receiving units (photoelectric converting units) that have color filters passing only a red component, a green component, and blue component, respectively, of a color image formed on the light-receiving surface. The CCD 6 outputs analog image signals each corresponding to three primary colors of red, green, and blue from the light receiving units, respectively.

When an original is read, the first moving body 3 moves along a longitudinal direction of the original 2 at a speed V to a position indicated by 3′, and simultaneously, the second moving body 4 moves at a half the speed of the first moving body 3, i.e., ½ V, to a position indicated by 4′. Thus, the original 2 is read in the longitudinal direction.

On a left end portion of the document glass 1 shown in FIG. 2 is a reference white plate 8 used for generation of shading data and automatic gain adjustment. The reference white plate 8 is to be a reference of a white level of the image reading device. An output level when the reference white plate 8 is read is predetermined as “white-level target value”.

A gain of the variable gain amplifier is adjusted so that a reading level of the reference white plate 8 is to be the white-level target value. This is because as wide range as possible in a dynamic range of the A/D conversion circuit in the image signal processing IC is desired to be used.

FIG. 1 is a block diagram of an image signal processing IC 10 according to a first embodiment of the present invention.

In FIG. 2, the CCD 6 is a color linear image sensor that outputs an even-numbered pixel signal and an odd-numbered pixel signal for each of the three primary colors, red, green, and blue, i.e., analog image signals REO and ROO, GEO and GOO, and BEO and BOO.

The image signal processing IC 10 receives the analog image signals REO and ROO, GEO and GOO, and BEO and BOO, which are the image reading signals generated two each, through capacitors Cre, Cro, Cge, Cgo, Cbe, and Cbo while performing the AC coupling. The image signal processing IC 10 includes two signal processing systems for each color that include clamp circuits 12RE, 12RO, 12GE, 12GO, 12BE, and 12BO to define electric potentials of input terminals after AC coupling with respect to input signals REIN, ROIN, GEIN, GOIN, BEIN, and BOIN of respective colors input through input terminals 11RE, 11RO, 11GE, 11GO, 11BE, and 11BO, and sample-and-hold circuits 13RE, 13RO, 13GE, 13GO, 13BE, and 13BO that extract only a signal component of a specified range in output signals from the CCD 6. Such two signal processing systems are commonly used in embodiments of the present invention described below.

The image signal processing IC 10 further includes three analog multiplexer circuits 17R, 17G, and 17B that alternately select two output signals from the sample-and-hold circuits of the signal processing system for each color, and multiplex selected signals into a signal of one system per color, variable gain amplifiers 14R, 14G, and 14B that amplify the output signals of respective colors at a fixed or specified gain with respect to each system on the output side that is arranged to be one system per color, and A/D conversion circuits 15R, 15G, and 15B that convert the amplified analog image signals of respective colors to digital signals. The image signal processing IC 10 outputs digital image data DRO, DGO, and DBO that correspond respective systems per color, through output terminals 16R, 16G, and 16B, respectively.

A timing generator/interface circuit 20 controls operating timing of each circuit, similarly to the TG&IF circuit 101 shown in FIG. 25, and receives the same signals CLMPIN, SH, and MCLK as those described above.

For example, the TG&IF circuit 20 receives the sample clock SH for sampling of a signal region and generates an internal sample clock SHI, to control each of the sample-and-hold circuits 13RE, 13RO, 13GE, 13GO, 13BE, and 13BO. Thus, each of the sample-and-hold circuits samples a signal in a period in which the internal sample clock SHI is “H”, and holds during a period in which the internal sample clock SHI is “L”.

However, the three analog multiplexer circuits 17R, 17G, and 17B output the signals alternately selecting from two input signals, with only one of the AMPX control signal M1 being “H” or “L”.

Each of the variable gain amplifiers 14R, 14G, and 14B includes a register that stores therein a gain setting value set through the TG&IF circuit 20 and the data/address bus.

According to the first embodiment, all image signals can be digitalized with a single image signal processing IC for a color linear image sensor that outputs image reading signals of three colors in two systems per color. Therefore, less mounting space is required on a printed circuit board, resulting in higher design flexibility. As just described, because image signals in two systems for each of three colors are processed in the same IC, a difference in characteristics between the processing systems is small. Thus, signal processing can be performed at a low cost without causing a fixed pattern noise.

FIG. 3 is a block diagram of an image signal processing IC according to a second embodiment of the present invention. Like reference numerals refer to corresponding portions throughout the drawing, and the same explanations are not repeated. Although the image signal processing IC differs between embodiments described below, the same reference numeral 10 is hereafter used in designating it for convenience.

The CCD 6 is basically the same as previously described in the first embodiment. Further, similarly to the first embodiment, the analog image signals REO and ROO, GEO and GOO, and BEO and BOO are input to the image signal processing IC 10 while performing the AC coupling through the capacitors Cre, Cro, Cge, Cgo, Cbe, and Cbo, and two signal processing systems for each color that include the clamp circuits 12RE, 12RO, 12GE, 12GO, 12BE, and 12BO and the sample-and-hold circuits 13RE, 13RO, 13GE, 13GO, 13BE, and 13BO for the respective input signals REIN, ROIN, GEIN, GOIN, BEIN, and BOIN are provided at an input unit of the image signal processing IC 10.

The image signal processing IC 10 according to the second embodiment further includes, subsequently to the sample holed circuits 13RE, 13RO, 13GE, 13GO, 13BE, and 13BO, two systems per color of variable gain amplifiers 14RE, 14RO, 14GE, 14GO, 14BE, and 14BO, and A/D conversion circuits 15RE, 15RO, 15GE, 15GO, 15BE, and 15BO that convert the amplified analog image signals to digital signals.

In a stage subsequent thereto, the image signal processing IC 10 further includes three multiplexer circuits (MPX) 19R, 19G, and 19B. The multiplexer circuits 19R, 19G, and 19B alternately select two sets of digital image data for each color output from the A/D conversion circuits 15RE, 15RO, 15GE, 15GO, 15BE, and 15BO, and multiplex selected data to generate the digital image data DRO, DGO, and DBO of one system per color. The image signal processing IC 100 outputs the digital image data DRO, DGO, and DBO from the output terminals 16R, 16G, and 16B. In short, in this example, the variable gain amplifier and the A/D conversion circuit are provided in each system on an input side of each of the multiplexer circuits 19R, 19G, and 19B.

In the second embodiment, the image signal processing IC 10 includes an R register 18R, a G register 18G, and a B register 18B each of which stores therein a gain setting value of each color set through the TG&IF circuit 20 and the data/address bus. The variable gain amplifiers 14RE, 14RO, 14GE, 14GO, 14BE, and 14BO amplify the image signals at a gain corresponding to the gain setting value in the register of a corresponding color.

FIGS. 4 and 5 are timing charts of signals in a different operation mode according to the second embodiment. In FIGS. 4 and 5, (a) corresponds to the signals of respective colors REIN/ROIN, GEIN/GOIN, and BEIN/BOIN to be input, (b) corresponds to the sample clock SH, (c) corresponds to the reference clock MCLK, (d) corresponds to the AMPX control signals M1, and (e) corresponds to the image data DRO, DGO, and DBO to be output.

FIG. 4 depicts the case of the normal operation mode. Inputs from two systems for each color are effective, and image data from an EVEN side and image data from an ODD side are alternately output as the output signals DRO, DGO, and DBO of the multiplexer circuits 19R, 19G, and 19B, corresponding to “H” and “L” of the AMPX control signal M1.

FIG. 5 depicts the case that a mode is selected in which the image signal of only one of two systems is active for each color. That is, the input image signals REIN, GEIN, and BEIN each corresponding to one of two systems are active, and the input image signals ROIN, GOIN, and BOIN of the other system are ignored. Specifically, the AMPX control signal M1 is fixed to “H”, and only the image signals input from the EVEN side systems are output as the output signals DRO, DGO, and DBO of the multiplexer circuits 19R, 19G, and 19B of respective colors.

According to the second embodiment, the same image signal processing IC 10 can be used not only for the color linear image sensor that outputs image reading signals of three colors from two systems per color, but also for a color linear image sensor that outputs image reading signals of three colors from one system per color. Therefore, cost of the image signal processing IC can be reduced by mass production.

FIG. 6 is a block diagram of an image signal processing IC according to a third embodiment of the present invention. The image signal processing IC 10 of the third embodiment is of basically the same configuration as that of the second embodiment shown in FIG. 3. However, differently from the second embodiment, lines of a block operation control signal DIS from the TG&IF circuit 20 are connected to the sample-and-hold circuits 13RO, 13GO, and 13BO, the variable gain amplifiers 14RO, 14GO, and 14BO, and the A/D conversion circuits 15RO, 15GO, and 15BO in the systems of the input signals ROIN, GOIN, and BOIN of red, green, and blue.

When the mode in which only an image signal from one of the systems is active out of the image signals of two systems is selected, similarly to the second embodiment described above, the AMPX control signal M1 of the multiplexer circuits 19R, 19G, and 19B is fixed to “H”, and only data input from the EVEN side is output as the output image data DRO, DGO, and DBO. At the same time, the control signal DIS becomes active, and the sample-and-hold circuits 13RO, 13GO, and 13BO, the variable gain amplifiers 14RO, 14GO, and 14BO, and the A/D conversion circuits 15RO, 15GO, and 15BO being the active circuits of the system (the other system) of the input signals ROIN, GOIN, and BOIN on the ODD side to which the lines are connected are turned into a shutdown mode in which an operation current is cut off, or into a low power mode in which power consumption is lowered.

In this example, since the sample-and-hold circuits, the variable gain amplifiers, and the A/D conversion circuits are provided in two systems per color on the input side of the multiplexer circuits 19R, 19G, and 19B, the operation current of all the active circuits in the system not selected in the multiplexer circuits is cut off or reduced. However, it can be configured to cut off or reduce the operation current of some of the active circuits among the sample-and-hold circuits, the variable gain amplifiers, and the A/D conversion circuits in the system not selected.

If this arrangement is applied to the first embodiment, it can be configured to cut off or reduce the operation current of, for example, the sample-and-hold circuits 13RO, 13GO, and 13BO in the system not selected, among the sample-and-hold circuits provided two for each color on the input side of the analog multiplexer circuits 17R, 17G, and 17B.

According to the third embodiment, the active circuits not in use in the image signal processing IC 10 consumes no power or only a very low level of power. Therefore, overall power consumption can be reduced, and the temperature rise of the IC can be minimized. This improve the reliability of the IC.

FIG. 7 is a block diagram of an image signal processing IC according to a fourth embodiment of the present invention. The image signal processing IC 10 of the fourth embodiment is also of essentially the same configuration as that of the second embodiment shown in FIG. 3. However, to the TG&IF circuit 20, a sampling start signal SAMPLE and a hold start signal HOLD are input instead of the sample clock SH for sampling of a signal region.

As shown in a timing chart in FIG. 8, the TG&IF circuit 20 generates the internal sample clock SHI that becomes active at a rising edge of the sampling start signal SAMPLE and becomes inactive at a rising edge of the hold start signal HOLD, from two rectangular wave signals of the sampling start signal SAMPLE and the hold start signal HOLD externally input, to control each of the sample-and-hold circuits 13RE, 13RO, 13GE, 13GO, 13 BE, and 13BO shown in FIG. 7. Thus, each of the sample-and-hold circuits samples a signal in the period in which the internal sample clock SHI is “H”, and holds in the period in which the internal sample clock SHI is “L”.

In other words, sampling start timing and hold start timing of each of the sample-and-hold circuits are determined by the rising edge, which is one of signal edges, of the sampling start signal SAMPLE and the rising edge, which is one of signal edges, of the sample hold signal HOLD, respectively.

In the sample hold control by the sample clock SH, waveform distortion is caused by transmission paths, and an actual sample width can be changed by the waveform (rising, falling, duty, etc.). On the other hand, according to the fourth embodiment, the transmission paths of the sampling start signal and the hold start signal can be matched by using the sampling start signal SAMPLE and the hold start signal HOLD, and therefore, both of the signals can be made in the same waveform as shown in FIG. 8. Thus, the change of the sample width due to the waveforms can be suppressed.

FIGS. 9 and 10 depict an exclusive OR circuit that is used when the TG&IF circuit 20 generates the internal sample clock SHI from the sampling start signal SAMPLE and the hold start signal HOLD according to a modification of the fourth embodiment.

Exclusive OR operation is performed on the sampling start signal SAMPLE with a register bit or an external input signal POL_S to generate an internal signal SAMPLE_I as shown in FIG. 9. On the other hand, exclusive OR operation is performed on the hold start signal HOLD with a register bit or an external input signal POL_H to generate an internal signal HOLD_I as shown in FIG. 10.

The internal sample clock SHI that becomes active at a rising edge of the internal signal SAMPLE_I and becomes inactive at a rising edge of the internal signal HOLD_I is generated. Each of the sample-and-hold circuits 13RE, 13RO, 13GE, 13GO, 13BE, and 13BO shown in FIG. 7 is controlled with the internal sample clock SHI. Each of the sample-and-hold circuits samples a signal in the period in which the sample clock SHI is “H”, and holds in the period in which the sample clock SHI is “L”.

By this arrangement, the polarity of active edges (rising/falling) of the sampling start signal SAMPLE and the hold start signal HOLD can be arbitrarily selected. Therefore, radiation noise can be reduced by making both of the signals into reverse phase signals, or when waveform distortion is not a problem with a low speed clock, by supplying a sampling clock of a single signal to a terminal of the sampling start signal and a terminal of the hold start signal to set the polarity of each active edge to reverse polarity, reduction of a transmission path area and clock drivers can be achieved.

FIG. 11 is a block diagram of n image signal processing IC according to a fifth embodiment of the present invention. The image signal processing IC 10 of the fifth embodiment is also similar in configuration to that of the second embodiment shown in FIG. 3 except for the following points.

In the stage subsequent to the A/D conversion circuits 15RE, 15RO, 15GE, 15GO, 15BE, and 15BO of each signal processing system, coefficient multipliers (MULT) 21RE, 21RO, 21GE, 21GO, 21BE, and 21BO are provided. Each of the variable gain amplifiers 14RE, 14RO, 14GE, 14GO, 14BE, and 14BO has a register that stores therein a gain setting value. Each of the coefficient multipliers also has a register that stores therein a multiplication coefficient.

Each of the variable gain amplifiers 14RE, 14RO, 14GE, 14GO, 14BE, and 14BO and the coefficient multiplications 21RE, 21RO, 21GE, 21GO, 21BE, and 21BO amplifies the analog image signal of each system and multiplies image data converted to digital data by the A/D conversion circuits 15RE, 15RO, 15GE, 15GO, 15BE, and 15BO, corresponding to the gain setting value and the multiplication-coefficient setting value set for respective registers by the TG&IF circuit 20 through the data/address bus.

According to the fifth embodiment, the gain of the variable gain amplifier and the multiplication coefficient of the coefficient multiplier are not determined for each color, but can be set for each of the input signal systems. Therefore, variations in the signal levels of the respective input systems can be absorbed, thereby accurately adjusting the levels of output image data.

FIG. 12 is a block diagram of an image signal processing IC according to a sixth embodiment of the present invention. In the image signal processing IC 10 according to the sixth embodiment, an adder circuit 22 is arranged between each of the sample holed circuits 13RE, 13RO, 13GE, 13GO, 13BE, and 13BO and each of the variable gain amplifiers 14RE, 14RO, 14GE, 14GO, 14BE, and 14BO, in each of the signal processing systems in the second embodiment shown in FIG. 3.

SUB&INTG circuits 23R, 23G, and 23B are connected to the multiplexer circuits 19R, 19G, and 19B of respective colors on an output side thereof, respectively. The SUB&INTG circuits 23R, 23G, and 23B directly output, to the output terminals 16R, 16G, and 16B, the image data DRO, DGO, and DBO output by the multiplexer circuits 19R, 19G, and 19B, respectively. Digital data obtained as a result of the processing by each of the SUB&INTG circuits 23R, 23G, and 23B is converted back to an analog signal by each of digital/analog (D/A) conversion circuits (DAC) 24RE, 24RO, 24GE, 24GO, 24BE, and 24BO that converts data to an analog signal for each EVEN/ODD, and added to an output of each of the sample holed circuits 13RE, 13RO, 13GE, 13GO, 13BE, and 13BO by each of the adder circuits 22. Thus, the data is input to each of the variable gain amplifiers 14RE, 14RO, 14GE, 14GO, 14BE, and 14BO.

FIG. 13 is a timing chart of signals representing the operation of the SUB&INTG circuit 20.

Based on a trigger signal BKCLP externally input to the TG&IF circuit 20, an internal signal BKCLPI that is active only for a specified offset region BKPIX after the trigger signal BKCLP is generated. An output of the multiplexer circuit of each color in the period in which the internal signal BKCLP is active is separated into EVEN/ODD, and differences of EVEN/ODD from the specified offset level are integrated to obtain a difference sum. Then, the difference sum is averaged, and using the result of difference averaging, a setting value of the D/A conversion circuit is updated. When the DAC setting value is updated, a process such as addition to a present DAC setting value by performing an appropriate operation on the result of the difference averaging, for fluctuation of the offset level due to a noise, or optimization of a response speed.

According to the sixth embodiment, an output offset level of each color can be defined, and saturation inside the image signal processing IC can be avoided. Therefore, the operation can be stabilized, and processing in subsequent stages can be simplified, thereby reducing cost.

FIG. 14 is a block diagram of an image signal processing IC according to a seventh embodiment of the present invention. The image signal processing IC 10 of the seventh embodiment is of essentially the same configuration as that of the first embodiment shown in FIG. 1, except that latch circuits (LH) 25R, 25G, and 25B that latch the output of the A/D conversion circuits 15R, 15G, and 15B are provided for the output systems, respectively, and the image data DRO, DGO, and DBO latched by the latch circuits 25R, 25G, and 25B are output to the output terminals 16R, 16G, and 16B.

FIG. 15 is a timing chart of signals in the image signal processing IC 10 according to the seventh embodiment.

A conversion clock ADCK of the A/D conversion circuits 15R, 15G, and 15B is generated from a reference clock MCLK having the same frequency as the data rate of output image data. This clock is generated considering a delay in the variable gain amplifiers 14R, 14G, and 14B and the like in the stage preceding to the A/D conversion circuits 15R, 15G, and 15B.

Since the outputs of the A/D conversion circuits 15R, 15G, and 15B are output further delayed from the conversion clock ADCK, the outputs are greatly delayed from the input reference clock MCLK. The latch circuits 25R, 25G, and 25B that are positioned immediately before the output latch the digital image data DRO, DGO, and DBO with input reference clock MCLK. Therefore, the delay from the reference clock MCLK becomes the smallest.

According to the seventh embodiment, digital image data of each color to be output is synchronized with the reference clock. This enables to grasp the delay time and to reduce variations in the delay time. Therefore, a high speed operation is possible. In addition, a timing design in a subsequent stage is facilitated, which shortens a development period and improves the reliability.

FIG. 16 is a block diagram of an image signal processing IC according to an eighth embodiment of the present invention. The image signal processing IC 10 of the eighth embodiment is of essentially the same configuration as that of the seventh embodiment shown in FIG. 14, except that an external input terminal 26 through which digital data DEXI is input is included, and that the digital data DEXI input thereto is latched by a latch circuit 25EX in a similar manner as the image data of each color and is output through an output terminal 16E as data DEXO.

FIG. 17 is a timing chart of signals in the image signal processing IC 10 according to the eighth embodiment.

The conversion clock ADCK of the A/D conversion circuits 15R, 15G, and 15B is generated from a reference clock MCLK having the same frequency as the data rate of output image data. This clock is generated considering a delay in the variable gain amplifiers 14R, 14G, and 14B and the like in the stage preceding to the A/D conversion circuits 15R, 15G, and 15B. Since the digital image data DRO, DGO, and DBO being the outputs of the A/D conversion circuits 15R, 1SG, and 15B are output further delayed from the conversion clock ADCK, the outputs are greatly delayed from the input reference clock MCLK.

Further, because the digital data DEXI input through the external input terminal 26 is generated by an external circuit, the digital data DEXI has different delay from the delay of the output data of the A/D conversion circuits 15R, 15G, and 15B. The latch circuits 25R, 25G, 25B, and 25EX latch the digital image data DRO, DGO, and DBO, and the digital data DEXI externally input with the reference clock MCLK. Therefore, the delay from the reference clock MCLK is minimized, and timing of the digital image data DRO, DGO, and DBO, and the digital data DEXI externally input can be matched.

According to the eighth embodiment, combining with the effect of the seventh embodiment described above, definition of output timing of the digital image data of each color and the digital data externally input is facilitated.

FIG. 18 is a block diagram of an image signal processing IC according to a ninth embodiment of the present invention. The image signal processing IC 10 of the night embodiment is in a way a combination of the fourth, the fifth, and the sixth embodiments. Therefore, all the effects of these embodiments can be achieved.

Specifically, in the image signal processing IC 10, the TG&IF circuit 20 receives the sampling start signal SAMPLE and the hold start signal HOLD, and generates the internal sample clock SHI, and the variable gain amplifiers 14RE, 14RO, 14GE, 14GO, 14BE, and 14BO each having the gain setting resister and the coefficient multipliers 21RE, 21RO, 21GE, 21GO, 21BE, and 21BO each having the coefficient setting register perform the amplification and the coefficient operation.

The SUB&INTG circuits 23R, 23G, and 23B, the D/A conversion circuits 24RE, 24RO, 24GE, 24GO, 24BE, and 24BO, and the adder circuits 22 set a specified offset, and the output timing of the digital image data DRO, DGO, and DBO, and the digital data DEXI input through the external input terminal 26 is synchronized using the latch circuits 25R, 25G, and 25B and the reference clock MCLK having the same frequency as the data rate of the output image data.

FIG. 19 is a block diagram of an image signal processing IC according to a tenth embodiment of the present invention. The image signal processing IC 10 of the tenth embodiment is of essentially the same configuration as that of the ninth embodiment shown in FIG. 18, except for the following points.

In the image signal processing IC 10 shown in FIG. 19, the latch circuit positioned immediately before the output terminal 16R that outputs the image data DRO in the system of the input signal REIN/ROIN in the circuit shown in FIG. 18 is an output control latch circuit (LHOB) 28R whose output becomes “H” to be high impedance when a control signal is “L”. In parallel to this latch circuit, an output control latch circuit (LHO) 29R whose output becomes “L” to be high impedance when the control signal is “H” is connected, and an input terminal thereof is connected to an output terminal of the SUB&INTG circuit 23B in the system of the input signal BEIN/BOIN.

Further, the latch circuit positioned immediately before the output terminal 16B that outputs the image data DBO in the system of the input signal BEIN/BOIN is an output control latch circuit (LHOB) 28B. In parallel to this latch circuit, an output control latch circuit (LHO) 29B is connected, and an input terminal thereof is connected to an output terminal of the SUB&INTG circuit 23R in the system of the input signal REIN/ROIN. Control terminals of the output control latch circuits (LHOB) 28R and 28B and the output control latch circuits (LHO) 29R and 29B are connected to an external terminal RBEXG.

Therefore, when the external terminal RBEXG is set to “L”, the output of the SUB&INTG circuit 23R in the system of the input signal REIN/ROIN is output as the output image data DRO, which is the digital data, through the output control latch circuit (LHOB) 28R, and the output of the SUB&INTG circuit 23B in the system of the input signal BEIN/BOIN is output as the output data DBO through the output control latch circuit (LHOB) 28B.

When the external terminal RBEXG is set “H”, the output of the SUB&INTG circuit 23B in the system of the input signal BEIN/BOIN is output as the output image data DRO through the output control latch circuit (LHO) 29R, and the output of the SUB&INTG circuit 23R in the system of the input signal REIN/ROIN is output as the output image data DBO through the output control latch circuit (LHO) 29B.

Accordingly, by controlling the external terminal RBEXG, contents of the output image data DRO and DBO can be switched to be output.

According to the tenth embodiment, interline correction that is specific to a three-line color linear image sensor necessary because of the difference in a reading method (flat-base scanning in which a carriage is moved and a sheet through scanning in which an original is moved), in other words correction of the difference in physical positions of lines caused because the order of reading lines of red (R), green (G), and blue (B) by the color linear image sensor becomes opposite, can be performed without an external part added.

FIG. 20 is a block diagram of an image signal processing IC according to an eleventh embodiment of the present invention. The image signal processing IC 10 of the eleventh embodiment is essentially the same configuration as that of the ninth embodiment shown in FIG. 18, except for the following points.

In the image signal processing IC 10 shown in FIG. 20, subsequent to the latch circuits 25E, 25R, 25G, and 25B immediately before the output terminals 16E, 16R, 16G, and 16B shown in FIG. 18 are connected, respectively, low-voltage differential signaling (LVDS) circuits 30E, 30R, 30G, and 30B that convert input parallel data to serial data, and then to differential signals of low amplitude (low voltage). Outputs of the respective LVDS circuits 30E, 30R, 30G, and 30B are output as low-amplitude differential signals of four systems, LVEX+/LVEX−, LVR+/LVR−, LVG+/LVG−, and LVB+/LVB−, and the reference clock MCLK is also output, although not serialized, as low-amplitude differential signals LVCKG+/LVCK− through an LVDS circuit 30K.

A phase-lock loop (PLL) circuit 31 generates a serialization clock LVCK that is necessary for serialization performed by the LVDS circuits 30E, 30R, 30G, and 30B, by multiplying the reference clock MCLK by n, where “n” is the number of bits of input parallel data that is to be serialized by the LVDS circuit.

According to the eleventh embodiment, image data to be output is a serialized low-amplitude differential signal. Therefore, compared with the case where parallel image data DRO, DGO, and DBO of respective colors are output, the number of terminals required in the image signal processing IC 10 is significantly reduced, and the miniaturization of a package can be achieved.

FIG. 21 is a block diagram of an image signal processing IC according to a twelfth embodiment of the present invention. The image signal processing IC 10 of the twelfth embodiment is of essentially the same configuration as that of the eleventh embodiment shown in FIG. 20, except for the following points.

In the image signal processing IC 10 shown in FIG. 21, a common mapping circuit (MAP) 32 is connected on the output side of the latch circuits 25R, 25G, and 25B that latch the respective outputs from the SUB&INTG circuits 23R, 23G, and 23B of respective systems shown in FIG. 20, and the latch circuit 25E that latches the external digital signal DEXI input through the external input terminal 26. Six outputs of the mapping circuit 32 are connected to six LVDS circuits 30a to 30f, respectively.

The outputs of the LVDS circuits 30a to 30f are output as low-amplitude differential signals TX1A+/TX1A−, TX1B+/TX1B−, TX1C+/TX1C−, TX2A+/TX2A−, TX2B+/TX2B−, and TX2C+/TX2C−, and the reference clock MCLK is also output as low-amplitude differential signals TX1CK+/TX1CK− and TX2CK+/TX2CK− by two LVDS circuits 30g and 30h. In this example, the external digital signal DEXI is 5 bits, the parallel image data output by each of the SUB&INTG circuit 23R, 23G, and 23B of each system is 10 bits, and the input of each of the LVDS circuits 30a to 30f is 7 bits. Therefore, in this case, the PLL circuit 31 multiplies the reference clock MCLK by 7.

The mapping circuit 32 is connected to the data/address bus from the TG&IF circuit 20, and maps the input data 35 bits (5 bits+10 bits*3) to the output data 42 bits (7 bits*6), corresponding to the data/address bus.

Since the output includes information indicative of “H/L” and multiplex allocation, the number of bits of the input data and the output data differs.

According to the twelfth embodiment, more than one or arbitrary patterns of serialization can be selected or designated. Therefore, the flexibility of the configuration (receiver of the low-amplitude differential signal) in a subsequent stage increases. Accordingly, configuration required for cost reduction of an image reading device and improvement of reliability is enabled.

FIG. 22 is a block diagram of an image signal processing IC according to a thirteenth embodiment of the present invention. The image signal processing IC 10 of the thirteenth embodiment is in a way a combination of the twelfth embodiment (FIG. 21) and the tenth embodiment (FIG. 19).

Specifically, in the image signal processing IC 10 shown in FIG. 22, the latch circuit arranged immediately before the mapping circuit 32 in the system of the input signal REIN/ROIN shown in FIG. 21 is an output control latch circuit (LHOB) 28R of an active “L” whose output becomes “H” to be high impedance when a control signal is “L”. In parallel to this latch circuit, an output control latch circuit (LHO) 29R of an active “H” whose output becomes “L” to be high impedance when the control signal is “H” is connected, and an input terminal thereof is connected to the output terminal of the SUB&INTG circuit 23B in the system of the input signal BEIN/BOIN.

Further, the latch circuit arranged immediately before the mapping circuit 32 in the system of the input signal BEIN/BOIN is an output control latch circuit (LHOB) 28B of an active “L”, an output control latch circuit (LHO) 29B of an active “H” is connected in parallel thereto, and an input terminal thereof is connected to the output terminal of the SUB&INTG circuit 23R in the system of the input signal REIN/ROIN. The control terminals of the output control latch circuits (LHOB) 28R and 28B and the output control latch circuits (LHO) 29R and 29B are connected to the external terminal RBEXG.

Therefore, according to the thirteenth embodiment, by controlling the external terminal RBEXG, output signals similar to that in the twelfth embodiment (FIG. 21) can be output switching contents of the system of the input signal REIN/ROIN and the system of the input signal BEIN/BOIN.

FIG. 23 is a block diagram of an image reading device 60 that includes the image signal processing IC 10 according to the embodiments.

The image reading device 60 includes the scanning optical system shown in FIG. 2 in which the CCD 6 converts color image data of the original 2 to electrical signals of three primary colors, and the image signal processing IC 10 of any one of the embodiments that processes the signals output from the CCD 6.

The image reading device 60 further includes, as an image signal system, a shading correction circuit 61 and a digital processor 62 subsequent to the image signal processing IC 10. The shading correction circuit 61 stores data read from the reference white plate 8 in a memory as the shading correction data to correct variation in light distribution of the light source 7 shown in FIG. 2 and sensitivity of each pixel of the CCD 6 for the digital image data output from the image signal processing IC 10, and reads the correction data from the memory, when reading the original 2, to perform the shading correction. The digital processor 62 performs image processing such as scaling, γ conversion, and color conversion, and transmits the image data as a scanner output to a personal computer, a printer, or the like (not shown).

The image reading device 60 further includes a scanner control unit 63 (CPU), a driving unit 64 that drives the first moving body 3 and the second moving body 4 shown in FIG. 2, a cooling fan, and the like, a lighting circuit 65 that lights the light source 7 such as a fluorescent light and a lamp, and a sensor 66 that detects a home position of the moving bodies, temperature of the light source, and the like. The scanner control unit 63 controls the image signal system described above, and the operation and the timing of these components.

The image reading device 60 is of basically the same configuration and operates in the same manner as a conventional image reading device except for the image signal processing IC 10. Therefore, detailed explanations thereof are omitted.

With the image reading device 60 including the image signal processing IC 10, less mounting space is required on a printed board, resulting in higher design flexibility, as explained in the above embodiments. In addition, because image signals in two systems for each of three colors are processed in the same IC, a difference in characteristics between the processing systems is small. Thus, signal processing can be performed at a low cost. Accordingly, a compact and high-performance image reading device can be provided at a low price.

FIG. 24 is a schematic diagram of a hardware configuration of an image forming apparatus 70 including the image reading device 60. The image forming apparatus 70 can be realized by executing a computer program on a microcomputer. Such microcomputer includes a CPU 71 for overall control, a read only memory (ROM) 72 that stores therein an operation program of the CPU 71, a random access memory (RAM) 73 that stores therein various kinds of data concerning the operation of the apparatus and that serves as a working memory of the CPU 71, and a bus 79 that connects these components.

The image forming apparatus 70 further includes an operation-display unit 74, a reading unit 75, an image forming unit 76, a page memory 77, and a sheet feeding unit 78. These components are also connected to the CPU 71 and to each other through the bus 79.

The operation-display unit 74 includes, for example, a liquid crystal display (LCD) that displays various types of information, and an input device such as a keyboard and a touch panel through which input is provided from an operator.

The reading unit 75 corresponds to the image reading device 60. The reading unit 75 optically reads a color image of an original to output digital image data corresponding to three primary colors, and stores the image data in the page memory 77 of each color under the control of the CPU 71.

The image forming unit 76 is a plotter such as a laser printer and an ink jet printer that color-prints the image data stored in each of the page memories 77 on a recording sheet. The sheet feeding unit 78 feeds a recoding sheet to the image forming unit 76, and includes a sheet feeding tray, a feeding roller, and a conveyance mechanism.

With the image signal processing IC 10 applied to the reading unit 75, the image forming apparatus 70 can achieve various effects as noted above. Therefore, a compact high-performance image forming apparatus can be provided at a low price.

The image forming apparatus 70 can be any of digital copier, facsimile machine, and MFP that combines any or all of the functions of copier, facsimile machine, printer, scanner and the like.

As set forth hereinabove, according to an embodiment of the present invention, an image signal processing IC enables digitalization of all image signals with one image signal processing IC in a color linear image sensor that can read three colors of RGB and outputs analog image signals of two systems per color. Therefore, less mounting space is required on a printed board, resulting in higher design flexibility. Moreover, a difference in characteristics between the processing systems can be reduced, and high-performance signal processing can be achieved at a low cost.

Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art that fairly fall within the basic teaching herein set forth.

Claims

1. A signal processing integrated circuit that receives analog signals from a color linear image sensor that converts incident light to analog electrical signals each corresponding to one of three colors, the signal processing integrated circuit comprising: two systems of input-signal processing for each of the colors, each system including at least a sample-and-hold circuit that receives an analog signal of corresponding color from the color linear image sensor, and samples and holds a specified region of the analog signal;a multiplexer circuit that receives the analog signal from the sample-and-hold circuit in the two systems, and multiplexes received signals of the two systems into a signal of one system for each of the colors;a variable gain amplifier that amplifies the analog signal subjected to sampling and holding by the sample-and-hold circuit; andan analog-to-digital converter circuit that converts amplified analog signal to digital data, whereinthe variable gain amplifier and the analog-to-digital converter circuit are located on an input side or an output side of the multiplexer circuit, anddigital data of one system is output for each of the colors.

2. The signal processing integrated circuit according to claim 1, further comprising a register that stores therein a gain value set with respect to each of the colors, wherein the variable gain amplifier amplifies the analog signal by a gain factor corresponding to the gain value.

3. The signal processing integrated circuit according to claim 1, further comprising a mode-selecting unit that selects a one-system mode in which the multiplexer circuit always output a signal of only one of the two systems among the received signals.

4. The signal processing integrated circuit according to claim 3, further comprising a power control unit that cuts off or reduces power supply to at least part of the circuits in another one of the two systems when the mode-selecting unit selects the one-system mode.

5. The signal processing integrated circuit according to claim 1, further comprising a timing control unit that controls sampling start timing and hold start timing of the sample-and-hold circuit based on a sampling start signal and a hold start signal.

6. The signal processing integrated circuit according to claim 5, wherein the sampling start signal is a rectangular wave signal, and determines the sampling start timing by an active edge of the sampling start signal, andthe hold start signal is a rectangular wave signal, and determines the hold start timing by an active edge of the hold start signal, the signal processing integrated circuit further comprising:a polarity selecting unit that selects a polarity of the active edge of each of the rectangular wave signals.

7. The signal processing integrated circuit according to claim 1, wherein the variable gain amplifier and the analog-to-digital converter circuit are located on the input side of the multiplexer circuit, andthe variable gain amplifier includes a resister that stores therein a gain value set independently for each of the two systems, the signal processing integrated circuit further comprising:a coefficient multiplier that is located between the analog-to-digital converter circuit and the multiplexer circuit; anda setting unit that sets the gain value and a multiplication coefficient of the coefficient multiplier independently for each of the two systems.

8. The signal processing integrated circuit according to claim 1, further comprising: an offset specifying unit that specifies an offset region; andan offset applying unit that applies an offset to the analog signal that is input to the variable gain amplifier so that digital data output for each of the colors in the offset region has an offset value specified for the color.

9. The signal processing integrated circuit according to claim 1, further comprising a synchronization output unit that generates a clock having a frequency identical to a data rate of digital data output for each of the colors, and outputs the digital data in synchronization with the clock.

10. The signal processing integrated circuit according to claim 9, further comprising an external input terminal for externally receiving digital data, wherein the synchronization output unit outputs the digital data received through the external input terminal and the digital data of each of the colors in synchronization with the clock.

11. The signal processing integrated circuit according to claim 1, further comprising an output control unit that selectively outputs digital data of two of the three colors based on a terminal or a register determining an operation mode and a state of the terminal or the register.

12. The signal processing integrated circuit according to claim 1, further comprising a low-voltage differential signaling circuit that serializes a plurality of bits of digital data of each of the colors into serial signals, and converts the serial signals to low-amplitude differential signals to output serial low-amplitude differential signals for each of the colors.

13. The signal processing integrated circuit according to claim 12, further comprising a pattern selecting unit that selects a serialization pattern of patterns of serialization performed by the low-voltage differential signaling circuit.

14. An image reading device comprising: a color linear image sensor that optically reads image data, converts the image data to analog electrical signals each corresponding to one of three colors, and outputs the analog signals; anda signal processing integrated circuit that receives the analog signals output from the color linear image sensor, the signal processing integrated circuit including two systems of input-signal processing for each of the colors, each system including at least a sample-and-hold circuit that receives an analog signal of corresponding color from the color linear image sensor, and samples and holds a specified region of the analog signal;a multiplexer circuit that receives the analog signal from the sample-and-hold circuit in the two systems, and multiplexes received signals of the two systems into a signal of one system for each of the colors;a variable gain amplifier that amplifies the analog signal subjected to sampling and holding by the sample-and-hold circuit; andan analog-to-digital converter circuit that converts amplified analog signal to digital data, whereinthe variable gain amplifier and the analog-to-digital converter circuit are located on an input side or an output side of the multiplexer circuit, anddigital data of one system is output for each of the colors.

15. An image forming apparatus comprising: an image reading device including a color linear image sensor that optically reads image data, converts the image data to analog electrical signals each corresponding to one of three colors, and outputs the analog signals, and a signal processing integrated circuit that receives the analog signals output from the color linear image sensor, the signal processing integrated circuit including two systems of input-signal processing for each of the colors, each system including at least a sample-and-hold circuit that receives an analog signal of corresponding color from the color linear image sensor, and samples and holds a specified region of the analog signal;a multiplexer circuit that receives the analog signal from the sample-and-hold circuit in the two systems, and multiplexes received signals of the two systems into a signal of one system for each of the colors;a variable gain amplifier that amplifies the analog signal subjected to sampling and holding by the sample-and-hold circuit; andan analog-to-digital converter circuit that converts amplified analog signal to digital data such that the digital data of one system is output for each of the colors; andan image forming unit that forms an image on a recording medium based on the digital data output from the image reading unit, whereinthe variable gain amplifier and the analog-to-digital converter circuit are located on an input side or an output side of the multiplexer circuit.