Patent Grant
11894428
The present application is based on PCT filing PCT/JP2019/011112, filed Mar. 18, 2019, the entire contents of which is incorporated herein by reference.
The present invention relates to a silicon carbide semiconductor device and in particular to a silicon carbide semiconductor device that includes trench gates.
A configuration is known in which a unipolar semiconductor device such as a metal oxide semiconductor field effect transistor (MOSFET) for use as a power switching element includes a Schottky barrier diode (SBD) serving as a unipolar freewheeling diode.
This configuration is achieved by arranging, in parallel, MOSFET cells including gate electrodes and SBD cells including Schottky electrodes. As one example of general configurations, there is a configuration in which a Schottky electrode is provided in a predetermined region of a semiconductor chip, and this region is caused to operate as a Schottky barrier diode.
This configuration can reduce costs as compared to the case of using individual diodes externally mounted on a semiconductor chip. Besides, the fact that the inclusion of Schottky barrier diodes suppresses bipolar operation of parasitic pn diodes becomes a merit of an MOSFET that uses silicon carbide as a base material. This is because a silicon carbide semiconductor device may suffer a phenomenon of extended crystal defects resulting from the recombination energy of carriers generated by bipolar operation of parasitic pn diodes, and accordingly may impair its reliability as a switching element.
In the case where a trench-gate MOSFET includes Schottky barrier diodes, a configuration is conceivable in which some gate electrodes are replaced by Schottky electrodes and connected to source electrodes as disclosed in, for example, Patent Document 1. This configuration keeps the distances between the trenches small and accordingly makes it possible to obtain high Schottky current from built-in SBD regions while maintaining low electric fields at the bottoms of the trenches.
In a semiconductor device such as a trench-gate MOSFET that include gate electrodes inside trenches, channels are formed in the side walls of the trenches. This configuration has the merit of being able to improve the density of channel widths and reduce ON-state resistance as compared to those of a planar MOSFET that has gate electrodes formed on the device surface. There is, however, a problem in that the concentration of electric fields occurs at the bottoms of the trenches when a high voltage is applied in the OFF state of the semiconductor device. In particular, in a trench-gate silicon carbide semiconductor device, SiC has high breakdown strength and therefore the breakdown of a gate insulating film due to the concentration of electric fields at the bottoms of the trenches tends to occur prior to the occurrence of avalanche breakdown in a drift layer. Thus, the concentration of electric fields at the bottoms of the trenches is liable to be a problem.
In order to moderate the concentration of electric fields at the bottoms of the trenches, it has been proposed to provide a protective layer having a different conductive type from that of the drift layer in the trenches. For example, as disclosed in Patent Document 2, the concentration of electric fields at the bottoms of the trenches can be moderated by providing a trench-bottom protective layer on the drift layer provided in lower portions of the trenches. Note that the effect of moderating electric fields diminishes as the intervals between the trenches or the distances between the protective layers increase, and in this case, the intensity of electric fields applied to the bottoms of the protective layers and the gate insulating film at the bottoms of the trenches increases. This results in deterioration in reliability and withstand voltage of the gate insulating film. Accordingly, it generally becomes important to keep the distances between trenches small in a trench-gate silicon carbide semiconductor device.
In the case where an SBD region is formed between MOSFET regions as in the trench-gate MOSFETs disclosed in Patent Documents 1 and 2, SBD current flows between trench gates. At this time, if the intervals between the trench gates are designed to be as narrow as possible in order to moderate electric fields, the current path may become narrow and may not allow a sufficient amount of unipolar current to flow therethrough. Therefore, it may become difficult to obtain a sufficient effect of suppressing bipolar operation of parasitic pn diodes.
In view of this, it is conceivable to increase unipolar current flowing through SBDs and an MOSFET by increasing impurity concentrations in regions between trenches. This, however, increases in return an electric field at a gate oxide film in gate trenches and SiC electric fields at the interfaces between the SBDs and the SiC regions, and may become a cause of increasing leakage current in the OFF state of the MOSFET or deteriorating long-term reliability of the MOSFET.
The electric field applied to the gate oxide film can be moderated by increasing the thickness of the gate oxide film, although there is a tradeoff relationship between the ON-state resistance and leakage current of the MOSFET. On the other hand, it is difficult to moderate the SiC electric fields at the interfaces between the SBDs and the SiC regions because the SiC electric fields cannot be controlled by control of film thickness or other parameters. When the MOSFET is OFF state, highest electric fields are detected in the vicinity of the interfaces between the SBDs and the SiC regions, except at pn junctions. This becomes a factor of failure in withstand voltage.
The present invention has been made in order to solve the problems as described above, and it is an object of the present invention to provide a silicon carbide semiconductor device capable of improving a trade-off between the ON-state resistance and leakage current of an MOSFET and suppressing bipolar operation by increasing unipolar current flowing through SBDs.
A silicon carbide semiconductor device according to the present invention is a silicon carbide semiconductor device that includes a Schottky barrier diode in a field-effect transistor. The silicon carbide semiconductor device includes semiconductor layer of a first conductivity type, a first semiconductor region of the first conductivity type provided in an upper layer portion of the semiconductor layer, a second semiconductor region of a second conductivity type provided in contact with a bottom face of the first semiconductor region, a first trench provided through the first semiconductor region and the second semiconductor region in a thickness direction and having a bottom face that reaches inside the semiconductor layer, a gate electrode embedded in the first trench via a gate insulating film that covers an inner face of the first trench, an interlayer insulation film having a contact portion above the first semiconductor region, a first low-resistance layer of the first conductivity type provided in the semiconductor layer to have contact with at least one trench side wall of the first trench in a direction perpendicular to a direction of extension of the first trench, a second trench provided through the second semiconductor region in the thickness direction and having a bottom face that reaches inside the semiconductor layer, a Schottky barrier diode electrode embedded in the second trench, a second low-resistance layer of the first conductivity type provided in the semiconductor layer to have contact with at least one trench side wall of the second trench in a direction perpendicular to a direction perpendicular to a direction parallel to a direction of extension of the second trench, a first main electrode embedded in the contact portion and covering the interlayer insulation film, and a second main electrode provided on a main surface of the semiconductor layer on a side opposite to a side on which the first main electrode is provided. The second low-resistance layer has an impurity concentration higher than an impurity concentration in the semiconductor layer and lower than an impurity concentration in the first low-resistance layer.
The silicon carbide semiconductor device according to the present invention is capable of suppressing the ON-state resistance of a field-effect transistor as well as leakage current flowing therethrough and improving the density of unipolar current flowing through built-in Schottky barrier diodes.
In the following description, terms that may be used to mean specific positions and directions, such as “upper,” “lower,” “side,” “bottom,” “front,” and “back,” are merely used for convenience's sake in order to facilitate understanding of the content of embodiments, and do not relate to actual positions and directions during implementation.
In the following description, the conductivity type of impurities is generally defined such that an n-type is a first conductivity type, and a p-type is a second conductivity type, but this definition may be reversed.
As illustrated in
There is also a gate trench 6 (first trench) that extends from the outermost surface of the source region 3 through the source region 3 and the body region 5 to inside the drift layer 2 in a thickness direction. The drift layer 2 is a semiconductor layer formed by epitaxial growth of the SiC substrate 1 and having a lower impurity concentration of the first conductivity type than the SiC substrate 1.
On the inner surface (bottom and side faces) of the gate trench 6, a gate insulating film 7 is provided, and a gate electrode 8 is embedded in the gate trench 6 surrounded by the gate insulating film 7. Then, a low-resistance layer 16 (first low-resistance layer) of the first conductivity type is provided in contact with the side face of the gate trench 6. One end of the low-resistance layer 16 in a depth direction (Y direction) is in contact with the lower face of the body region 5, and the other end thereof is located at a depth of the same order as or slightly deeper than the bottom face of the gate trench 6.
An interlayer insulation film 12 is provided so as to cover the gate trench 6 and the vicinity thereof, and a source contact electrode 4 is provided on the source region 3 that is outside the interlayer insulation film 12. Also, a source electrode 9 (first main electrode) is connected to the source contact electrode 4. The source contact electrode 4 is composed of silicide of a metal such as nickel (Ni) or titanium (Ti) and silicon of the source region 3 and has an ohmic contact with the source region 3.
Moreover, a drain electrode 11 (second main electrode) is provided on the other main surface (second main surface) of the SiC substrate 1 on the side opposite to the source electrode 9.
The trench-gate MOSFET is configured as described above, and a region in which the trench-gate MOSFET (field-effect transistor) is formed is referred to as an MOSFET region 19.
Although not shown in
An SBD region 20 is formed adjacent to the MOSFET region 19. In the SBD region 20, an SBD trench 25 (second trench) that extends from the outermost surface of the source region 3 through the source region 3 and the body region 5 to inside the drift layer 2 in the thickness direction is provided, and instead of the gate insulating film 7 and the gate electrode 8, a Schottky electrode 10 (Schottky barrier diode electrode) is embedded in the SBD trench 25.
The source electrode 9 is in contact with the SBD trench 25 and the source region 3 that is in the vicinity of the SBD trench 25. Then, a low-resistance layer 17 (second low-resistance layer) of the first conductivity type is provided in contact with the side face of the SBD trench 25. Note that the low-resistance layer 17 has a lower impurity concentration of the first conductivity type than the low-resistance layer 16. The low-resistance layer 17 is provided such that its one end in the depth direction (Y direction) is in contact with the lower face of the body region 5 and its other end is located at a depth of the same order as or slightly deeper than the depth of the bottom face of the SBD trench 25.
In plan view, a plurality of gate trenches 6 and a plurality of SBD trenches 25 are alternately arranged, for example in strips, on the SiC substrate 1. Note that the gate electrodes 8 embedded in the gate trenches 6 are connected to gate lines not shown.
Next, the impurity concentrations of each semiconductor layer and each impurity region will be described. The impurity concentration of the first conductivity type in the drift layer 2 is higher than or equal to 1.0×1014 cm−3 and lower than or equal to 1.0×1017 cm−3 and is set based on the withstand voltage or other factors of the silicon carbide semiconductor device. The body region 5 is assumed to have an impurity concentration of the second conductivity type higher than or equal to 1.0×1014 cm−3 and lower than or equal to 1.0×1018 cm−3. The source region 3 has an impurity concentration of the first conductivity type higher than or equal to 1.0×1018 cm−3 and lower than or equal to 1.0×1021 cm−3. Although not shown in
The impurity concentration of the first conductivity type in the low-resistance layer 16 is higher than that in the drift layer 2 and is set to be, for example, higher than or equal to 1.0×1016 cm−1 and lower than or equal to 1.0×1019 cm−3. On the other hand, the impurity concentration of the first conductivity type in the low-resistance layer 17 is set to be higher than that in the drift layer 2 and lower than that in the low-resistance layer 16 and is set in the range, for example, higher than 1.0×1016 cm-3 and lower than 1.0×1019 cm−3. More practically, the difference in impurity concentration between the low-resistance layer 16 and the low-resistance layer 17 is set to fall within an order of magnitude. For example, when the drift layer 2 has an impurity concentration of the first conductivity type higher than or equal to 1.0×1015 cm−3 and lower than or equal to 1.0×1016 cm−3, the impurity concentration of the low-resistance layer 17 may be set to be higher than or equal to 2.0×1016 cm−3 and lower than or equal to 1.0×1017 cm−3, and the impurity concentration of the low-resistance layer 16 may be set to be higher than or equal to 4.0×1016 cm−3 and lower than or equal to 1.0×1018 cm−3.
Next, operations of the silicon carbide semiconductor device 100 will be described briefly. Referring to
When a voltage less than the threshold voltage is applied to the gate electrode 8, no channel is formed in the body region 5, and therefore such a current path as described in the case of ON state is not formed. Thus, even if a voltage is applied between the drain electrode 11 and the source electrode 9, almost no current flows from the drain electrode 11 to the source electrode 9. When the voltage at the gate electrode 8 is less than the threshold voltage as described above, the silicon carbide semiconductor device 100 is in the OFF state. In this way, the silicon carbide semiconductor device 100 operates by switching between the ON and OFF states by control of the voltage applied to the gate electrode 8.
Meanwhile, when a forward voltage is applied to the Schottky barrier diode in the SBD region 20 in the OFF state of the silicon carbide semiconductor device 100, unipolar current starts to flow between the Schottky electrode 10 and the drain electrode 11. At this time, the unipolar current increases for a while with an increase in the forward voltage, but when a difference in potential between the source electrode 9 and the drain electrode 11 has reached a given value, bipolar current resulting from a pn junction between the body region 5 and the drift layer 2 starts to flow between the body region 5 and the drain electrode 11. The unipolar current that can flow immediately before the bipolar current starts to flow is referred to as maximum unipolar current. The magnitude of the maximum unipolar current is affected by the pn junction between the body region 5 and the drift layer 2 and the potential difference occurring in the drift layer 2.
For example, when the low-resistance layer 17 is set to have a low impurity concentration of the first conductivity type, the resistance between the SBD trench 25 and the gate trench 6 increases and consequently bipolar current flows without a large flow of unipolar current. As a result, the effect of suppressing bipolar current may not be obtained enough even in the case where the MOSFET includes SBDs. In view of this, if the low-resistance layer 17 is set to have a high impurity concentration of the first conductivity type, leakage current may increase as a result of the electric field in the low-resistance layer 17 in the vicinity of the SBD trench 25 being increased by the application of a high drain voltage in the OFF state.
The same applies to the MOSFET region 19, and when the low-resistance layer 16 is set to have a low impurity concentration, the ON-state resistance of the MOSFET will increase. Conversely, when the low-resistance layer 16 is set to have a high impurity concentration, the reliability of the gate insulating film 7 may be lowered as a result of an increase in the electric field applied to the corners of the bottom of the gate trench 6.
In the case of the MOSFET region 19, a local increase in the electric field at the corners of the bottom of the gate trench 6 can be moderated to some extent by increasing the thickness of the gate insulating film 7. However, the same technique cannot be used for the SBD region 20 due to the absence of an oxide film. That is, it can be said that suppressing leakage current in the SBD region 20 in the OFF state is more difficult than in the MOSFET region 19.
In contrast, in Embodiment 1 according to the present invention, the impurity concentration of the first conductivity type in the low-resistance layer 17 formed adjacent to the SBD trench 25 is set to be independent of and smaller than that in the low-resistance layer 16 formed adjacent to the gate trench 6. This enables reducing leakage current in the SBD region 20 while reducing the ON-state resistance of the MOSFET region 19. Moreover, although the electric field that is applied to the gate insulating film 7 of the MOSFET can be controlled by changing the thickness of the gate insulating film 7 as described previously, the electric field that is applied to the vicinity of the SBD is determined mainly by the impurity concentration in the vicinity of the SBD region 20. Accordingly, the electric field that is applied to the vicinity of the SBD can be adjusted by setting the impurity concentration of the first conductivity type in the low-resistance layer 17 and the impurity concentration of the first conductivity type in the drift layer 2 to the aforementioned values.
A method of manufacturing the silicon carbide semiconductor device 100 will be described hereinafter with reference to
First, in the step illustrated in
Then, the source region 3 and the body region 5 are each formed by ion implantation in the upper layer portion of the drift layer 2 as illustrated in
The order in which each region is formed may be inverted, and all or some of the regions may be formed by epitaxial growth, instead of ion implantation. Although not shown, a well contact region having a higher impurity concentration of the second conductivity type than the body region 5 may be formed in the vicinity of the surface of the body region 5 by techniques such as selective ion implantation using a mask.
Next, in the step illustrated in
Next, in the step illustrated in
In the case illustrated in
Then, after the mask 32 is removed, in the step illustrated in
In the case illustrated in
Thereafter, heat treatment is conducted in order to electrically activate impurities implanted in the drift layer 2. This heat treatment is desirably conducted in an inert gas atmosphere such as an argon (Ar) or nitrogen (N) atmosphere or in vacuum at a temperature higher than or equal to 1500° C. and lower than or equal to 2200° C. for a period of time longer than or equal to 0.5 minutes and shorter than or equal to 60 minutes. Alternatively, this heat treatment may be conducted while the surface of the drift layer 2 is covered with a film composed of carbon. This covering prevents the surface of the drift layer 2 from becoming rough due to etching caused by reactions of residual moisture and residual oxygen in heat treatment equipment during the heat treatment.
Next, in the step illustrated in
Next, in the step illustrated in
Thereafter, the source contact electrode 4 is formed in contact with the source region 3 and the well contact region (not shown) that are exposed at the bottom of the opening. A method of forming the source contact electrode 4 involves depositing a metal film composed primarily of Ni on the entire surface of the source region 3 including the inside of the opening that becomes a source contact portion, forming a silicide film that becomes the source contact electrode 4 by causing reactions of the metal film and silicon carbide through heat treatment conducted at a temperature higher than or equal to 600° C. and lower than or equal to 1100° C., and thereafter removing an unreacted portion of the metal film that remains on the interlayer insulation film 12 by wet etching using nitric acid, sulfuric acid, or hydrochloric acid or using a liquid mixture of any of these acids and a hydrogen peroxide solution. Note that another heat treatment may be conducted after the removal of the metal film remaining on the interlayer insulation film 12. In this case, the latter heat treatment is conducted at a higher temperature than the temperature of the former heat treatment in order to establish an ohmic contact with lower contact resistance.
Next, in the step illustrated in
Thereafter, the Schottky electrode 10 is formed by embedding components such as Ti, molybdenum (Mo), and Ni in the SBD trench 25 by sputtering or other techniques. Then, the source electrode 9 is formed in contact with the Schottky electrode 10, the surface of the source region 3, and the surface of the source contact electrode 4, and the drain electrode 11 is formed on the rear surface of the SiC substrate 1. This forms the silicon carbide semiconductor device 100 illustrated in
Alternatively, the steps after the step described with reference to
The silicon carbide semiconductor device 100 according to Embodiment 1 of the present invention achieves advantageous effects as follows. In
In the example shown in
With this configuration, if the low-resistance layer 16 and the low-resistance layer 17 are made to have the same impurity concentrations as those in the silicon carbide semiconductor device 100, the effect of reducing the ON-state resistance of the MOSFET and the effect of improving the flow of unipolar current in SBDs will diminish as compared with those achieved by the silicon carbide semiconductor device 100, but instead it is possible to moderate electric fields applied to the bottoms and corners of the gate trench 6 and the SBD trench 25. As a result, the effect of improving the reliability of the oxide film and the effect of reducing leakage current in SBDs are achieved.
Conversely, the low-resistance layer 16 may be formed only to a position shallower than the bottom of the gate trench 6, and the low-resistance layer 17 may be formed to a position deeper than the bottom of the SBD trench 25. With this configuration, it is possible to achieve the effect of improving the reliability of the oxide film and the effect of improving the flow of unipolar current in SBDs.
This configuration facilitates current diffusion in the planar direction (X direction) and achieves the effect of reducing the ON-state resistance because the current flowing through the MOSFET region 19 flows to the low-resistance layer 16 that is in contact with the bottom of the gate trench 6.
Although the example of forming the low-resistance layer 16 that is also in contact with the bottom of the gate trench 6 is shown in
This configuration facilitates current diffusion in the planar direction (X direction) and improves the effect of suppressing bipolar current because the unipolar current flowing through the SBD region 20 flows to the low-resistance layer 17 that is in contact with the bottom of the SBD trench 25.
Alternatively, a configuration is also possible in which the low-resistance layer 16 is formed also in contact with the bottom of the gate trench 6 and the low-resistance layer 17 is formed also in contact with the bottom of the SBD trench 25. With this configuration, it is possible to reduce the ON-state resistance in the MOSFET region 19 and to improve the effect of suppressing bipolar current in the SBD region 20.
With this configuration, it is possible to achieve the effect of moderating electric fields applied to the vicinity of the bottoms of the gate trench 6 and the SBD trench 25. Alternatively, the protective layer 13 may be formed on only either of the gate trench 6 and the SBD trench 25.
The protective layer 13 may be formed by ion implantation and may have an impurity concentration of the second conductivity type higher than or equal to 1×1014 and lower than or equal to 1×1020 cm−3.
The connection layers 14 may be formed by ion implantation and may have an impurity concentration of the second conductivity type higher than or equal to 1×1014 and lower than or equal to 1×1020 cm−3.
Alternatively, part of the low-resistance layer 16 and part of the low-resistance layer 17 may be replaced by the connection layers 14, instead of replacing the low-resistance layer 16 and the low-resistance layer 17 in their entirety.
This configuration allows the protective layer 13 to be electrically connected to the body region 5 via the connection layers 14 and thus enables discharging the protective layer 13 or recharging the protective layer 13 via the source region 3 or the well contact region (not shown) at turn-on or turn-off. Accordingly, the path length of charge carriers is shortened, and an increase in potential is suppressed. As a result, the reliability of the gate insulating film 7 is improved.
With this configuration, each of the connection layers 14 serves as a high-resistance layer in the MOSFET region 19 and the SBD region 20 on the sides on which the connection layers 14 are formed, and accordingly the MOSFET current and the SBD current decrease. However, in the MOSFET region 19 and the SBD region 20 on the sides on which the connection layers 14 are not formed, the MOSFET current and the SBD current do not decrease.
In
The silicon carbide semiconductor device 200 illustrated in
When the low-resistance layer 17 and the low-resistance layer 18 are formed by ion implantation, one example of the methods is forming the low-resistance layer 18 by implanting ions in a slanting direction with a high implantation energy and then forming the low-resistance layer 17 by implanting ions in a slanting direction with a lower implantation energy so as to form a retrograde profile. This forms a configuration in which the impurity concentration in the vicinity of the SBD trench 25 is low, and the impurity concentration in a region slightly away from the SBD trench 25 is high.
This configuration facilitates lateral diffusion of unipolar current flowing through SBDs and improves the effect of suppressing a flow of bipolar current. Besides, it is possible to minimum leakage current at turn-off of the MOSFET because the impurity concentration in the vicinity of the SBD trench 25 is low.
Although the example in which the low-resistance layer 18 is provided on the SBD trench 25 is shown in
The silicon carbide semiconductor device 300 illustrated in
This configuration facilitates lateral diffusion of the MOSFET current and the SBD unipolar current and improves the effect of reducing the ON-state resistance and the effect of suppressing a flow of bipolar current. Note that the low-resistance layer 16 and the low-resistance layer 17 are formed by implanting ions in a slanting direction at a constant inclination angle as in Embodiments 1 and 2.
The silicon carbide semiconductor device 400 illustrated in
The low-resistance layer 17 is formed by techniques such as ion implantation before the gate trenches 6 are formed by etching or other methods. In this case as well, an SBD region 20 including the SBD electrode 10 is formed between MOSFET regions 19 each including the gate trench 6, and like the MOSFET regions 19, the SBD region 20 is a region in strip form.
In the SBD regions 20, the source region 3 is not provided, and the body region 5 is provided to sandwich the low-resistance 17 in the upper layer portion of the drift layer 2. The low-resistance layer 17 is formed to a position deeper than the body region 5 and shallower than the gate trenches 6 and is also in contact with the side faces of the gate trenches 6. The low-resistance layer 16 is provided such that its one end in the depth direction (Y direction) is in contact with the lower face of the body region 5, and its other end is at a depth of the same order as or slightly deeper than the depth of the bottoms of the gate trenches 6. Although the low-resistance layer 17 is provided so as to extend between the low-resistance layers 16, the low-resistance layer 17 is formed to a depth shallower than the depth of the low-resistance layer 16.
The silicon carbide semiconductor device 400 according to Embodiment 4 of the present invention moderates the electric field applied to the vicinity of the SBD electrode at OFF state of the MOSFET because the SBD electrode 10 is formed on the surface of the drift layer 2.
Moreover, the presence of the low-resistance layer 17 formed deeper than the body region 5 facilitates current diffusion in the planar direction (X direction) in the drift layer 2 in the vicinity of the bottom of the body region 5 and improves the effect of suppressing a flow of bipolar current.
When the low-resistance layer 16 is not formed in the SBD region 20, it is possible to reduce the electric field applied to the vicinity of the SBD electrode 10 and to reduce leakage current. This is because a depletion layer can easily expand from the body region 5 toward the drift layer 2.
The present embodiment applies the silicon carbide semiconductor device according to any one of the Embodiments 1 to 4 described above to a power converter. The silicon carbide semiconductor devices according to Embodiments 1 to 4 are not limited to be used as specific power converters, but the following description is given of a case as Embodiment 5 in which any of these devices is applied to a three-phase inverter.
The power conversion system illustrated in
The power converter 2000 is a three-phase inverter connected between the power source 1000 and the load 3000. The power converter 2000 converts direct-current power supplied from the power source 1000 into alternating-current power and supplies the alternating-current power to the load 3000. As illustrated in
The load 300 is a three-phase electric motor driven by the alternating-current power supplied from the power converter 2000. The load 3000 is not for specific purpose of use but is an electric motor that is mounted on various electrical devices. Thus, it is used as an electric motor for a hybrid automobile, an electric automobile, a railway vehicle, or an air conditioner.
The power converter 2000 will be described hereinafter in detail. The main converter circuit 201 includes switching elements and free-wheeling diodes (not shown) and converts direct-current power supplied from the power supply 1000 into alternating-current power and supplies the alternating-current power to the load 3000 by switching the switching elements. Although the main converter circuit 201 may come in various types of specific circuit configurations, the main converter circuit 201 according to the present embodiment is a two-level three-phase full-bridge circuit that include six switching elements and six free-wheeling diodes connected respectively in inverse-parallel to the six switching elements. The silicon carbide semiconductor device according to any one of Embodiments 1 to 4 and variations described above is applied to each switching element in the main converter circuit 201. Each two of the six switching elements are connected in series and constitute upper and lower arms, and each pair of upper and lower arms constitutes each phase (U phase, V phase, or W phase) of the full-bridge circuit. An output terminal for each pair of upper and lower arms (i.e., three output terminals of the main converter circuit 201) is connected to the load 3000.
The driving circuit 202 generates a driving signal for driving each switching element in the main converter circuit 201 and supplies the driving signal to the control electrode of the switching element in the main converter circuit 201. Specifically, in accordance with a control signal received from the control circuit 203 described later, the driving circuit outputs a driving signal for turning on each switching element or a driving signal for turning off each switching element to the control electrode of the switching element. In the case of maintaining a switching element in the ON state, the driving signal is a voltage signal (ON-state signal) higher than or equal to a threshold value of the switching element, and in the case of maintaining a switching element in the OFF state, the driving signal is a voltage signal (OFF-state signal) less than a threshold value of the switching element.
The control circuit 203 controls each switching element in the main converter circuit 201 so that desired power is supplied to the load 3000. Specifically, on the basis of the power to be supplied to the load 3000, the control circuit 203 calculates a time (turn-on time) when each switching element in the main converter circuit 201 is to be turned on. For example, the control circuit may control the main converter circuit 201 by PWM control in which the turn-on time of each switching element is modulated in accordance with the voltage to be output. Then, the control circuit outputs a control command (control signal) to the driving circuit 202 so that, at each time, an ON-state signal is output to a switching element that is to be turned on and an OFF-state signal is output to a switching element that is to be turned off. In accordance with this control signal, the driving circuit 202 outputs either an ON-state signal or an OFF-state signal as a driving signal to the control electrode of each switching element.
In the power converter according to the present embodiment, the silicon carbide semiconductor device according to any of Embodiments 1 to 4 is applied as each switching element in the main converter circuit 201. Accordingly, it is possible to achieve a power converter with low loss and high reliability in high-speed switching.
Although the present embodiment has described an example of applying the silicon carbide semiconductor device according to any of Embodiments 1 to 4 to the two-level three-phase inverter, the present invention is not intended to be limited to this example, and the silicon carbide semiconductor device is applicable to various types of power converters. Although the two-level power converter has been described in the present embodiment, the silicon carbide semiconductor device may be applied to a three-level or multilevel power converter, or may be applied to a single-phase inverter when power is supplied to a single-phase load. The present invention is also applicable to a DC/DC or AC/DC converter when power is supplied to a direct-current load or the like.
The power converter that applies the silicon carbide semiconductor device according to any of Embodiments 1 to 4 is not limited for use in the case where the load described above is an electric motor. It may be used in, for example, a power supply unit for an electric discharge machine, a laser beam machine, an induction heating cooking appliance, or a non-contact power supply system, or may also be used in a power conditioner such as a photovoltaic power generating system or a power condenser system.
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore to be understood that numerous modifications and variations can be devised without departing from the scope of the invention.
According to the present invention, the above embodiments can be arbitrarily combined, or each embodiment can be appropriately varied or omitted within the scope of the invention.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2019/011112 | 3/18/2019 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2020/188686 | 9/24/2020 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 11271084 | Fukui | Mar 2022 | B2 |
| 20090283776 | Iwamuro | Nov 2009 | A1 |
| 20220037474 | Tanaka | Feb 2022 | A1 |
| 20230215942 | Tanaka | Jul 2023 | A1 |
| 20230290874 | Yoshida | Sep 2023 | A1 |
| Number | Date | Country |
|---|---|---|
| 2006-210392 | Aug 2006 | JP |
| 2009-278067 | Nov 2009 | JP |
| Entry |
|---|
| International Search Report and Written Opinion dated May 11, 2019, received for PCT Application PCT/JP2019/011112, Filed on Mar. 18, 2019, 6 pages including English Translation. |
| Number | Date | Country | |
|---|---|---|---|
| 20220102503 A1 | Mar 2022 | US |
