Patent Grant
7005678
This application is based on Japanese Patent Application No. 2003-385092 filed on Nov. 14, 2003, the disclosure of which is incorporated herein by reference.
The present invention relates to a silicon carbide semiconductor device having a junction field effect transistor and a method for manufacturing the same.
A semiconductor device in a prior art includes a cell portion, in which a semiconductor device such as a MOSFET (i.e., metal-oxide semiconductor field effect transistor) is formed. The cell portion of the device is disposed at the center of the device so that electric field concentration is dispersed by an outer periphery of the device. Thus, the withstand voltage of the device is increased. In the prior art, a floating field ring as a guard ring is used for the outer periphery of the device to relax the electric field concentration. The guard ring is composed of the end portion of the outer periphery of the device. The guard ring is formed in such a manner that an impurity is implanted from the surface of a semiconductor substrate of the device by an ion implantation method. Then, the implanted impurity is activated by a thermal diffusion method. This method for forming the guard ring is preferably used for a silicon based semiconductor device.
However, it is difficult to increase the withstand voltage of the silicon based semiconductor device. Therefore, a silicon carbide based semiconductor device has been studied to increase the withstand voltage of the device. The silicon carbide crystal has a wide band gap wider than the silicon crystal, a high melting point higher than the silicon crystal, a low dielectric constant, a high breakdown withstand voltage, a high thermal conductivity coefficient, and a high electron mobility. Therefore, it is considered that the performance of the silicon carbide based semiconductor device is higher than the silicon based semiconductor device.
In the prior art, a silicon carbide semiconductor device is disclosed, for example, in U.S. Pat. No. 5,233,215. The device is shown in
In the above device, electric field generated from the N− conductive type drift layer J1 is concentrated at the oxide film J6 disposed in the trench J5. Since the withstand voltage of the oxide film J6 is lower than the silicon carbide crystal, the withstand voltage of the device is defined by the oxide film J6 so that the withstand voltage of the device is decreased.
Further, after the trenches J5, J8 are formed, an oxide film forming process and a metal film forming process are necessitated. Furthermore, the deep trench forming process for forming the deep trench J8 at the utmost outer periphery is necessitated. Therefore, a manufacturing method for manufacturing the silicon carbide semiconductor device becomes more complicated.
In view of the above-described problem, it is an object of the present invention to provide a silicon carbide semiconductor device having a high withstand voltage. It is another object of the present invention to provide a method for manufacturing a silicon carbide semiconductor device, the method having simplified manufacturing process.
A silicon carbide semiconductor device includes: a semiconductor substrate including a base substrate, a first semiconductor layer, a second semiconductor layer and a third semiconductor layer, which are laminated in this order; a cell portion disposed in the semiconductor substrate and providing an electric part forming portion; and a periphery portion surrounding the cell portion. The base substrate has a first conductive type and is made of silicon carbide. The first semiconductor layer is disposed on the base substrate, has the first conductive type, and is made of silicon carbide with a low impurity concentration lower than the base substrate. The second semiconductor layer has a second conductive type and is made of silicon carbide. The third semiconductor layer has the first conductive type and is made of silicon carbide. The periphery portion includes a trench, which penetrates the second and the third semiconductor layers, reaches the first semiconductor layer, and surrounds the cell portion so that the second and the third semiconductor layers are divided by the trench substantially. The periphery portion further includes a fourth semiconductor layer having the first conductive type and disposed on an inner wall of the trench.
In the silicon carbide semiconductor device, the trench and the fourth semiconductor layer disposed in the trench divide the second and the third semiconductor layers so that the second semiconductor layer works as a guard ring. This guard ring improves an insulation withstand voltage of the device, compared with a conventional device having an oxide film disposed on an inner wall of a trench. Thus, the device has the high withstand voltage.
Further, a method for manufacturing a silicon carbide semiconductor device includes the steps of: laminating a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in this order on a base substrate so that a semiconductor substrate is formed; forming a first trench in a cell portion of the semiconductor substrate to penetrate the second and the third semiconductor layers and to reach the first semiconductor layer; forming a second trench in a periphery portion of the semiconductor substrate to penetrate the second and the third semiconductor layers and to reach the first semiconductor layer so that the second trench surrounds the cell portion to divide the second and the third semiconductor layers substantially; forming a channel layer on an inner wall of the first trench by an epitaxial growth method; forming a fourth semiconductor layer on an inner wall of the second trench by an epitaxial growth method together with forming the channel layer; forming a fifth semiconductor layer on the channel layer; forming a gate electrode to connect to at least one of a first and second gate layers, which is provided by the fifth semiconductor layer in the cell portion and the second semiconductor layer in the cell portion, respectively; forming a source electrode to connect to a source layer, which is provided by the third semiconductor layer; and forming a drain electrode on a backside of the base substrate. The periphery portion surrounds the cell portion. The base substrate has a first conductive type and is made of silicon carbide. The first semiconductor layer is disposed on the base substrate, has the first conductive type, and is made of silicon carbide with a low impurity concentration lower than the base substrate. The second semiconductor layer has a second conductive type and is made of silicon carbide. The third semiconductor layer has the first conductive type and is made of silicon carbide. The channel layer has the first conductive type. The fourth semiconductor layer has the first conductive type. The fifth semiconductor layer has the second conductive type.
In the silicon carbide semiconductor device manufactured by the above method, the trench and the fourth semiconductor layer disposed in the trench divide the second and the third semiconductor layers so that the second semiconductor layer works as a guard ring. This guard ring improves an insulation withstand voltage of the device, compared with a conventional device having an oxide film disposed on an inner wall of a trench. Thus, the device has the high withstand voltage.
Further, in the above method for manufacturing the device, the first trench in the cell portion is formed together with the formation of the second trench in the periphery portion. Further, when the channel layer in the cell portion is formed, the fourth semiconductor layer is formed in the second trench at the same time. The second semiconductor layer provides the guard ring. Accordingly, an additional process for forming the guard ring only can be eliminated. Therefore, the process for forming the guard ring combines with the process for forming the J-FET so that the manufacturing process is simplified.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
First Embodiment
A silicon carbide semiconductor device according to a first embodiment of the present invention is shown in
The device includes a cell portion 51 and a periphery portion 52. In the cell portion 51 of the semiconductor substrate 5, multiple J-FETs (i.e., junction field effect transistors) are formed. The periphery portion 52 surrounds the cell portion 51. Thus, the silicon carbide semiconductor device is provided.
In the cell portion as a J-FET forming region, a trench 6 as the first trench is formed on a principal surface of the semiconductor substrate 5. The trench 6 penetrates the N+ conductive type layer 4 and the P+ conductive type layer 3, and reaches the N+ conductive type drift layer 2. The device includes multiple trenches 6 (not shown) so that the trenches 6 are aligned at predetermined intervals. An N− conductive type epitaxial layer (i.e., an N− epi-layer) 7 and a P+ conductive type layer 8 as the fifth semiconductor layer are formed on an inner wall of each trench 6 in this order. The N− epi-layer 7 as the first N− epi-layer provides a channel layer. The N− epi-layer 7 has a thickness equal to or thinner than 1 μm and an impurity concentration in a range between 5×1015 cm−3 and 5×1016 cm−3. The P+ conductive type 8 has an impurity concentration in a range between 1×1018 cm−3 and 5×1020 cm−3.
In the J-FET, the P+ conductive type layer 8 provides the first gate layer, and the other P+ conductive type layer 3 provides the second gate layer. The N+ conductive type layer 4 provides an N+ conductive type source layer. The device further includes the first gate electrode 9 and the second gate electrode 10. The first gate electrode 9 electrically connects to the P+ conductive type layer 8, and the second gate electrode 10 electrically connects to the P+ conductive type layer 3. Specifically, the first gate electrode 9 is formed on the surface of each P+ conductive type layer 8 as the first gate layer. The first gate electrode 9 is formed of a nickel (i.e., Ni) film and a nickel-aluminum (i.e., Ni—Al) alloy film. The Ni film is capable of contacting a P+ conductive type semiconductor with ohmic contact. The Ni film is formed on the P+ conductive type layer 8, and then, the Ni—AL alloy film is laminated on the Ni film so that the first gate electrode 9 is formed. The second gate electrode 10 is also formed on the surface of the P+ conductive type layer 3 as the second gate layer. The second gate electrode 10 can be actually formed on another sidewall, which is different from a position shown in
A source electrode 11 is formed on the surface of the N+ conductive type layer 4. The source electrode 11 is made of, for example, Ni. The source electrode 11 is electrically separated from the first and second gate electrodes 9, 10 with an interlayer insulation film and the like.
A drain electrode 12 is formed on the backside of the semiconductor substrate 5. The drain electrode 12 electrically connects to the N+ conductive type substrate 1. Thus, multiple J-FETs having the above construction are formed in the cell portion 51.
In the periphery portion 52, another trench 13 as the second trench is formed on the principal surface of the semiconductor substrate 5 in such a manner that the trench 13 penetrates the N+ conductive type layer 4 and the P+ conductive type layer 3 and reaches the N+ conductive type drift layer 2. Actually, the device includes multiple trenches 6 (not shown) so that the trenches 13 are aligned at predetermined intervals, for example at 2 μm intervals. Each trench 13 is embedded with an N− conductive type epitaxial layer (i.e., an N− epi-layer) 14 as the fourth semiconductor layer. The N− epi-layer 14 as the second N− epi-layer is formed together with the N− epi-layer 7 at the same time.
The trench 13 provides a guard ring. The depth of the second trench 13 disposed in the periphery portion 52 is almost equal to the first trench 6 disposed in the cell portion 51. The width of the second trench 13 disposed in the periphery portion 52 is narrower than the first trench 6 disposed in the cell portion 51. This is because when the first N− epi-layer 7 is formed on the inner wall of the first trench 6, the second N− epi-layer 14 fills the second trench 13 so that the second trench 13 is embedded with the second N− epi-layer 14 completely. For example, the thickness of the N− epi-layer 7 is about 0.5 μm, and the width of the second trench 13 is about 1 μm. Accordingly, the second trench 13 is embedded with the second N− epi-layer 14 completely when the first N− epi-layer 7 is formed on the inner wall of the first trench 6. In this case, the first trench 6 is not embedded with the first N− epi-layer 7 completely.
Thus, the P+ conductive type layer 3 and the N+ conductive type layer 4 are divided by the second trench 13 and the second N− epi-layer 14. The cell portion 51 is surrounded by the P+ conductive type layer 3 and the N+ conductive type layer 4, which are disposed between multiple trenches 13. Specifically, the P+ conductive type layer 3 works as the guard ring so that electric field disposed in the periphery portion 52 extend to an outer circumference of the cell portion 51. Thus, the electric field concentration is relaxed, i.e., reduced.
Each P+ conductive type layer 3 and each N+ conductive type layer 4 disposed between the trenches 13 becomes a floating state. Specifically, the P+ conductive type layers 3 and the N+ conductive type layers 4 are not electrically connected to the first and second gate electrodes 9, 10 and the source and the drain electrodes 11, 12.
Further, in the periphery portion 52, the third trench 15 is formed. The third trench 15 is disposed utmost outer portion of the periphery portion 52, which is disposed on the outside of the second trench 13. An N− conductive type epitaxial layer (i.e., an N− epi-layer) 16 as the third N− epi-layer is formed in the third trench 15. An N+ conductive type layer 17 is disposed under the bottom of the third trench 15. The depth of the third trench 15 is almost equal to the first trench 6 disposed in the cell portion 51. Further, the width of the third trench 15 is equal to the second trench 13. A distance between the third trench 15 and the second trench 13 is larger than a distance between the second trenches 13. Specifically, the distance between the third trench 15 and the utmost outer second trench 13 is, for example, 5 μm. Here, the distance between the second trenches is 2 μm. The third trench 15 and the N− conductive type layer 17 provide a channel stopper for an electric field (i.e., a EQR).
In the device having the above construction, the J-FET disposed in the cell portion works with a normally off operation. This operation is controlled by an applied voltage of each of the first and second gate electrodes 9, 10. The operation is described as follows.
In a case where the first gate electrode 9 and the second gate electrode 10 are electrically connected each other so that an electric potential of each electrode 9, 10 is controlled to have the same electric potential, a double gate operation is performed. Further, in a case where the first and second gate electrodes 10 are not electrically connected so that the electric potential of each electrode 9, 10 is controlled independently, the double gate operation is also performed. Specifically, when the device is operated with the double gate operation, an extension of a depletion layer extending from both of the P+ conductive type layers 3, 8 for providing the first and second gate layers is controlled on the basis of the electric potential of each of the first and second gate electrodes 9, 10. For example, when no voltage is applied to the first and second gate electrodes 10, 11, the first N− epi-layer 7 is pinched off by the depletion layer extending from both of the P+ conductive type layers 3, 8. Thus, a current between a source and a drain of the J-FET turns off, i.e., no current flows between the source and the drain of the J-FET. On the other hand, when a forward bias is applied between the P+ conductive type layers 3, 8 and the N− epi-layer 7, the extension of the depletion layer extending to the N− epi-layer 7 becomes smaller. Thus, a channel region is formed in the N− epi-layer 7 so that a certain current flows between the source and the drain of the J-FET.
In the silicon carbide semiconductor device according to the first embodiment, the trench 13 and the N− epi-layer 14 disposed in the trench 13 divide the P+ conductive type layer 3 so that the P+ conductive type layer 3 works as the guard ring. This guard ring improves the insulation withstand voltage of the device, compared with a conventional device having an oxide film disposed on an inner wall of a trench. Thus, the device of this embodiment has the high withstand voltage.
Next, a method for manufacturing the device shown in
Firstly, the N+ conductive type substrate 1 having a predetermined impurity concentration is prepared. The N− conductive type drift layer 2, the P+ conductive type layer 3, and the N+ conductive type layer 4 are formed in this order on the principal surface of the substrate 1 by an epitaxial growth method. Thus, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
After that, the interlayer insulation film is formed on the whole surface of the semiconductor substrate 5. Then, the contact hole is formed in the interlayer insulation film and the N+ conductive type layer 4 at a predetermined position. A wiring layer is formed on the interlayer insulation film, and then, the wiring layer is patterned by a photolithography method and the like. Thus, the first and the second gate electrodes 9, 10, and the source electrode 11 are provided. The drain electrode 12 is formed on the backside of the semiconductor substrate 5. Thus, the device is completed.
In the above method for manufacturing the device, the trench 6 in the cell portion 51 is formed together with the formation of the trenches 13, 15 in the periphery portion 52. Further, when the N− epi-layer 6 in the cell portion 51 is formed, the N− epi-layers 14, 16 are formed in the trenches 13, 15 at the same time. Thus, the P+ conductive type layer 3 provides the guard ring. Accordingly, an additional process for forming the guard ring only can be eliminated. In this embodiment, the process for forming the guard ring combines with the process for forming the J-FET so that the manufacturing process is simplified.
Although the device includes multiple trenches 13 for dividing the providing P+ conductive type layer 3 as the guard ring, the device can be include at least one part of the P+ conductive type layer 3 for working as the guard ring.
Although the J-FET of the device works with the double gate operation, in which the electric potential of each of the first and second gate electrodes 9, 10 is controlled independently, the device can have other operations. For example, only the electric potential of the first gate electrode 9 is independently controlled, and the electric potential of the second gate electrode 10 is set to be equal to the source electrode 11. In this case, the extension of the depletion layer extending from the P+ conductive type layer 3 to the N− epi-layer 7 is controlled on the basis of the electric potential of the first gate electrode 9. Thus, the J-FET of the device works with a single gate operation. In this case, the channel region in the N− epi-layer 7 is defined by the depletion layer extending from the P+ conductive type layer 3. Basically, the single gate operation is similar to the double gate operation.
Further, only the electric potential of the second gate electrode 10 is independently controlled, and the electric potential of the first gate electrode 9 is set to be equal to the source electrode 11. In this case, the extension of the depletion layer extending from the P+ conductive type layer 8 to the N− epi-layer 7 is controlled on the basis of the electric potential of the second gate electrode 10. Thus, the J-FET of the device works with the single gate operation. In this case, the channel region in the N− epi-layer 7 is defined by the depletion layer extending from the P+ conductive type layer 8. In this case, basically, the single gate operation is also similar to the double gate operation.
Although the first conductive type is the N conductive type, and the second conductive type is the P conductive type, the first conductive type can be the P conductive type, and the second conductive type can be the N conductive type.
Second Embodiment
A silicon carbide semiconductor device according to a second embodiment of the present invention is shown in
In this case, not only the P+ conductive type layer 3 disposed between the trenches 13 but also the P+ conductive type layer 20 disposed in the trench 13 work as the guard ring. Therefore, even when the construction of the trench 13 in the periphery portion 52 is the same as the trench 6 in the cell portion 51, the device according to the second embodiment has the same effect as the device shown in
Further, the P+ conductive type layer 20 in the periphery portion 52 can be formed together with the P+ conductive type layer 3 in the cell portion 51. Accordingly, an additional process for forming the guard ring only can be eliminated. Thus, the process for forming the guard ring combines with the process for forming the J-FET so that the manufacturing process is simplified.
In the device, a field plate is formed on the substrate 5 in the periphery portion 52. The construction of the field plate disposed in the periphery portion 52 is, for example, shown in
In
Third Embodiment
A silicon carbide semiconductor device according to a third embodiment of the present invention is shown in
In this case, the P+ conductive type layer 3 between the trenches 13 works as the guard ring. The oxide film 30 is formed on the surface of the N− epi-layer 14 disposed on the inner wall of the trench 13. Therefore, the oxide film 30 is surrounded with the N− epi-layer 14. Accordingly, the electric field generated from the N− conductive type drift layer 2 is applied to the oxide film 30 through the N− epi-layer 14. Therefore, when the impurity concentration of the N− epi-layer 14 is higher than the N− conductive type drift layer 2, the electric field concentration of the oxide film 30 is relaxed. Thus, the withstand voltage of the device is increased. Here, the impurity concentration of the N− epi-layer 14 is set to be equal to or higher than twice the impurity concentration of the N− conductive type drift layer 2.
Thus, the trench 13 in the periphery portion 52 can be embedded with the N− conductive type layer 14 and the oxide film 30. The oxide film 30 is formed as follows. After the N− conductive type layer 14 is formed on the inner wall of the trench 13, there is nothing on the surface of the N− conductive type layer 14. Therefore, when the P+ conductive type layer 8 is formed in the cell portion 51, the P+ conductive type layer 8 is also formed on the surface of the N− conductive type layer 14 in the trench 13. Therefore, after the P+ conductive type layer 8 is formed, a part of the P+ conductive type layer 8 disposed on the surface of the N− conductive type layer 14 in the trench 13 in the periphery portion 52 is removed. Then, the oxide film 30 is formed on the surface of the N− conductive type layer 14 by, for example, a CVD method (i.e., a chemical vapor deposition method).
Here, an oxide film forming process for forming the oxide film 30 can be combined with a process for forming the interlayer insulation film on the surface of the semiconductor substrate 5. Thus, the manufacturing process can be simplified.
Although the second and the third trenches 13, 15 have predetermined widths, respectively, the trenches 13, 15 can have other widths, respectively. When the width of the trench 13 is set to be wider, for example, wider than the trench 15, the penetration of the electric field penetrating into the oxide film 30 becomes larger than a case where the width of the trench 13 is set to be narrower than the trench 15. Therefore, the electric field concentration is much reduced, compared with the case where the trench 13 is narrow. Thus, the device has much high withstand voltage.
Fourth Embodiment
A silicon carbide semiconductor device according to a fourth embodiment of the present invention is shown in
In this embodiment, when the P+ conductive type layer 8 is formed in the cell portion 51, the P+ conductive type layer 8 is formed on the surface of the N− conductive type layer 14 in the trench 13. Therefore, after the P+ conductive type layer 8 is formed, a part of the P+ conductive type layer 8 disposed on the surface of the N− conductive type layer 14 in the trench 13 in the periphery portion 52 is removed. Then, the oxide film 40 is formed on the surface of the N− conductive type layer 14 by the thermal oxidation method.
In the device, when the impurity concentration of the N− epi-layer 14 is higher than the N− conductive type drift layer 2, the electric field concentration of the oxide film 40 is relaxed. Thus, the withstand voltage of the device is increased.
Fifth Embodiment
A silicon carbide semiconductor device according to a fifth embodiment of the present invention is shown in
In this case, not only the P+ conductive type layer 3 disposed between the trenches 13 but also the P/P+ conductive type layer 50 disposed in the trench 13 work as the guard ring. Therefore, even when the construction of the trench 13 in the periphery portion 52 is the same as the trench 6 in the cell portion 51, the device according to the fifth embodiment has the same effect as the device shown in
The P/P+ conductive type layer 50 is formed in such a manner that a P conductive type impurity is implanted from the surface of the N− epi-layer 14 on the bottom of the trench 13 before the oxide film 30 is formed in the trench 13.
Such changes and modifications are to be understood as being within the scope of the present invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-385092 | Nov 2003 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5233215 | Baliga | Aug 1993 | A |
| 20030096464 | Lanois | May 2003 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20050151158 A1 | Jul 2005 | US |
