Patent Grant
8901576
1. Field
The disclosure relates generally to an improved silicon photonics wafer and more specifically to fabricating a silicon photonics wafer using standard silicon-on-insulator processes through substrate removal or transfer.
2. Description of the Related Art
Silicon (Si) photonics is a technology that is under worldwide research and development due to its promise of delivering high performance optical components built in low-cost silicon chip technologies. Silicon photonics is the study and application of photonic systems that use silicon as an optical medium. The silicon is patterned with sub-micrometer precision into silicon photonic components. The silicon typically lies on top of a layer of silica in what is known as silicon-on-insulator (SOI).
In order for the silicon photonic components to remain optically independent from the bulk silicon of the wafer on which the silicon photonic components are fabricated, it is necessary to have a layer of intervening material. This layer of intervening material is usually silica, which has a lower optical refractive index than the silicon photonic components. As a result, light at the silicon-silica interface undergoes internal reflection and, therefore, remains in the silicon photonic components.
According to one embodiment of the present invention, a method for processing a silicon photonics wafer is provided. A silicon photonics wafer that includes an active silicon photonics layer, a thin buried oxide layer, and a silicon substrate is received for processing. The thin buried oxide layer is located between the active silicon photonics layer and the silicon substrate. An electrical complementary metal-oxide-semiconductor wafer that includes an active electrical layer is also received. The active silicon photonics layer of the silicon photonics wafer is flip chip bonded to the active electrical layer of the electrical complementary metal-oxide-semiconductor wafer. The silicon substrate is removed from the silicon photonics wafer exposing a backside surface of the thin buried oxide layer. Also, a low-optical refractive index backing wafer is optionally added to the exposed backside surface of the thin buried oxide layer of the silicon photonics wafer. The low-optical refractive index backing wafer is either a glass substrate wafer or a silicon substrate wafer. In addition, the silicon substrate wafer includes a thick oxide layer that is attached to the thin buried oxide layer of the silicon photonics wafer.
With reference now to the figures, and in particular, with reference to
In the course of developing illustrative embodiments, it was discovered that a custom, non-standard silicon-on-insulator wafer with a thick buried oxide layer was needed to enable functionality of silicon optical device structures in active silicon photonics layer 106 and silicon waveguide 112. The silicon optical device structures (i.e., photonic devices) are fabricated in the front side silicon layer of the silicon photonics wafer. A photonic device is any structure fabricated in the front side silicon layer that guides, generates, manipulates, or detects pulses of light. Examples of photonic devices are lasers, optical modulators, photodetectors, and optical switches, with optical waveguides used for optical input and output. In addition, the front side silicon layer also may include fabricated electronic devices, along with the photonic devices. Examples of electronic devices that may be included in the front side silicon layer are transistors, capacitors, resistors, and inductors. However, it should be noted that depending on the illustrative embodiment, the front side silicon layer may include only photonic devices or may include both electronic devices and photonic devices. A standard fabrication process for these photonic and electronic devices is a complimentary metal oxide-semiconductor (CMOS) process.
Custom thick buried oxide layer 108 of silicon photonics wafer 102 is buried between active silicon photonics layer 106 and silicon substrate 110. Active silicon photonics layer 106 is on a front side of silicon photonics wafer 102. Active silicon photonics layer 106 propagates light waves and includes the silicon photonic devices, which are essentially transparent to the light waves. In addition, as noted above, active silicon photonics layer 106 also may include electronic devices. Further, it should be noted that any active silicon photonics layer referenced in the detailed description below, in the figures, or in the claims may include both photonic devices and electronic devices or may include only photonic devices. Silicon substrate 110 is on a backside of silicon photonics wafer 102 and is a bulk silicon layer that provides support for silicon photonics wafer 102. Custom thick buried oxide layer 108 is typically greater than or equal to one (1) micrometer (um) in thickness. Custom thick buried oxide layer 108 may, for example, be comprised of silicon dioxide (SiO2) material.
Without custom thick buried oxide layer 116, the high-optical refractive index of silicon substrate 118 makes it difficult to build low light transmission loss silicon waveguide structures, such as silicon waveguide 112. Light transmission loss is the reduction of the intensity of the light wave with respect to the distance traveled by the light wave through the transmission medium, which in this example is silicon waveguide 112. However, the requirement of a custom thick buried oxide layer adds to the complexity and cost of implementing silicon photonics wafers in a monolithically integrated CMOS process because standard industrial silicon-on-insulator processes use base wafers with a thin buried oxide layer. Typically, a standard thin buried oxide layer is less than 500 nanometers (nm) in thickness as compared to the one micrometer or greater thickness of a custom thick buried oxide layer.
Custom thick buried oxide layer 116 serves as a low-optical refractive index cladding material. In addition, CMOS dielectric stack 114 also serves as a low-optical refractive index cladding material. Cladding is one or more layers of lower optical refractive index material in contact with a core material of higher optical refractive index, which in this example is silicon waveguide 112 that is etched as a rectangular cross-section structure in the active silicon photonics layer. The cladding material causes light to be confined to the core of the silicon waveguide structure by internal reflection at the boundary between the cladding material and the silicon waveguide structure. However, if a standard thin buried oxide layer is used in fabricating the silicon photonics wafer, then high light transmission loss will occur because the light tends to couple with the higher optical refractive index of the silicon substrate of the silicon photonics wafer.
Illustrative embodiments enable low-loss silicon optical waveguide structures and other active silicon photonic devices in standard silicon-on-insulator processes using standard thin buried oxide layers by removing the higher optical refractive index silicon substrate from the silicon photonics wafer after fabrication of the silicon photonic devices and CMOS electrical devices in the active silicon photonics layer. By removing the backside higher optical refractive index silicon substrate below the buried oxide layer, illustrative embodiments make it possible to utilize standard silicon-on-insulator wafers, along with standard CMOS fabrication processes, while still enabling low-loss silicon optical waveguide structures to function in the front side active silicon photonics layer of the silicon photonics wafers. As a result, illustrative embodiments lower the complexity and cost of implementing silicon photonics wafers because illustrative embodiments allow for the use of unmodified CMOS silicon-on-insulator processing and wafers. Thus, by removing the requirement of a custom thick buried oxide layer, the additional steps to modify CMOS processes from standard silicon-on-insulator processes to accommodate thick silicon-on-insulator wafers is not required, which saves time and cost. Further, illustrative embodiments avoid issues with custom thick silicon-on-insulator wafers, such as, for example, increased wafer bowing as compared to the thin silicon-on-insulator wafers and the lack of thick silicon-on-insulator substrates in any diameters larger than 200 millimeters (mm).
With reference now to
Silicon photonics wafer 204 includes silicon waveguide 214, CMOS dielectric stack 216, and silicon substrate 220, such as silicon waveguide 112, CMOS dielectric stack 114, and silicon substrate 118 of silicon photonics wafer 104 in
By removing the high-optical refractive index silicon substrates 212 and 220 after the active device structures are fabricated in the active silicon photonics layer, illustrative embodiments enable the functionality of silicon photonic structures fabricated on standard thin oxide silicon-on-insulator wafers, which offer low-loss light propagation because the silicon core region (i.e., silicon waveguide 222) is now surrounded by low-optical refractive index material (i.e., CMOS dielectric stack 224 on a front side of silicon waveguide 222 and standard thin buried oxide layer 226 on a backside of silicon waveguide 222). In addition, illustrative embodiments may subsequently add either air or low-optical refractive index material 228 on a backside surface of standard thin buried oxide layer 226.
With reference now to
Fabrication process 300 is a process for electrically bonding a standard thin silicon-on-insulator photonics wafer to an electrical CMOS wafer. Fabrication process 300 includes process steps 302, 304, 306, and 308. Process step 302 includes fabrication of a silicon photonics wafer with a standard thin buried oxide layer, such as silicon photonics wafer 202 in
At step 302, a silicon photonics wafer is designed in a standard silicon-on-insulator CMOS process and then fabricated. The fabrication of the silicon photonics wafer includes the formation of electrical CMOS devices and optical devices in the active silicon photonics layer, such as active silicon photonics layer 208 in
Once standard CMOS fabrication of the silicon photonics wafer is completed, additional processing options of the silicon photonics wafer are available for silicon substrate removal and/or transfer of a new low-optical refractive index substrate material onto the silicon photonics wafer. Although the additional processing options are described herein as wafer-scale processes, it should be noted that each processing option may be performed on individual chips. For processing options where the silicon photonics wafer is transferred or bonded to a new substrate, the new substrate may include optical and mechanical features. The optical features included in the new substrate may be, for example, integrated micro-lenses or prisms and the mechanical features may be, for example, alignment holes or posts.
In addition to the optical lens structures and mechanical alignment features designed for surface-normal optical coupling, the new substrate bonded to the silicon photonics wafer also may include features designed to turn optical signals by 90-degrees such that the optical signals enter/exit the new substrate of the silicon photonics chip in a direction parallel to the silicon photonics chip, which is shown in the example of
At process step 304, the silicon photonics wafer is bonded to the electrical CMOS wafer. The electrical CMOS wafer may include a variety of circuits, such as, for example, digital logic, high-speed analog, and microprocessors, in the active electrical layer. The silicon photonics wafer is flip chip bonded with its active silicon photonics layer, such as active silicon photonics layer 208 in
After the wafers are bonded together and the electrical connections made, the silicon substrate of the silicon photonics wafer, such as silicon substrate 212 in
After the removal of the silicon substrate, a low-optical refractive index material, such as low-optical refractive index material 228 in
Moreover, it should be noted that although an electrical CMOS wafer is shown in this example of
With reference now to
Fabrication process 400 is a process for transferring a silicon photonics wafer to a low-optical refractive index material, such as low-optical refractive index material 228 in
At process step 404, the silicon photonics wafer is bonded to a temporary handler wafer. An adhesive, for example, may be used to bond the silicon photonics wafer to the temporary handler wafer. Also, the temporary handler wafer may be, for example, a glass handler wafer. The active devices in the active silicon photonics layer of the silicon photonics wafer are face down toward the temporary handler wafer.
At process step 406, the silicon substrate is removed from the silicon photonics wafer similar to process step 306 in
After the low-optical refractive index backing wafer is bonded to the silicon photonics wafer, the front side surface of the active silicon photonics layer of the silicon photonics wafer is detached from the temporary handler wafer at step 410. The low-optical refractive index backing wafer is now the new substrate for the silicon photonics wafer. After completing fabrication process 400, the silicon photonics wafer with the new substrate may be, for example, electrically attached to an electrical CMOS wafer through conventional processes, such as solder bumping and reflow, similar to process step 304 in
With reference now to
Fabrication process 500 is a process for the removal of the silicon substrate at selected sites under photonic devices in an active silicon photonics layer of a silicon photonics wafer and attachment of a backing wafer to the silicon substrate. Fabrication process 500 includes process steps 502, 504, 506, 508, and 510. Process step 502 includes fabrication of a silicon photonics wafer with a standard thin buried oxide layer, such as standard thin buried oxide layer 226 in
At process step 504, the silicon photonics wafer is bonded to a temporary handler wafer with an adhesive, for example. The temporary handler wafer may be, for example, a glass handler wafer. The active devices in the active silicon photonics layer of the silicon photonics wafer are face down toward the temporary handler wafer.
At process step 506, backside trenches are etched in the silicon substrate at selected sites under photonic devices, such as optical waveguides, located within the active silicon photonics layer of the silicon photonics wafer. In the example at step 506, three photonic devices are located under the three backside trenches. However, it should be noted that the three illustrated photonic devices represent a 3×N array of photonic devices in the active silicon photonics layer. In addition, illustrative embodiments are not limited to a 3×N array of photonic devices or to three backside trenches. In other words, illustrative embodiments may utilize any number of photonic devices and backside trenches in the silicon photonics wafer.
The selective silicon substrate removal is performed using a photolithography process on the backside of the silicon photonics wafer followed by chemical etching. Selectively etching backside trenches in the silicon substrate exposes a backside surface of the thin buried oxide layer at the selected sites. The backside trenches may be, for example, filled with air. Also, it should be noted that the silicon substrate may be left intact under electronic devices located within the active silicon photonics layer where the silicon substrate was not removed by the chemical etching. In this example, four electrical devices are located under the four columns of silicon substrate that represent a 4×N array of electrical devices in the active silicon photonics layer. However, it should be noted that illustrative embodiments are not limited to a 4×N array of electrical devices and may utilize any number of electrical devices in the silicon photonics wafer.
After the silicon substrate is removed at the selected sites, a low-optical refractive index backing wafer is added to a backside surface of the etched silicon substrate of the silicon photonics wafer at process step 508 covering the backside trenches. In addition, the backing wafer may add mechanical strength to prevent the silicon photonics wafer from breaking in areas where the silicon substrate has been completely removed. The low-optical refractive index backing wafer added to the etched silicon substrate of the silicon photonics wafer may be, for example, a glass substrate backing wafer or a silicon substrate backing wafer. After the low-optical refractive index backing wafer is bonded to the silicon photonics wafer, the front side surface of the active silicon photonics layer of the silicon photonics wafer is detached from the temporary glass handler wafer at step 510. After completing fabrication process 500, the silicon photonics wafer with the added backing wafer may be, for example, electrically attached to an electrical CMOS wafer through conventional processes, such as solder bumping and reflow, similar to process step 304 in
With reference now to
Silicon photonic devices 610 represents a plurality of silicon photonic devices that are integrally fabricated by a microlithographic process into the silicon of active silicon photonics layer 602, along with silicon waveguides 614, diffractive element 612, and reflective element 616. In the case of diffractive element 612, the addition of a mirror or thin metal film layer above diffractive element 612 may be used to enhance optical coupling efficiency between diffractive element 612 and silicon photonic devices 610. The mirror or thin metal film layer may be, for example, located in a CMOS dielectric stack, such as CMOS dielectric stack 224 in
Silicon photonic devices 610 may represent an N×N array of different types of photonic devices. For example, silicon photonic devices 610 may represent emitters or modulators for transmitting optical data signals and also may represent photodiodes for receiving optical data signals. Thus, silicon photonic devices 610 may provide optical transceiver capabilities for silicon photonics chip 600.
Silicon waveguides 614 may be, for example, rectangular structures that guide optical signals or electromagnetic waves to and from silicon photonic devices 610. Silicon waveguides 614 represent arrays of silicon waveguides for guiding optical input/output 620 to and from the array of silicon photonic devices 610. Reflective element 616 is another microlithographically etched structure in active silicon photonics layer 602 designed to reflect optical input/output 620 to and from silicon photonic devices 610 via silicon waveguides 614. Alternatively, reflective element 616 may be, for example, a mirror or a thin metal film.
Similarly, diffractive element 612 also is a microlithographically fabricated structure in active silicon photonics layer 602 that is designed to diffract rather than reflect optical input/output 620 to and from silicon photonic devices 610. One benefit of using diffractive element 612 is that diffractive element 612 may perform a plurality of optical operations simultaneously. However, it should be noted that even though in this example of
Silicon photonics chip 600 also includes reflective element 618. In this example of
With reference now to
The process begins when the assembler receives a fabricated silicon photonics wafer that includes an active silicon photonics layer, a standard thin buried oxide layer, and a silicon substrate for processing (step 702). The fabricated silicon photonics wafer may be, for example, silicon photonics wafer 202 in
Then the assembler flip chip bonds the active silicon photonics layer of the fabricated silicon photonics wafer to the active electrical layer of the fabricated electrical CMOS wafer similar to process step 304 in
With reference now to
The process begins when the assembler receives a fabricated silicon photonics wafer that includes an active silicon photonics layer, a standard thin buried oxide layer, and a silicon substrate for processing (step 802). The fabricated silicon photonics wafer may be, for example, silicon photonics wafer 202 in
Afterward, the assembler removes the silicon substrate from the fabricated silicon photonics wafer exposing a backside surface of the standard thin buried oxide layer similar to process step 406 in
With reference now to
The process begins when the assembler receives a fabricated silicon photonics wafer that includes an active silicon photonics layer, a standard thin buried oxide layer, and a silicon substrate for processing (step 902). The fabricated silicon photonics wafer may be, for example, silicon photonics wafer 202 in
After bonding the active silicon photonics layer of the fabricated silicon photonics wafer to a temporary glass handler wafer in step 904, the assembler etches backside trenches in the silicon substrate at selected sites under photonic devices located within the active silicon photonics layer of the fabricated silicon photonics wafer exposing a backside surface of the standard thin buried oxide layer at the selected sites similar to process step 506 in
Then the assembler adds a low-optical refractive index backing wafer to the etched silicon substrate of the fabricated silicon photonics wafer for mechanical support similar to process step 508 in
With reference now to
Processor unit 1004 serves to execute instructions for software that may be loaded into memory 1006. Processor unit 1004 may be a number of processors, a multi-processor core, or some other type of processor, depending on the particular implementation.
Memory 1006 and persistent storage 1008 are examples of storage devices 1016. A storage device is any piece of hardware that is capable of storing information, such as, for example, without limitation, data, program code in functional form, and/or other suitable information either on a temporary basis and/or a persistent basis. Storage devices 1016 may also be referred to as computer readable storage devices in these illustrative examples. Memory 1006 in these examples may be, for example, a random access memory or any other suitable volatile or non-volatile storage device. Persistent storage 1008 may take various forms, depending on the particular implementation.
For example, persistent storage 1008 may contain one or more components or devices. For example, persistent storage 1008 may be a hard drive, a flash memory, a rewritable optical disk, a rewritable magnetic tape, or some combination of the above. The media used by persistent storage 1008 also may be removable. For example, a removable hard drive may be used for persistent storage 1008.
Communications unit 1010, in these illustrative examples, provides for communications with other data processing systems or devices. In these illustrative examples, communications unit 1010 is a network interface card.
Input/output unit 1012 allows for input and output of data with other devices that may be connected to data processing system 1000. For example, input/output unit 1012 may provide a connection for user input through a keyboard, a mouse, and/or some other suitable input device. Further, input/output unit 1012 may send output to a printer. Display 1014 provides a mechanism to display information to a user. Data processing system 1000 uses assembler 1028 to fabricate, assemble, or process, for example, optical transceiver chips, such as silicon photonics chip 600 in
Instructions for the operating system, applications, and/or programs may be located in storage devices 1016, which are in communication with processor unit 1004 through communications framework 1002. The processes of the different embodiments may be performed by processor unit 1004 using computer-implemented instructions, which may be located in a memory, such as memory 1006.
These instructions are referred to as program code, computer usable program code, or computer readable program code that may be read and executed by a processor in processor unit 1004. The program code in the different embodiments may be embodied on different physical or computer readable storage media, such as memory 1006 or persistent storage 1008.
Program code 1018 is located in a functional form on computer readable media 1020 that is selectively removable and may be loaded onto or transferred to data processing system 1000 for execution by processor unit 1004. Program code 1018 and computer readable media 1020 form computer program product 1022 in these illustrative examples. In one example, computer readable media 1020 may be computer readable storage media 1024 or computer readable signal media 1026. In these illustrative examples, computer readable storage media 1024 is a physical or tangible storage device used to store program code 1018 rather than a medium that propagates or transmits program code 1018.
Alternatively, program code 1018 may be transferred to data processing system 1000 using computer readable signal media 1026. Computer readable signal media 1026 may be, for example, a propagated data signal containing program code 1018. For example, computer readable signal media 1026 may be an electromagnetic signal, an optical signal, and/or any other suitable type of signal. These signals may be transmitted over communications links, such as wireless communications links, optical fiber cable, coaxial cable, a wire, and/or any other suitable type of communications link.
The different components illustrated for data processing system 1000 are not meant to provide architectural limitations to the manner in which different embodiments may be implemented. The different advantageous embodiments may be implemented in a data processing system including components in addition to and/or in place of those illustrated for data processing system 1000. Other components shown in
Thus, illustrative embodiments provide a method and apparatus for processing a silicon photonics wafer. The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiment. The terminology used herein was chosen to best explain the principles of the embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed here.
The flowcharts and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of methods according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of code which comprises one or more executable instructions for implementing the specified logical function(s). It also should be noted that, in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The circuit as described above is part of the design for an integrated circuit chip. The chip design is created in a graphical computer programming language and stored in a computer readable storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer transmits the resulting design by physical means (e.g., by providing a copy of the computer readable storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
The description of the present invention has been presented for purposes of illustration and description and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4722586 | Dodson et al. | Feb 1988 | A |
| 4867371 | Yamazaki | Sep 1989 | A |
| 4935939 | Liau et al. | Jun 1990 | A |
| 5195150 | Stegmueller et al. | Mar 1993 | A |
| 5346583 | Basavanhally | Sep 1994 | A |
| 5499312 | Hahn et al. | Mar 1996 | A |
| 5568574 | Tanguay, Jr. et al. | Oct 1996 | A |
| 5790730 | Kravitz et al. | Aug 1998 | A |
| 6075908 | Paniccia et al. | Jun 2000 | A |
| 6095697 | Lehman et al. | Aug 2000 | A |
| 6304687 | Inoue et al. | Oct 2001 | B1 |
| 6333208 | Li | Dec 2001 | B1 |
| 6455398 | Fonstad, Jr. et al. | Sep 2002 | B1 |
| 6727576 | Hedler et al. | Apr 2004 | B2 |
| 6934133 | Hayakawa et al. | Aug 2005 | B2 |
| 6935792 | Saia et al. | Aug 2005 | B2 |
| 6955934 | Gallup et al. | Oct 2005 | B2 |
| 7010184 | Hasegawa et al. | Mar 2006 | B2 |
| 7027687 | Kishima | Apr 2006 | B2 |
| 7110629 | Bjorkman et al. | Sep 2006 | B2 |
| 7128476 | Boudreaux et al. | Oct 2006 | B1 |
| 7162124 | Gunn, III et al. | Jan 2007 | B1 |
| 7203387 | Doan | Apr 2007 | B2 |
| 7251398 | Baets et al. | Jul 2007 | B2 |
| 7283717 | Mendoza et al. | Oct 2007 | B2 |
| 7298941 | Palen et al. | Nov 2007 | B2 |
| 7303339 | Zhou et al. | Dec 2007 | B2 |
| 7344383 | Lu et al. | Mar 2008 | B1 |
| 7349614 | Doan | Mar 2008 | B2 |
| 7352066 | Budd et al. | Apr 2008 | B2 |
| 7352924 | Gaebe et al. | Apr 2008 | B2 |
| 7454102 | Keyser et al. | Nov 2008 | B2 |
| 7454105 | Yi et al. | Nov 2008 | B2 |
| 7548669 | Nakagawa | Jun 2009 | B2 |
| 7553088 | Nakajima | Jun 2009 | B2 |
| 7556440 | Birincioglu et al. | Jul 2009 | B2 |
| 7639912 | Wang et al. | Dec 2009 | B2 |
| 7702197 | Nakagawa | Apr 2010 | B2 |
| 7703993 | Darbinyan et al. | Apr 2010 | B1 |
| 7729581 | Rolston et al. | Jun 2010 | B2 |
| 7773836 | De Dobbelaere | Aug 2010 | B2 |
| 7801397 | Block et al. | Sep 2010 | B2 |
| 7920770 | Holzwarth et al. | Apr 2011 | B2 |
| 20020076130 | Pandraud | Jun 2002 | A1 |
| 20030231828 | Brock et al. | Dec 2003 | A1 |
| 20040155325 | Ma et al. | Aug 2004 | A1 |
| 20050058408 | Colgan et al. | Mar 2005 | A1 |
| 20060177173 | Shastri et al. | Aug 2006 | A1 |
| 20070274630 | Ghrion et al. | Nov 2007 | A1 |
| 20080285920 | Budd et al. | Nov 2008 | A1 |
| 20080298818 | Epitaux et al. | Dec 2008 | A1 |
| 20090046456 | Urano et al. | Feb 2009 | A1 |
| 20090087137 | Doan | Apr 2009 | A1 |
| 20090154872 | Sherrer et al. | Jun 2009 | A1 |
| 20090226130 | Doany et al. | Sep 2009 | A1 |
| 20090263923 | Shimooka | Oct 2009 | A1 |
| 20090294814 | Assefa et al. | Dec 2009 | A1 |
| 20100008675 | De Dobbelaere | Jan 2010 | A1 |
| 20100055919 | Carothers | Mar 2010 | A1 |
| 20100059822 | Pinguet et al. | Mar 2010 | A1 |
| 20100061683 | Sasaki | Mar 2010 | A1 |
| 20100111473 | Pinguet et al. | May 2010 | A1 |
| 20100119192 | Fujikata et al. | May 2010 | A1 |
| 20100135619 | Choi et al. | Jun 2010 | A1 |
| 20110052114 | Bernasconi et al. | Mar 2011 | A1 |
| 20110193169 | Assefa et al. | Aug 2011 | A1 |
| 20110216997 | Gothoskar et al. | Sep 2011 | A1 |
| 20120207426 | Doany et al. | Aug 2012 | A1 |
| 20130084039 | Doany et al. | Apr 2013 | A1 |
| Entry |
|---|
| U.S. Appl. No. 13/028,814, Doany et al. |
| U.S. Appl. No. 13/211,018, Doany et al. |
| Doany et al., “Through-Substrate Optical Coupling to Photonic Chips,” U.S. Appl. No. 13/370,886, filed Feb. 10, 2012, 28 pages. |
| Ade et al., “Direct backside connection of optical fibers to GaAs detectors”, Proceedings of SPIE vol. 881, Optical Computing and Nonlinear Materials, May 1988, pp. 199-203. |
| Dillon et al., “Micromachining of a fiber-to-waveguide coupler using grayscale lithography and through-wafer etch”, Proceedings of SPIE vol. 6882, Micromachining and Microfabrication Process Technology XIII, Feb. 2008, pp. 688206.1-688206.10. |
| Jones et al., “Advanced applications of wafer bonding,” In: Silicon Wafer Bonding Technology for VLSI and MEMS Applications, Iyer et al., (Eds.), INSPEC/IEE, 2002, pp. 93-121. |
| Palen, “Optical coupling to monolithic integrated photonic circuits”, Proceedings of SPIE vol. 6478, Photonics Packaging, Integration, and Interconnects VII, Feb. 2007, pp. 64780K.1-64708K.6. |
| Office Action, dated Dec. 20, 2012, regarding U.S. Appl. No. 13/028,814, 11 pages. |
| Final Office Action, dated Jul. 3, 2013, regarding U.S. Appl. No. 13/028,814, 11 pages. |
| Cunningham et al., “Compact, Thermally-Tuned Resonant Ring Muxes in CMOS with Integrated Backside Pyramidal Etch Pit,” Optical Fiber Communication Conference, OSA Technical Digest (CD), Optical Society of America, Mar. 6, 2011, OMV3, 3 pages. |
| Holzwarth et al., “Localized Substrate Removal Technique Enabling Strong-Confinement Microphotonics in Bulk Si CMOS Processes,” In: Conference on Lasers and Electro-Optics/Quantum Electronics and Laser Science Conference Photonic Applications Systems Technologies, OSA Technical Digest, CThKK5, Massachusetts Institute of Technology, May 2008, 2 pages. |
| Jones et al., “Advanced Applications of Wafer Bonding,” In: Silicon Wafer Bonding Technology for VLSI and MEMS Applications, Iyer et al. (Eds.), INSPEC/IEE, United Kingdom, pp. 93-121, 2002 (Abstract only). |
| Lentine et al., High-speed optoelectronic VLSI switching chip with >4000 optical I/O based on flip-chip bonding of MQW modulators and detectors to silicon CMOS:, IEEE Journal of Selected Topics in Quantum Electronics, 2 (1):77-84, Apr. 1996. |
| Nakagawa et al., “Highly Efficient Coupling Between LD Array and Optical Fiber Array Using Si Microlens Array,” IEEE Photonics Technology Letters, 5(9):1056-1058, Sep. 1993. |
| Orcutt, et al., “Photonic integration in a commercial scaled bulk-CMOS process,” Massachusetts Institute of Technology, Nov. 3, 2009, 2 pages. |
| Schares et al., “Terabus: Terabit/Second-Class Card-Level Optical Interconnect Technologies,” IEEE Journal of Selected Topics in Quantum Electronics, 12(5):1032-1044, Sep./Oct. 2006. |
| Tan et al., “Soldering Technology for Optoelectronic Packaging,” In: Passive Micro-Optical Alignment Methods, Department of Mechanical Engineering, University of Colorado, pp. 149-186, Jun. 2005. |
| Thacker et al., “Flip-Chip Integrated Silicon Photonic Bridge Chips for Sub-Picojoule Per Bit Optical Links,” 2010 Electronic Components and Technology Conference, Las Vegas, Nevada, pp. 240-246, Jun. 1-4, 2010. |
| Office Action, dated Mar. 19, 2014, regarding U.S. Appl. No. 13/028,814, 8 pages. |
| Office Action, dated Feb. 20, 2014, regarding U.S. Appl. No. 13/370,886, 17 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20130181233 A1 | Jul 2013 | US |
