Patent Application
20090243690
1. Technical Field of the Invention
The present invention relates generally to a high speed digital clock circuit that produces multiple clock frequencies, and particularly to a wireless communication system using the clock circuit, one such system being the Multi-Band Orthogonal Frequency Digital Modulation (OFDM) Alliance (MBOA) Ultra Wideband (UWB) system.
2. Description of the Prior Art
Digital clock generation is used in digital electronic systems to maintain synchronism of processes. In the MBOA UWB system, several radio frequency (RF) clock frequencies subject to severe timing restraints are needed in the transceiver circuitry. Clock generators are typically used to generate one or more clocks employed by various circuits in the system. A voltage-controlled oscillator (VCO) is typically used to generate a clock signal. Some constraints of VCOs include tuning range and potential interference in frequency bands of interest due to harmonic spurs. Improved design of a clock generation scheme can achieve an optimized system in terms of power consumption, tuning range, form factor and manufacturing cost.
Existing digital clock generators have used a three voltage controlled oscillator design to provide the three required clock frequencies. Such a design is straightforward, but it suffers from high power consumption and has a large form factor. Form factor refers to the size, configuration, or physical arrangement of the circuit. A larger form factor generally relates to high manufacturing costs.
Another prior art digital clock generator uses two voltage controlled oscillators combined with a mixer. Although not as straightforward as using voltage controlled oscillators to generate the needed three clock frequencies, this design requires only two voltage controlled oscillators. However, two voltage controlled oscillators still consume significant power, while resulting in a large form factor and high manufacturing costs.
What is needed is a clock frequency generator with reduced power consumption and form factor, as well as lower manufacturing costs.
Briefly, in an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a clock signal quadrature output frequency and a clock signal in-phase output frequency. The clock generator circuit generates a single clock frequency that is a fraction of the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output that is phase and frequency synchronized to the single clock frequency.
The foregoing and other objects, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments which make reference to several figures of the drawing.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses clock generation circuits which generate multiple clock frequencies using a single voltage controlled oscillator (VCO). By using only a single VCO a smaller form factors and thereby lower manufacturing cost is achieved. By sharing the first divider of a divider circuit between clock generation and a phase locked loop (PLL), lower power consumption can also be achieved. Such a design can be used in electronic systems that use multiple clock frequencies, more particularly applicable to a wireless communication system. For example, in Multi-Band OFDM Alliance (MBOA) Ultra Wideband (UWB) system, each band group needs three clock frequencies. By using one VCO to generate all three frequencies, the required additional cock generation circuits currently used in the prior art can be eliminated. The reduction in required clock generation source circuits in the present invention reduces both power consumption and manufacturing cost when compared existing digital clock generators. The present invention also enables faster frequency hopping in a time frequency interleaving (TFI) mode, where less than 9 ns is allowed for switching between two clock frequencies.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of embodiments of the present invention.
The dividers 102, 104, 105 and 108 serve as fractional frequencies by dividing the frequency of their input by a predetermined value. For example, the divider 104 divides by the integer value 4, which results in the frequency of its input being divided by four. The dividers 104 and 105 collectively divide frequency by 7.
VCO 101 is shown to receive the filtered phase synchronized error signal 136 from low-pass filter 111 and is operative to generate single clock frequency f0135. The low-pass filter 111 is shown to receive a synchronized signal 133, which is generated by the phase frequency detector (PFD) 109. The PFD 109 is shown to receive a reference frequency 132 from the reference frequency generator 110. The reference frequency generator 110 generates the reference frequency 132.
First divider 102 is shown to receive frequency 135 and is operative to divide the frequency 135 by approximately half (or two) to yield an in-phase and a quadrature output, which are 90 degrees phase-offset to one another. Quadrature output, as used herein, describes the output of a frequency divider 102, 104, 105, or 108 in the form of both a carrier wave and a ‘quadrature’ carrier wave that is 90° out of phase with the main carrier. Because the clock generator circuit 100 advantageously uses only a single voltage controlled oscillator (VCO), the resulting output frequencies of divider 102, 104, 105, and 108 does not require further synchronization following each division. This advantageously reduces form factor and decreases power consumption and manufacturing costs. Prior art designs using multiple VCOs require further synchronization of their VCO outputs.
First divider 102 is operative to generate clock signal output frequency 120. Clock signal output frequency 120 is further comprised of clock signal quadrature output frequency 120a, and clock signal in-phase output frequency 120b. Both frequency 120a and frequency 120b are received by frequency selection switch 107, and first single sideband (SSB) mixer 103.
First single sideband (SSB) mixer 103 is shown to receive clock signal output frequency 120, consisting of frequency 120a and 120b, and is operative to generate phase and frequency synchronized clock frequency f1121. Phase and frequency synchronized clock frequency f1121 is shown to be comprised of a quadrature phase frequency 121a and an in-phase frequency 121b. Mixer 103 additionally receives output 123 from third divider 105, which is used in generating frequency 121. Output 123 is shown to be comprised of a quadrature output 123a and a in-phase output 123b. Second divider 104 is shown to receive frequency 121, comprising frequency 121a and frequency 121b, and is operative to generate output 122. Output 122 is shown to be further comprised of quadrature output 122a, and in-phase output 122b. Third divider 105 is shown to receive output 122, comprised of output 122a and 122b, and is operative to generate output 123. Output 123 is shown to be further comprised of quadrature output 123a and in-phase output 123b. Output 123 is received by mixer 103. In total, mixer 103 receives two separate and unique inputs, output 123 and output.
Feedback clock-frequency generator 137 is shown to be comprised of a voltage controlled oscillator (VCO) 101, a first divider 102, a first single sideband (SSB) mixer 103, second divider 104, and a third divider 105. During operation of either the embodiment 100 of
In an exemplary embodiment of the present invention, second divider 104 divides by 8. Among resulting outputs of divider 104 are the outputs of dividing the frequency by 5. Effectively, the output of divider 104 includes the resulting output of dividing by integers 5, 7, and 9. Through dividing by 8 with divider 104 the circuit 100 generates an output which can later be divided by two at divider 105. The resulting output of divider 105 and divider 104 advantageously allows a single VCO to generate the three required clock frequencies. Furthermore, frequency is divided by an odd value, which is not done by prior art methods.
Described in the context of the specific frequency requirements of Multi-Band OFDM Alliance (MBOA) Ultra Wideband (UWB) system, VCO 101 generates a substantially 3,960 MHz source frequency, the first single sideband mixer 103 generates a frequency offset of substantially +/−528 MHz, and the second divider 104 divides by 8 and third divider 105 divides by two to yield hopping frequencies of substantially 3,432 MHz, 3,960 MHZ and 4,488 MHz for Band-Group One compliant with the aforementioned system.
In an example where a division by 7 of the frequency is desired at the output of the divider 104, this is done by the following equations:
fi+fx/8=fx Eq. (1)
fi=fx*7/8 Eq. (2)
fx=fi/7*8 Eq. (3)
where fx is the desired frequency, Eq. (1) is the output of the divider 104 and Eqs. (2) and (3) describe the operation of the divider 105 and the respective output frequency. Thus, the frequency of the phase and frequency synchronized clock frequency f1121 is effectively divided by 7, which is an odd number.
The mixer 103 further receives as input a clock 123 whose frequency is equal to the output frequency of mixer 103 divided by the product of B times C, which in the preferred embodiment is 8 times 2 or 16. The quadrature output 120a and in-phase output 120b is shown to be coupled to the frequency selection switch 107 and to the mixer 106.
The mixer 103 is a single sideband mixer that combines (or multiplies) the in-phase components and also separately multiplies the quadrature components. In an alternative embodiment, the mixer 103 is a double quadrature sideband mixer that multiplies the in-phase components together and the quadrature components together and then also multiplies the in-phase and the quadrature components. It should be noted however, that the double quadrature sideband mixer consumes more power and is larger in size but offers a more accurate output than the single sideband mixer.
The circuit 100 operates at the frequency bands (or ranges) specified by the UWB standard.
The VCO 101, the first divider 102, the first single sideband (SSB) mixer 103, second divider 104, third divider 105 collectively form a feedback clock-frequency generator 137 that generates a phase and frequency synchronized clock frequency f1121 as the output of mixer 103. In an exemplary embodiment, the clock frequency f1121 is represented by the following equations:
f1=f0/[(1+1/BC)A], or Eq. (4)
f1=f0/[(1−1/BC)A] Eq. (5)
In an exemplary embodiment, A refers to 2, B refers to 8, and C refers to 2. The value of f1 can be selected by properly choosing the SSB mixer output. Frequency f1/B is fed into a SSB mixer 106 and mixed with f1 to generate the desired frequencies f1+f1/B and f1−f1/B. The clock frequency f1/(BC) is also fed into the fourth divider 108 to generate a final output frequency that is equal to the reference frequency 132 when the loop is stable. Stable, as used herein, is defined as non-linearity experienced by a circuit. The divide ratio of divider 108 thus needs to be programmed dynamically or statically to suit this purpose. Divider 108 does not affect loop stability. To this end, the PFD 109 is a loop filter, or a special low pass filter that guards against instability by employing resistors and capacitors of values that prevent such stability. Loop filters are known to those skilled in the art.
Referring still to
In an exemplary embodiment, the circuit 100 is designed to conform to the standards of the Multi-Band Orthogonal Frequency-Division Multiplexing (OFDM) Alliance (MBOA) Ultra Wideband (UWB) system. It is understood however that the circuit 100 may operate at other frequencies. Accordingly, VCO 101 is operative to generate single clock frequency f0135. Frequency 135 is operative at a frequency of substantially 7920 MHz so as to conform to the foregoing standard. Frequency 135 is received by first divider 102. Divider 102 is operative to generate clock signal output frequency 120 at a frequency of substantially 3960 MHz. Frequency 120 is shown to be received by first single sideband (SSB) mixer 103. Mixer 103 is operative to generate the phase and frequency synchronized clock frequency f1121 at a frequency of substantially 4224 MHz. Frequency 121 is shown to be received by second divider 104. Divider 104 is operative to generate output 122 at a frequency of substantially 528 MHz. The third divider 105 is shown to receive output 122, and is operative to generate output 123 at a frequency of substantially 264 MHz.
Said exemplary embodiment of circuit 100 is further shown to include a fourth divider 108. Divider 108 receives phase and frequency synchronized clock frequency f1121 from mixer 103. Divider 108 is operative to generate final output 130 at a frequency of substantially 66 MHz. Reference frequency generator 110 is shown to generate reference frequency 132 at a frequency of substantially 66 MHz. It is understood however that clock signal output frequency 120, phase and frequency synchronized clock frequency f1121, output 122, output 123, final output 130, and reference frequency 132 may operate at other frequencies.
Also, in the exemplary embodiment of the above Eqs. (1) and (2), A refers to 2, B refers to 8, and C refers to 2. However in other embodiments, A, B, and C may equal other numbers.
The phase frequency detector (PFD) 109 is operative to compare the phase and frequency difference of outputs the fourth divider 108 and reference frequency generator 110 and to output the synchronized signal 133 used as an error signal. A low-pass filter 111 is used to filter out high frequency components. The filtered phase synchronized error signal is then used to control the frequency of VCO 101.
Referring still to
Voltage controlled oscillator (VCO) 101, first divider 102, first single sideband (SSB) mixer 103, second divider 104, third divider 105, fourth divider 108, phase frequency detector (PFD) 109, reference frequency generator 110, and low-pass filter 111 form the control loop 140 which generates a stable VCO frequency. Phase and frequency synchronized clock frequency f1121 (output of mixer 103) is shown to be received by fourth divider 108. Divider 108 is operative to generate final output 130.
The phase frequency detector (PFD) 109 is shown to receive final output 130. PFD 109 also receives reference frequency 132. Reference frequency 132 is shown to be generated by reference frequency generator 110. PFD 109 is operative to generate synchronized signal 133. In the final step of control loop 140, synchronized signal 133 is shown to be received by low-pass filter 111. Filter 111 is operative to generate a filtered phase synchronized error signal 136.
The divide ratios of 102, 104, 105 and 108 can be programmable or a fixed value, although the stated frequencies herein are desirable for the UWB application contemplated herein. The input signals of the SSB mixers 103, 106 are desirable to be quadrature signals (as illustrated by double lines) to maintain phase and frequency relationship. In addition, the second SSB mixer 106 desirably also has two outputs, each with an image frequency suppressed output due to the properties of a single sideband circuit.
The above disclosed description of clock generation circuit 100 is a dual loop system which includes two interactive loops: one for generating a stable VCO frequency, the other for generating the desired multiple clock frequency output. Since the difference of loop time constant is large in prior art designs using two or more voltage controlled oscillators, the dual loop in the present invention shows increased stability. The frequency selection switch 107 (or 107A) selects one frequency from three output frequencies, f1, (f1+f1/B) and (f1−f1/B). Since the switch circuitry has a response time that is faster than that experienced by prior art systems, the switching time from one clock frequency to the other is advantageously expedited.
Properly choosing the divide ratios A, B, C and D and the VCO frequency can generate different output frequencies with specific utility. For example, in Band-Group One of the MBOA UWB system, VCO frequency f0 can be chosen as substantially 7,920 MHz, A is chosen as 2, thus, the input frequency of mixer 103 after being divided by 2 is substantially 3,960 MHz; if B equals to 8 and C equals to 2, then, the mixer output frequency can be substantially 4,224 MHz. Choosing the reference frequency equal to substantially 66 MHz, D will be 4. Or choosing the reference frequency equal to substantially 44 MHz, D will be 6. Thus the single frequency clock source has a circuitry portion, second divider 104, in common to generate hopping frequencies for an MBOA UWB system.
Although the present invention has been described in terms of specific embodiments it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alterations and modification as fall within the true spirit and scope of the invention.
