Patent Application
20250063853
The disclosure relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures including a single-photon avalanche diode and methods of forming such structures.
A single-photon avalanche diode (SPAD) is a type of solid-state photodetector belonging to the same family as photodiodes and avalanche photodiodes. A fundamental difference between single-photon avalanche diodes and other types of photodetectors is that a single-photon avalanche diode is biased well above its reverse-bias breakdown voltage. When a single-photon avalanche diode is placed under such a high reverse bias, photon-initiated charge carriers are accelerated by the electric field to a kinetic energy that is large enough to knock electrons out of atoms of the bulk material and generate additional charge carriers that may exponentially grow to generate an avalanche of charge carriers. A single-photon avalanche diode can detect single photons providing short duration current pulses that can be counted or used to obtain a time of arrival of a particular incident single photon.
An electrical circuit including a single-photon avalanche diode tends to have a large footprint. A transistor is used to control the operation of the single-photon avalanche diode. The transistor tends to be large and consumes significant chip area. A single-photon avalanche diode may be electrically isolated from its surroundings by a deep trench isolation region. Deep trench isolation regions may also consume significant chip area.
Improved structures including a single-photon avalanche diode and methods of forming such structures are needed.
In an embodiment of the invention, a structure comprises a semiconductor substrate including a trench. The trench surrounds a portion of the semiconductor substrate. The structure further comprises a deep trench isolation region that includes a dielectric layer and a semiconductor layer inside the trench. The dielectric layer is disposed between a sidewall of the trench and the semiconductor layer. The structure further comprises an active device that includes a doped region in the semiconductor layer.
In an embodiment of the invention, a method comprises forming a trench in a semiconductor substrate and forming a deep trench isolation region that includes a dielectric layer and a semiconductor layer inside the trench. The trench surrounds a portion of the semiconductor substrate, and the dielectric layer is disposed between a sidewall of the trench and the semiconductor layer. The method further comprises forming an active device including a doped region in the semiconductor layer.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
With reference to
Shallow trench isolation regions 18, 20 may be disposed in portions of the semiconductor substrate 12. In an embodiment, the shallow trench isolation regions 18, 20 may be formed by applying and patterning a hardmask, etching trenches using the patterned hardmask, depositing a dielectric material (e.g., silicon dioxide) in the trenches, and planarizing with chemical-mechanical polishing.
A deep well 22 is disposed in a portion of the semiconductor substrate 12 and is spaced in a vertical direction from the top surface 13 of the semiconductor substrate 12. In an embodiment, the deep well 22 may be formed by introducing a dopant by, for example, a masked ion implantation into the semiconductor substrate 12. A patterned implantation mask may be formed to define a selected area (e.g., location and horizontal dimensions) on a top surface 13 of the semiconductor substrate 12 that is exposed for implantation to form the deep well 22. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the deep well 22. In an embodiment, the deep well 22 may be doped with a concentration of an n-type dopant (e.g., arsenic or phosphorus) such that the deep well 22 has n-type conductivity.
A well 24 is disposed in a portion of the semiconductor substrate 12 adjacent to the top surface 13 of the semiconductor substrate 12. In an embodiment, the well 24 may be formed in a peripheral portion of the semiconductor layer 16 and may surround a central portion of the semiconductor layer 16. A patterned implantation mask may be formed to define a selected area (e.g., location and horizontal dimensions) on the top surface 13 of the semiconductor substrate 12 that is exposed for implantation to form the well 24. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the well 24. In an embodiment, the well 24 may be formed by introducing a dopant by, for example, a masked ion implantation into the semiconductor substrate 12. In an embodiment, the well 24 may be doped with a concentration of an n-type dopant (e.g., arsenic or phosphorus) such that the well 24 has n-type conductivity. In an embodiment, the well 24 may be doped to have the same conductivity type as the deep well 22. The well 24 may contain a higher dopant concentration of the n-type dopant than the deep well 22.
A well 26 may be disposed in a central portion of the semiconductor layer 16 adjacent to the top surface 13 of the semiconductor substrate 12. In an embodiment, the well 26 may be formed by introducing a dopant by, for example, a masked ion implantation into the semiconductor substrate 12. A patterned implantation mask may be formed to define a selected area (e.g., location and horizontal dimensions) on the top surface 13 of the semiconductor substrate 12 that is exposed for implantation to form the well 26. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the well 26. In an embodiment, the well 26 may be doped with a concentration of a p-type dopant (e.g., boron) such that the well 26 has p-type conductivity.
The well 24 may adjoin a portion of the deep well 22. The deep well 22 and the well 24 may be doped to have the same conductivity type. The well 26 may also adjoin a portion of the deep well 22. The well 26 and the deep well 22 may be doped to have opposite conductivity types. The well 24 may surround the well 26, and an undoped portion of the semiconductor layer 16 may be disposed between the well 26 and the well 24. The well 24 and the well 26 are positioned in a vertical direction between the deep well 22 and the top surface 13 of the semiconductor substrate 12.
A doped region 28 may be disposed in a portion of the well 24 adjacent to the top surface 13 of the semiconductor substrate 12. In an embodiment, the doped region 28 may be formed by introducing a dopant by, for example, a masked ion implantation into the semiconductor substrate 12. A patterned implantation mask may be formed to define a selected area (e.g., location and horizontal dimensions) on the top surface 13 of the semiconductor substrate 12 that is exposed for implantation to form the doped region 28. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the doped region 28. In an embodiment, the doped region 28 may be doped with a concentration of an n-type dopant (e.g., arsenic or phosphorus) such that the doped region 28 has n-type conductivity. In an embodiment, the doped region 28 may be doped to have the same conductivity type as the well 24. The doped region 28 may contain a higher dopant concentration of the n-type dopant than the well 24.
A doped region 30 may be disposed in a central portion of the well 26 adjacent to the top surface 13 of the semiconductor substrate 12. In an embodiment, the doped region 30 may be formed by introducing a dopant by, for example, a masked ion implantation into the semiconductor substrate 12. A patterned implantation mask may be formed to define a selected area (e.g., location and horizontal dimensions) on the top surface 13 of the semiconductor substrate 12 that is exposed for implantation to form the doped region 30. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the doped region 30. In an embodiment, the doped region 30 may be doped with a concentration of a p-type dopant (e.g., boron) such that the doped region 30 has p-type conductivity. In an embodiment, the doped region 30 may be doped to have the same conductivity type as the well 24. The doped region 30 may contain a higher dopant concentration of the n-type dopant than the well 24.
The doped region 28 and the doped region 30 may define terminals of the single-photon avalanche detector. In an embodiment, the doped region 28 may define a cathode of the single-photon avalanche detector, and the doped region 30 may define an anode of the single-photon avalanche detector. An absorption/multiplication region of the single-photon avalanche diode is defined by the wells 24, 26 and deep well 22.
A trench 32 is formed in the semiconductor substrate 12 as an opening that penetrates fully through the semiconductor layer 16 and into the bulk substrate 14. The trench 32 extends through the well 24 and the deep well 22. The trench 32 may surround a portion of the semiconductor substrate 12 and, in particular, may surround respective portions of the bulk substrate 14 and the semiconductor layer 16. The trench 32 may be patterned by lithography and etching processes. To that end, an etch mask may be formed by a lithography process over the semiconductor substrate 12. The etch mask may include a layer of a light-sensitive material, such as a photoresist, applied by a spin-coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer to define an opening at the location of the subsequently-etched trench 32. An etching process is used to form the trench 32 at the location of the opening in the etch mask. In an embodiment, the trench 32 may have a width of about 0.8 microns to about 1 micron and a depth in a range of about 7 microns to about 10 microns. The etch mask may be stripped by, for example, ashing after forming the trench 32.
The trench 32 includes an inner sidewall 33 that surrounds a portion of the semiconductor substrate 12 and an outer sidewall 35 that surrounds the inner sidewall 33. The terminals of the single-photon avalanche diode are formed in the portion of the semiconductor substrate 12 that is surrounded by the inner sidewall 33. The trench 32 has a closed shape. In the representative embodiment, the trench 32 is annular with circular sidewalls 33, 35. In an alternative embodiment, the trench 32 may have a different shape, such as a shape with polygonal sidewalls 33, 35.
With reference to
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The dielectric layer 34 and semiconductor layer 36 that are positioned inside the trench 32 collectively define a deep trench isolation region 38. The dielectric layer 34 electrically isolates the semiconductor layer 36 from the portion of the semiconductor substrate 12 that is surrounded by the deep trench isolation region 38. In an embodiment, the deep trench isolation region 38 may be included in a grid of deep trench isolation regions 38 in which each grid square includes a single-photon avalanche diode.
With reference to
The source/drain regions 42, 44 of the transistor 45 may be doped regions that are formed in the semiconductor layer 36 by, for example, a masked ion implantation. The source/drain regions 42, 44 may be doped with a concentration of a dopant, such as an n-type dopant (e.g., arsenic or phosphorus) that provides n-type conductivity. Alternatively, source/drain regions 42, 44 may be doped with a concentration of a p-type dopant (e.g., boron) that provides p-type conductivity. As used herein, the term “source/drain region” means a doped region of semiconductor material that can function as either a source or a drain of a field-effect transistor. In an embodiment, the source/drain region 42 may represent the drain of the transistor 45, and the source/drain region 44 may represent the source of the transistor 45. The doped regions representing the source/drain regions 42, 44 may be coextensive with the top surface 39 of the semiconductor layer 36. The doped regions representing the source/drain regions 42, 44 may extend from the top surface 39 of the semiconductor layer 36 to a depth D in the semiconductor layer 36 that is shallower than the depth of the doped regions 28, 30. The trench 32 extends to a depth in the semiconductor substrate 12 that is greater than the depth D.
In an embodiment, the gate 40 and source/drain regions 42, 44 of the transistor 45 in the semiconductor layer 36 of the deep trench isolation region 38 may fully surround the perimeter of the single-photon avalanche detector. In an alternative embodiment, the gate 40 and source/drain regions 42, 44 may be divided such that multiple transistors 45 are disposed in the semiconductor layer 36 of the deep trench isolation region 38 about the perimeter of the single-photon avalanche detector.
Other types of active devices may be formed in addition to the transistor 45 or instead of the transistor 45. As used herein, an active device is a circuit component with the ability to electrically control charge flow through the circuit component under either voltage control or current control. An active device is distinguishable over a passive device, such as a resistor. In an exemplary alternative embodiment, a silicon-controlled rectifier may be formed as an active device that includes multiple doped regions in the semiconductor layer 36.
With reference to
A wire 50 is formed defining a metal feature in the dielectric layer 48, and the wire 50 may be physically and electrically connected by metal features 51 of the metallization levels to the doped region 28 of the single-photon avalanche detector. A wire 52 is formed defining a metal feature in the dielectric layer 48, and the wire 52 may be physically and electrically connected by metal features 53 in the metallization levels to the source/drain region 42 of the transistor 45. The wire 52 is also physically and electrically connected by metal features 55 in the metallization levels to the doped region 30 of the single-photon avalanche detector such that the wire 52 is configured to connect the source/drain region 42 of the transistor 46 to the doped region 30 of the single-photon avalanche diode. The metal features 51, 53, 55 may include vias, contacts, and wires that are formed in the dielectric layers 46, 48. The source/drain region 44 of the transistor 45 and the gate 40 of the transistor 45 may also be connected to metal features (not shown) in the metallization levels. For the example, the source/drain region 44 of the transistor 45 may be coupled by the metal features to ground, and the gate 40 of the transistor 45 may be coupled to a control voltage.
The structure 10 may be replicated to provide multiple instances of the single-photon avalanche diode and transistor 45, and these instances of the single-photon avalanche diode and transistor 45 may be arranged as pixels in a pixel array to define, for example, an image sensor. The image sensor may be used in mobile phones, digital cameras, and other types of devices.
In use, the p-n junction between the deep well 22 and the well 26 may be reverse-biased above the breakdown voltage. The single-photon avalanche diode is illuminated by light, and incident photons are absorbed in the portions of the semiconductor layer 16 interior of the deep trench isolation region 38. When an incident photon is absorbed, an electron-hole pair is created. An avalanche current is generated under the reverse bias by the creation of additional electron-hole pairs through impact ionization with atoms of the semiconductor material. The current continues to be generated until the avalanche is quenched by lowering the bias to less than or equal to the breakdown voltage. The collected current provides a detectable electronic signal. To be able to detect another photon, the reverse bias is raised again above breakdown voltage to recharge the single-photon avalanche diode.
The structure 10 utilizes the semiconductor layer 36 of the deep trench isolation region 38 to provide functionality through the integration of an active device. The structure 10 may be more compact and have a smaller form factor than traditional structures because the representative active device, namely the transistor 45, is integrated into the semiconductor layer 36 of the deep trench isolation region 38. The dielectric layer 34 of the deep trench isolation region 38 supplies electrical isolation for the surrounded single-photon avalanche diode relative to adjacent single-photon avalanche diodes. The transistor 45 may be used to control the operation of the single-photon avalanche diode. For example, the transistor 45 may be used to control the quenching of the single-photon avalanche diode and to control the recharging of the single-photon avalanche diode.
With reference to
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s).
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features may “overlap” if a feature extends over, and covers a part of, another feature.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
