Claims
- 1. A method of correcting symbol errors in a data word, comprising:generating a symbol error correction code according to an H-matrix comprising a plurality of subsets arranged in a plurality of rows and columns, wherein each of at least one row of said plurality of rows comprises, in part, multiple iterations of one subset of said plurality of subsets, and a remainder of said plurality of rows comprises, in part, a cyclic permutation of all remaining subsets of said plurality of subsets; and detecting symbol errors in the data word according to said symbol error correction code, wherein the detecting further comprises detecting multiple symbol errors in the data word using the symbol error correction code.
- 2. The method of claim 1, wherein said generating further comprises:generating a plurality of check bits associated with the data word according to the H-matrix; and generating a syndrome according to the H-matrix, said syndrome being associated with the data word and comprising a plurality of syndrome bits.
- 3. The method of claim 2, wherein each check bit of said plurality of check bits is generated by performing an exclusive OR function or exclusive NOR function on a distinct group of bits of said data word selected according to said H-matrix.
- 4. The method of claim 3, wherein said syndrome bits are generated by performing an exclusive OR function or exclusive NOR function on each said check bit and said distinct group of bits of said data word used to generate said particular check bit.
- 5. The method of claim 2, wherein each syndrome bit of said syndrome corresponds to a distinct check bit.
- 6. The method of claim 2, wherein said detecting comprises decoding said syndrome to detect any errors in the data word.
- 7. The method of claim 6, wherein each syndrome bit comprises an error state and an error-free state, and said decoding further comprises:indicating no error if each syndrome bit is in its error-free state.
- 8. The method of claim 7, further comprising:comparing, if any of said syndrome bits is in its error state, said syndrome with a syndrome decoder table generated according to the H-matrix to detect any single symbol errors, any double symbol errors, and multiple symbol errors in the data word.
- 9. The method of claim 8, wherein said syndrome decoder table comprises a plurality of columns, each column of said plurality of columns corresponding to a symbol of the data word and comprising three sub-columns, said first sub-column corresponding to a first bit of said symbol, said second sub-column corresponding to a second bit of said symbol, and said third sub-column being the result of an exclusive OR function performed on said first and said second sub-columns of said symbol, said comparing further comprising:comparing said syndrome with said first, second, and third sub-column of each column of said syndrome decoder table, wherein said first bit of said symbol is indicated as being erroneous if said syndrome is equal to the first sub-column, said second bit of said symbol is indicated as being erroneous if said syndrome is equal to the second sub-column, both bits of said symbol are indicated as being erroneous if said syndrome is equal to the third sub-column, and an uncorrectable error is indicated, signifying multiple symbol error, if no matches are made between said syndrome and any of the sub-columns of any of the columns.
- 10. The method of claim 1, wherein said error correction code is used in a computer system for single symbol error correction as well as said multiple symbol error detection.
- 11. The method of claim 1, wherein said data word comprises a plurality of two bit symbols.
- 12. The method of claim 1 further comprising:correcting any single symbol errors; and generating an uncorrectable error signal if a multiple symbol error is detected.
- 13. The method of claim 12, where said correcting comprises performing an XOR operation on a single bit or all bits in said single symbol.
- 14. The method of claim 1, wherein said plurality of subsets comprises n subsets, wherein 3≦n≦6.
- 15. The method of claim 1, wherein said one subset of said plurality of subsets comprises: M0=[0000000000101010101010101000000000000101010101010101]; andsaid remaining subsets of said plurality of subsets comprises: M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];andM5=[1010010010000000001001111101011100010000000001111010].
- 16. The method of claim 1, wherein said H-matrix is: H=[M0M0M0M0M0V0V0 M1M5M4M3M2V0V0 M2M1M5M4M3V0V1 I12M3M2M1M5M4V0V1 M4M3M2M1M5V1V0 M5M4M3M2M1V1V0 ].
- 17. The method of claim 16, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111];andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 18. The method of claim 1 wherein, said H-matrix is: H=[M0V0M0V0M0V0M0V0M0V0 M1V0M5V1M4V1M3V0M2V0 M2V0M1V0M5V1M4V1M3V0 I12M3V0M2V0M1V0M5V1M4V1 M4V1M3V0M2V0M1V0M5V1 M5V1M4V1M3V0M2V0M1V0 ].
- 19. The method of claim 18, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111];andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 20. The method of claim 1 wherein said H-matrix is: H=[M0V0V0M0V0V0M0V0V0M0V0V0M0V0V0 M1V0V0M5V1V2M4V1V2M3V0V0M2V0V1 M2V0V1M1V0V0M5V1V2M4V1V2M3V0V0 I12M3V0V0M2V0V1M1V0V0M5V1V2M4V1V2 M4V1V2M3V0V0M2V0V1M1V0V0M5V1V2 M5V1V2M4V1V2M3V0V0M2V0V1M1V0V0 ].
- 21. The method of claim 20, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111];V2=[1110];andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 22. The method of claim 1, wherein any row of said plurality of rows is interchangeable with any other row of said plurality of rows.
- 23. The method of claim 1, wherein any column of said plurality of columns is interchangeable with any other column of said plurality of columns.
- 24. A system of correcting symbol errors in a data word, comprising:means for generating a symbol error correction code according to an H-matrix comprising a plurality of subsets arranged in a plurality of rows and columns, wherein each of at least one row of said plurality of rows comprises, in part, multiple iterations of one subset of said plurality of subsets, and a remainder of said plurality of rows comprises, in part, a cyclic permutation of all remaining subsets of said plurality of subsets; and means for detecting symbol errors in the data word according to said symbol error correction code, wherein the means for detecting further comprises means for detecting multiple symbol errors in the data word using the symbol error correction code.
- 25. The system of claim 24, wherein said means for generating further comprises:means for generating a plurality of check bits associated with the data word according to the H-matrix; and means for generating a syndrome according to the H-matrix, said syndrome being associated with the data word and comprising a plurality of syndrome bits.
- 26. The system of claim 25, wherein each check bit of said plurality of check bits is generated by performing an exclusive OR function or exclusive NOR function on a distinct group of bits of said data word selected according to said H-matrix.
- 27. The system of claim 26, wherein said syndrome bits are generated by performing an exclusive OR function or exclusive NOR function on each said check bit and said distinct group of bits of said data word used to generate said particular check bit.
- 28. The system of claim 25, wherein each syndrome bit of said syndrome corresponds to a distinct check bit.
- 29. The system of claim 25, wherein said means for detecting comprises means for decoding said syndrome to detect any errors in the data word.
- 30. The system of claim 29, wherein each syndrome bit comprises an error state and an error-free state, and said means for decoding further comprises:means for indicating no error if each syndrome bit is in its error-free state.
- 31. The system of claim 30, further comprising:means for comparing, if any of said syndrome bits is in its error state, said syndrome with a syndrome decoder table generated according to the H-matrix to detect any single symbol errors, any double symbol errors, and multiple symbol errors in the data word.
- 32. The system of claim 31, wherein said syndrome decoder table comprises a plurality of columns, each column of said plurality of columns corresponding to a symbol of the data word and comprising three sub-columns, said first sub-column corresponding to a first bit of said symbol, said second sub-column corresponding to a second bit of said symbol, and said third sub-column being the result of an exclusive OR function performed on said first and said second sub-columns of said symbol, said means for comparing further comprising:means for comparing said syndrome with said first, second, and third sub-column of each column of said syndrome decoder table, wherein said first bit of said symbol is indicated as being erroneous if said syndrome is equal to the first sub-column, said second bit of said symbol is indicated as being erroneous if said syndrome is equal to the second sub-column, both bits of said symbol are indicated as being erroneous if said syndrome is equal to the third sub-column, and an uncorrectable error is indicated, signifying multiple symbol error, if no matches are made between said syndrome and any of the sub-columns of any of the columns.
- 33. The system of claim 24, wherein said error correction code is used in a computer system for single symbol error correction as well as said multiple symbol error detection.
- 34. The system of claim 24, wherein said data word comprises a plurality of two bit symbols.
- 35. The system of claim 24 further comprising:means for correcting any single symbol errors; and means for generating an uncorrectable error signal if a multiple symbol error is detected.
- 36. The system of claim 35, where said means for correcting comprises means for performing an XOR operation on a single bit or all bits in said single symbol.
- 37. The system of claim 24,wherein said plurality of subsets comprises n subsets, wherein 3≦n≦6.
- 38. The system of claim 24, wherein said one subset of said plurality of subsets comprises: M0=[0000000000101010101010101000000000000101010101010101];andsaid remaining subsets of said plurality of subsets comprises: M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];andM5=[1010010010000000001001111101011100010000000001111010].
- 39. The system of claim 24, wherein said H-matrix is: H=[M0M0M0M0M0V0V0 M1M5M4M3M2V0V0 M2M1M5M4M3V0V1 I12M3M2M1M5M4V0V1 M4M3M2M1M5V1V0 M5M4M3M2M1V1V0 ].
- 40. The system of claim 39, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111];andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 41. The system of claim 24 wherein, said H-matrix is: H=[M0V0M0V0M0V0M0V0M0V0 M1V0M5V1M4V1M3V0M2V0 M2V0M1V0M5V1M4V1M3V0 I12M3V0M2V0M1V0M5V1M4V1 M4V1M3V0M2V0M1V0M5V1 M5V1M4V1M3V0M2V0M1V0 ].
- 42. The system of claim 41, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111];andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 43. The system of claim 24 wherein said H-matrix is: H=[M0V0V0M0V0V0M0V0V0M0V0V0M0V0V0 M1V0V0M5V1V2M4V1V2M3V0V0M2V0V1 M2V0V1M1V0V0M5V1V2M4V1V2M3V0V0 I12M3V0V0M2V0V1M1V0V0M5V1V2M4V1V2 M4V1V2M3V0V0M2V0V1M1V0V0M5V1V2 M5V1V2M4V1V2M3V0V0M2V0V1M1V0V0 ].
- 44. The system of claim 43, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111];V2=[1110];andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 45. The system of claim 24, wherein any row of said plurality of rows is interchangeable with any other row of said plurality of rows.
- 46. The system of claim 24, wherein any column of said plurality of columns is interchangeable with any other column of said plurality of columns.
- 47. An article of manufacture comprising:a computer useable medium having computer readable program code means embodied therein for causing the correcting of symbol errors in a data word, the computer readable program code means in said article of manufacture comprising: computer readable program code means for causing a computer to effect generating a symbol error correction code according to an H-matrix comprising a plurality of subsets arranged in a plurality of rows and columns, wherein each of at least one of said plurality of rows comprises, in part, multiple iterations of one subset of said plurality of subsets, and a remainder of said plurality of rows comprises, in part, a cyclic permutation of all remaining subsets of said plurality of subsets; and computer readable program code means for causing a computer to effect detecting symbol errors in the data word according to said symbol error correction code, wherein the detecting further comprises detecting multiple symbol errors in the data word using the symbol error correction code.
- 48. The article of manufacture of claim 47, wherein said computer readable program code means for causing a computer to effect generating further comprises:computer readable program code means for causing a computer to generate a plurality of check bits associated with the data word according to the H-matrix; and computer readable program code means for causing a computer to generate a syndrome according to the H-matrix, said syndrome being associated with the data word and comprising a plurality of syndrome bits.
- 49. The article of manufacture claim 48, wherein each check bit of said plurality of check bits is generated by performing an exclusive OR function or exclusive NOR function on a distinct group of bits of said data word selected according to said H-matrix.
- 50. The article of manufacture claim 49, wherein said syndrome bits are generated by performing an exclusive OR function or exclusive NOR function on each said check bit and said distinct group of bits of said data word used to generate said particular check bit.
- 51. The article of manufacture claim 48, wherein each syndrome bit of said syndrome corresponds to a distinct check bit.
- 52. The article of manufacture claim 48, wherein said computer readable program code means for causing a computer to detect comprises decoding said syndrome to detect any errors in the data word.
- 53. The article of manufacture claim 52, wherein each syndrome bit comprises an error state and an error-free state, and said computer readable program code means for causing a computer to decode further comprises:computer readable program code means for causing a computer to indicate no error if each syndrome bit is in its error-free state.
- 54. The article of manufacture of claim 53, further comprising:computer readable program code means for causing a computer to compare, if any of said syndrome bits is in its error state, said syndrome with a syndrome decoder table generated according to the H-matrix to detect any single symbol errors, any double symbol errors, and multiple symbol errors in the data word.
- 55. The article of manufacture of claim 54, wherein said syndrome decoder table comprises a plurality of columns, each column of said plurality of columns corresponding to a symbol of the data word and comprising three sub-columns, said first sub-column corresponding to a first bit of said symbol, said second sub-column corresponding to a second bit of said symbol, and said third sub-column being the result of an exclusive OR function performed on said first and said second sub-columns of said symbol, said computer readable program code means for causing a computer to compare further comprising:computer readable program code means for causing a computer to compare said syndrome with said first, second, and third sub-column of each column of said syndrome decoder table, wherein said first bit of said symbol is indicated as being erroneous if said syndrome is equal to the first sub-column, said second bit of said symbol is indicated as being erroneous if said syndrome is equal to the second sub-column, both bits of said symbol are indicated as being erroneous if said syndrome is equal to the third sub-column, and an uncorrectable error is indicated, signifying multiple symbol error, if no matches are made between said syndrome and any of the sub-columns of any of the columns.
- 56. The article of manufacture of claim 47, wherein said error correction code is used in a computer system for single symbol error correction as well as the multiple symbol error detection.
- 57. The article of manufacture of claim 47, wherein said data word comprises a plurality of two bit symbols.
- 58. The article of manufacture of claim 47, further comprising:computer readable program code means for causing a computer to correct any single symbol errors; and computer readable-program code means for causing a computer to generate an uncorrectable error signal if a multiple symbol error is detected.
- 59. The article of manufacture of claim 58, wherein said computer readable program code means for causing a computer to correct comprises computer readable program code means for causing a computer to perform an XOR operation on a single bit or all bits in said single symbol.
- 60. The article of manufacture of claim 47,wherein said plurality of subsets comprises n subsets, wherein 3≦n≦6.
- 61. The article of manufacture of claim 47, wherein said one subset of said plurality of subsets comprises: M0=[0000000000101010101010101000000000000101010101010101];andsaid remaining subsets of said plurality of subsets comprises: M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];andM5=[1010010010000000001001111101011100010000000001111010].
- 62. The article of manufacture of claim 47, wherein said H-matrix is: H=[M0M0M0M0M0V0V0 M1M5M4M3M2V0V0 M2M1M5M4M3V0V1I12M3M2M1M5M4V0V1 M4M3M2M1M5V1V0 M5M4M3M2M1V1V0 ].
- 63. The article of manufacture of claim 62, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111]; andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 64. The article of manufacture of claim 47 wherein, said H-matrix is: H=[M0V0M0V0M0V0M0V0M0V0 M1V0M5V1M4V1M3V0M2V0 M2V0M1V0M5V1M4V1M3V0I12M3V0M2V0M1V0M5V1M4V1 M4V1M3V0M2V0M1V0M5V1 M5V1M4V1M3V0M2V0M1V0 ].
- 65. The article of manufacture of claim 64, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1=[0111]; andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 66. The article of manufacture of claim 47, wherein said H-matrix is: H=[M0V0V0M0V0V0M0V0V0M0V0V0M0V0V0 M1V0V0M5V1V2M4V1V2M3V0V0M2V0V1 M2V0V1M1V0V0M5V1V2M4V1V2M3V0V0I12M3V0V0M2V0V1M1V0V0M5V1V2M4V1V2 M4V1V2M3V0V0M2V0V1M1V0V0M5V1V2 M5V1V2M4V1V2M3V0V0M2V0V1M1V0V0 ].
- 67. The article of manufacture of claim 66, wherein: M0=[0000000000101010101010101000000000000101010101010101];M1=[0010111101000010010011010000011010110000011100101100];M2=[0000000110101100000110101100000011010110000011010110];M3=[1010001010100011100000001001010001010100100100000001];M4=[1000100010001000111110101001000100010001001010010101];M5=[1010010010000000001001111101011100010000000001111010];V0=[1001];V1[0111];V2=[1110]; andI12=[100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001000000000000100000000000010000000000001].
- 68. The article of manufacture of claim 47, wherein any row of said plurality of rows is interchangeable with any other row of said plurality of rows.
- 69. The article of manufacture of claim 47, wherein any column of said plurality of columns is interchangeable with any other column of said plurality of columns.
- 70. A system of correcting symbol errors in a data word, comprising:a symbol error correction code generating device adapted to generate a symbol error correction code according to an H-matrix comprising a plurality of subsets arranged in a plurality of rows and columns, wherein each of at least one row of said plurality of rows comprises, in part, multiple iterations of one subset of said plurality of subsets, and a remainder of said plurality of rows comprises, in part, a cyclic permutation of all remaining subsets of said plurality of subsets; and a symbol error detecting device adapted to detect symbol errors in the data word according to said symbol error correction code, wherein the symbol error detecting device is further adapted to detect multiple symbol errors in the data word using the symbol error correction code.
CROSS-REFERENCES TO RELATED APPLICATIONS
This application contains subject matter which is related to the subject matter of the following applications, each of which is assigned to the same assignee as this application and filed on the same day as this application. Each of the below listed applications is hereby incorporated herein by reference in its entirety:
“Detecting Address Faults In An ECC-Protected Memory,” Chen et al., Ser. No. 09/451,261; “Generating Special Uncorrectable Error Codes For Failure Isolation,” Chen et al., Ser. No. 09/452,079; and “Method, System And Program Products For Error Correction Code Conversion,” Chen et al., Ser. No. 09/450,548.
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