Patent Application
20070288875
According to the present invention, techniques are provided which assist in the design process of digital circuits through the visualization of skew clock trees. In some embodiments, a user (e.g., a circuit designer) of a computer system selects timing analysis data (from sources such as a placed gate netlist, DEF/PDEF, SDC, lib, or LEF file) for a digital circuit. The computer system acts upon the timing analysis data to determine one or more clock roots of the digital circuit. The computer system identifies the various components connected between the one or more clock roots and one or more clock sinks associated with each of the one or more clock roots. The computer system then determines an insertion delay or propagation time delay between the one or more clock roots and the one or more clock sinks associated with each of the one or more clock roots of the digital circuit. The computer system then generates corresponding graphical representations of skew clock trees of the one or more clock roots of the digital circuit for display to the circuit designer.
The computer system can determine the insertion delay or propagation time delay between a clock root and a circuit component or clock node. The computer system then determines the propagation delay from the circuit component to a clock sink. If there are a plurality of circuit components or clock nodes between a clock root and a clock sink, the computer system determines the corresponding propagation time delays (such as from a clock root to a component, and from the component to a clock sink) and generates graphical representations in the skew clock tree for display to the circuit designer.
Advantageously, the circuit designer can quickly determine from the skew clock tree visualization generated by the computer system a key figure-of-merit about the clock tree of the digital circuit. Namely, whether one or more clock trees in the digital circuit are balanced or not. A clock tree is balanced if the insertion delay or propagation time delay from a clock root, through various components or nodes, and to each clock sink is the same to within some tolerance or threshold.
The circuit designer can visually determine the insertion delay or propagation time delay for a clock sink, a circuit component, or group of clock sinks or circuit components. The circuit designer can also readily identify skew groups (e.g., groups of cells or components balanced with respect to one another, but not to the rest of the cells or components), and cells or components of the digital circuits that are given special clock signal treatment. Additionally, the designer can determine whether any circuit components along the clock tree are overloaded because there would be a large time delay between two components along a branch of the clock tree. Such large time delays can easily be identified since they would appear as large vertical gaps in the clock tree representation.
The computer system 400 may be programmed with computer programs stored on the storage 450 to perform various tasks. These tasks might involve accepting user input, and/or displaying images or text via the display interface 430. The processor 410 interprets input signals provided on the bus 460. The processor 410 uses the memory 420 (e.g., RAM or random access memory) for storage of program variables as needed. The bus 460 also provides a path for the processor 410 to send output signals to a monitor via the display interface 410. If used, the computer system 400 can communicate over a network (not shown) with a communications interface (e.g., a network interface card or modem).
In general, the timing analysis data is produced from a static timing analyzer using a combination of information sources. In one example, the timing analysis data is determined for one or more components of a digital circuit from a vendor component library that describes the one or more components. A vendor component library typically includes Synopsys' Non-Linear Delay Model (NLDM), Cadence's Effective Current Source Model (ECSM), Synopsys' Composite Current Source (CCS) model, and the like. In another example, the timing analysis data includes a static delay of a clock signal between different components of the digital circuit.
In one example, the timing analysis data is determined from placed gates information. The placed gates information may include the positions of cells in the digital circuit design and the interconnections between the cells. The timing analysis data may optionally be determined from routing information. Additionally, the computer system 400 may generate example routes based on the timing analysis data to determine representative delay and capacitance information of the digital circuit.
In this example, the timing analysis data is determined from a DEF file for cell placement and routing information and a Verilog netlist for the interconnections. The DEF file lists cells in the digital circuit design together with X and Y coordinates of the cells. If routing information is supplied, the DEF file includes a list of polygons that represent rectangles of metal in the digital circuit design. The Verilog netlist includes a series of hierarchical module declarations, and declares wires, cells, and the interconnection between the wires and cells in the digital circuit design. The timing analysis data may also be determined from information in a PDEF file for cell placement or in a DEF file for cell interconnections.
In step 520, the processor 410 selects a clock root of the digital circuit. In step 530, the processor 410 selects a clock sink, or circuit component or clock node. As discussed above, there may be a number of circuit components or clock nodes between the clock root and the clock sink. In step 540, the processor 410 determines an insertion delay or propagation time delay between the clock root and the clock sink or circuit component of the digital circuit based on the timing analysis data. The insertion delay or propagation time delay is the delay of the clock signal from the clock root through any gates, circuit components, or clock nodes (e.g., clock buffers) of the digital circuit to the clock sink. “Clock sink” as used in this disclosure refers to the clock input of a circuit components, such as a latch. In step 550, the processor 410 determines whether any other clock sinks or circuit components attached to the clock root remain from the timing analysis data.
If one or more clock sinks or circuit components remain; the processor 410 continues processing in step 530. In no clock sinks or circuit components remain, the processor 410 continues in step 560. In step 560, the processor 410 determines whether any other clock roots of the digital circuit remain from the timing analysis data. If one or more clock roots remain, the processor 410 continues processing the one or more clock roots in step 520. If no clock roots remain, the processor 410 continues in step 570.
In step 570, the processor 410 generates a skew clock tree visualization based on any clock roots and the insertion delay or propagation delay between the clock roots and the any clock sinks or circuit components associated with a clock root. Each clock sink's position along the clock tree is determined and then displayed based on its insertion delay. In step 560, the processor 410 displays the skew clock tree to the circuit designer.
Advantageously, the circuit designer can readily determine whether the clock tree 600 is balanced. In this example, most of the clock sinks have an insertion delay from the clock root of about 360 ps. There are only a few tens of picoseconds between the highest insertion delay and the lowest insertion delay, with the exception of the insertion delay of one clock sink at 200 ps. In this example, the circuit designer may have singled out this clock sink for special treatment or otherwise overlooked the clock sink during the design process.
The skew clock tree 600 also allows the circuit designer to readily determine skew groups which are sets of clock sinks that are balanced with respect to each other, but not to the rest of the components of the digital circuit. Further, the designer can easily identify larger than normal time delays since such large delays would appear as large vertical gaps in the clock tree representation. This information can be used to further improve the performance of the clock tree.
In this example, the delay between input 1150 and the clock root 1130 can be determined, for example, by static timing analysis. The delay determines the length of the dotted line segment 1140 in the skew clock tree visualization 1100. Advantageously, the digital circuit designer can readily determine that the clock sinks of the generated child clock tree 1120 are balanced with respect to the clock sinks of the parent clock tree 1110.
One reason for clock tree reconvergence is that the digital circuit designer may want to optionally invert the clock tree. The circuit designer multiplexes a clock signal and the inverse of the clock signal together, which creates a reconvergence point. Other examples are testing the chip after manufacture.
In this example, the dotted line segment from clock sink 1220 leads back into the main clock tree 1210 at node 1230. When the processor 410 determines a reconvergence point, the processor 410 breaks the reconvergence by declaring one path to be real (e.g. clock tree 1210), and the other to just end in a sink 1220. The sink 1220 then has a dotted line back to the main body of the clock tree 1210.
Advantageously, the digital circuit designs displayed by the processor 410 may include clock reconvergence and generated clocks, which can be displayed in a skew clock tree representation to assist the circuit designer in the design process.
Many variations of the invention are possible. For example, the actual gates (e.g., clocked mux, inverter, etc.) can be displayed in the clock tree representation rather than boxes and triangles representing the same. The various gates can be colored based on the type of gate (e.g., all inverters may be displayed with one color and all clocked multiplexers may be a displayed with a different color, and so on). The clock sinks can be colored in accordance with their insertion delay (e.g., the sinks in
The present invention can be implemented in the form of control logic in software or hardware or a combination of both. The control logic may be stored in an information storage medium as a plurality of instructions adapted to direct an information-processing device to perform a set of steps disclosed in embodiments of the present invention. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate other ways and/or methods to implement the present invention.
The above description is illustrative but not restrictive. Many variations of the invention will become apparent to those skilled in the art upon review of the disclosure. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the pending claims along with their full scope or equivalents.
