This application claims the benefit of a French Patent Application No. 06-54670, filed on Oct. 31, 2006, the disclosure of which is incorporated herein in its entirety by reference.
This invention is located in the field of “Silicon Nanophotonics” (the field of guiding light in guides of nanometric dimensions), and relates primarily to optical interconnections on silicon chips and in particular the production of photonic logic gates.
Highly integrated optical functions can be produced on silicon. In a general approach, transmitters are used (integrated or added on, and electrically controlled), which are coupled with a set of guides which perform an optical function, either passively, or in response to an electrical command. These guides terminate at photodetectors which deliver the result of the optical function electrically.
The operation of a slotted guide implements propagation in a low-index medium and an index discontinuity which enables excellent containment of the light. This architecture has thus far enabled:
In this structure, the optical field is increased and contained in the slot, both geometrically and optically, all the more so as the slot is narrow and the refractive index contrast is high.
In order to integrate this material into the slotted guide, a manufacturing method is generally implemented as shown in
However, no attempt at filling has thus far been concluded, in so far as a low deposition (for example by PECVD) temperature does not allow the slot 3 to be filled. This problem is introduced in particular for a shape factor (equivalent to the ratio of the height h to the width l of the slot) greater than 1.5. This manifests itself by the formation of a bubble 10 in the slot 3, degrading the performance of the guide, as shown in
Sometimes, it is impossible to fill the slot. In this case, there is not only a bubble associated with a filling defect, but a filling defect.
For example, the following various PECVD depositions were tested: SiO2 (with a SiH4 source) at 480° C. and 350° C., SiO2 (TEOS, tetraethyl orthosilicate) at 400° C. and 350° C. and SiOx (with a SiH4/N2O source) at 400° C.
As can be observed in
The invention proposes an alternative manufacturing method which makes it possible to avoid the difficult step of filling the slot.
The invention relates first of all to a method of producing a slotted guide, in which:
A material having a refractive index less than that of silicon can be silicon dioxide SiO2, or silicon nitride SiN, or non-stoichiometric SiOx (x<2).
In the case of non-stoichiometric SiOx (x<2), a method according to the invention may further comprise:
The invention enables an alternative horizontal-type structure to be produced (the guide layer is arranged parallel to a substrate), for which the polarisation changes, but the light containment properties remain unchanged.
The thickness of the silica layer SiO2 forming the etching barrier layer is preferably greater than 1 μm for the purpose of preventing interference with the circuit situated below.
The silica layer can be formed by deposition on the silicon substrate, by oxygen implantation through the first silicon layer followed by annealing, or by thermal oxidation of a silicon plate.
The silica layer and the first silicon layer can be the oxide layer and the surface layer of a SOI-type substrate, respectively.
A cap for the slotted guide obtained can be made of a SiO2 layer.
The second silicon layer can be produced in amorphous form.
The layer of material having a refractive index less than that of silicon can be formed on the first silicon layer via PECVD or LPCVD.
A first manufacturing method according to the invention will be described in connection with
In a first step, (
A silicon layer 24 is then deposited or formed on the oxide layer 22. This layer 24, as well as the layers mentioned below, can be formed via PECVD or LPCVD.
According to the invention, it is thus possible to deposit the silicon 24 in amorphous form (PECVD deposition), using a standard silicon plate 20, having undergone a deposition 22 of silica or a thermal oxidation. The thickness of this oxide 22, preferably greater than 1 μm, is such that the losses induced by coupling with the substrate or with the CMOS circuit situated beneath the SiO2 are prevented.
A layer 26 of material having a refractive index less than that of silicon (for example silicon dioxide SiO2, or silicon nitride SiN, or non-stoichiometric SiOx (x<2)) is then formed or deposited, via PECVD or LPCVD, on the silicon layer 24 (
A second deposition (
A lithographic and etching step for all of the layers 24-26-28 (
Silicon layer 24 is either made in amorphous silicon (via PECVD), either in monocristalline silicon: in the last case, one starts from a stack of a silicon dioxide layer and a silicon layer, e.g. a SOI wafer.
It is also possible to produce a stack from a SOI plate having an embedded silicon layer 22, of a thickness, for example, greater than 1 μm and a desired silicon thickness 24. The deposition 26 of material having a refractive index less than that of silicon is then carried out, then the second silicon deposition 28 can be carried out in amorphous form (by means of PECVD). With amorphous silicon, there are few optical losses. The guide is then formed by lithography and etching.
Lithographic and etching steps for all of the layers 24-26-28, using a hard mask, will be detailed more specifically in connection with
For example, a hard mask layer 40, e.g., made of silica, is formed (
A resin 42 is then deposited (
The hard mask 40 is then etched, and the resin 42 eliminated (
The layers 24, 26, 28 can then be etched (
This embodiment of
When the of material having a refractive index less than that of silicon is non-stoichiometric SiOx (x<2) an annealing step of the SiOx in order to form silicon nanocrystals can be carried out after the SiOx deposition and prior to the second silicon deposition 28, or after this second silicon deposition 28 and prior to etching the guide, or after etching the guide.
But, if the non-stoichiometric SiOx is deposited via PECVD, its thickness diminishes during annealing. In this case, it is preferable to insert the annealing step immediately after the non-stoichiometric SiOx deposition and prior to the second silicon deposition 28. Otherwise, line defects may appear between the non-stoichiometric SiOx and the Si. Furthermore, annealing has the effect of increasing the optical losses of the silicon layer.
Once the guide has been formed and etched, a SiO2 cap 30 can be made (
A device according to the invention has a slotted guide structure, made on a layer of silicon 22, or else in a plane parallel to the plane 21 of the substrate 20. The slot and its layer 26 of material having a refractive index less than that of silicon are thus contained between two layers of silicon 24, 28, the entire assembly resting on the silica barrier layer 22. This structure makes it possible to form the material of the slot before one of the silicon walls 24 of the guide. The production techniques involving the filling of a slot between two already formed silicon layers are thereby avoided, and thus the aforementioned bubble formation problems.
The invention is particularly advantageous for a shape factor (equivalent to the ratio of the length L to the thickness e of the slot,
The invention applies in particular to the field of optical interconnections, intra-chip optical interconnections, and optical telecommunications.
Number | Date | Country | Kind |
---|---|---|---|
06 54670 | Oct 2006 | FR | national |