This application claims the benefit of a French Patent Application No. 06-54669, filed on Oct. 31, 2006, the disclosure of which is incorporated herein in its entirety by reference.
This invention is located in the field of “Silicon Nanophotonics” (the field of guiding light in guides of nanometric dimensions), and relates primarily to optical interconnections on silicon chips and in particular the production of photonic logic gates.
Highly integrated optical functions can be produced on silicon. In a general approach, transmitters are used (integrated or added on, and electrically controlled), which are coupled with a set of guides which perform an optical function, either passively, or in response to an electrical command. These guides terminate at photodetectors which deliver the result of the optical function electrically.
The operation of a slotted guide implements propagation in a low-index medium and an index discontinuity which enables excellent containment of the light. This architecture has thus far enabled:
In this structure, the optical field is increased and contained in the slot, both geometrically and optically, all the more so as the slot is narrow and the refractive index contrast is high.
In order to integrate this material into the slotted guide, a manufacturing method is generated as shown in
However, no attempt at filling has thus far been concluded, in so far as a low PECVD deposition temperature does not allow the slot 3 to be filled. This problem exists in particular for a shape factor (equivalent to the ratio of the height h to the width 1 of the slot, see
Sometimes, it is impossible to fill the slot. In this case, there is not only a bubble associated with a filling defect, but a filling defect.
For example, the following various PECVD depositions were tested: SiO2 (with a SiH4 source) at 480° C. and 350° C., SiO2 (TEOS, tetraethyl orthosilicate) at 400° C. and 350° C. and Material having a refractive index less than that of silicon (with a SiH4/N2O source) at 400° C.
As can be observed in
The invention proposes an alternative manufacturing method which makes it possible to avoid the difficult step of filling the slot.
The invention relates first of all to a method of producing a slotted guide, in which:
A material having a refractive index less than that of silicon can be silicon dioxide SiO2, or silicon nitride SiN, or non-stoichiometric SiOx (x<2).
In the case of non-stoichiometric SiOx (x<2), an annealing step is carried out to separate SiOx into two distinct phases, thus forming nanocristals of silicon in a matrix of SiO2. Preferably, the annealing step is carried out after formation of SiOx and before the trenches are etched.
According to the invention, a method is implemented which is the reverse of the known methods, by first depositing the material having a refractive index less than that of silicon on an unstructured plate. Then it is etched in the form of a wall. Next, the silicon can be deposited.
The material having a refractive index less than that of silicon can be obtained by LPCVD or PECVD.
The silicon used to fill the trenches can be in amorphous form (obtained by PECVD).
The etching barrier layer can be SiO2.
According to another embodiment, the silicon used to fill the trenches can be in monocrystalline form; it is formed by epitaxial growth. The etching barrier layer can thus be made of silicon, this is the thinned surface layer of a SOI substrate, for example.
The material having a refractive index less than that of silicon can be eliminated from each side of the silicon formed in the trenches on either side of the wall of material having a refractive index less than that of silicon.
A first manufacturing method according to the invention will be described in connection with
This method is particularly suited to the case where the silicon of the slotted guide is in amorphous form.
In a first step, silica 22 (
A layer 26 of material having a refractive index less than that of silicon, for example silicon dioxide SiO2 or silicon nitride SiN, or non-stoichiometric SiOx (x<2), is then deposited on the oxide layer 22 (
Next, a hard mask 24 is formed (
A positive photoresist 28 is next deposited on the hard mask layer 24. Openings 30 are formed in this resin (
These openings enable etching of the hard mask layer 24 to be carried out (
Next, a deposit 42, 44 of amorphous silicon (
A planarization step (
Finally (
At the end of this step, a slotted guide remains, the slot consisting of the wall 36, which was isolated from the layer 26 during etching (
According to one alternative, shown in
A positive photoresist 28 is then deposited. Openings 30 are formed in this resin (
These openings enable etching of the hard mask layer 126 and of the nitride layer 124 (
The hard mask 126 is then removed (
Next, a deposit 42, 44 of amorphous silicon is made in each of these two trenches. The upper surface of these deposits is brought to the height or level of the outside surface 125 of the nitride layer 124 via planarization (
A resin 128 is then deposited. The edges are defined via lithography, for the purpose of etching the nitride layer 124 and the underlying layer 26 (
Upon completion of the etching of these latter layers, and then elimination of the resin 128 (
The starting element consists of a stack of a layer of silica 52 and a layer 51 of silicon. A stack such as this is obtained, for example, from a SOI plate, reference 50 designating a semiconductor substrate, made of silicon, for example. The layer 51 has a monocrystalline structure which makes it possible to use a starting crystal for an epitaxial step. This thin layer 51 further makes it possible to reduce the thermal dispersion induced by the light being propagated in the guide.
Next, a deposition 56 of material having a refractive index less than that of silicon is made (
Said material having a refractive index less than that of silicon is for example silicon dioxide SiO2 or silicon nitride SiN, or non-stoichiometric SiOx (x<2).
After lithography, this layer can be etched (see
Monocrystalline silicon 42, 44 can next be formed via epitaxy from the silicon layer 51 in the trenches 32, 34. A planarization step enables the top of these epitaxied areas to be brought back to the level of the outside surface 55 of layer 56 (see
The material having a refractive index less than that of silicon on either side of the epitaxied silicon areas 42, 44 can then be eliminated, thereby leaving a slotted guide structure as shown in
According to an alternative shown in
A positive photoresist 28 is then deposited. Openings 30 are formed in this resin (
These openings enable etching of the hard mask layer 126 and the nitride layer 124 (
The hard mask 126 is then removed (
Next, monocrystalline silicon 42, 44 is produced in each of these two trenches via epitaxy. The upper surface of these depositions is brought to the height or level of the outside surface 125 of the nitride layer 124 via planarization (
A resin 128 is then deposited. The edges are defined via lithography, for the purpose of etching the nitride layer 124 and the underlying layer 56 (
Upon completion of the etching of these latter layers, and then elimination of the resin 128 (
Whatever the embodiment, when the material having a refractive index less than that of silicon is non-stoichiometric SiOx (x<2), an annealing step of the SiOx (x<2) in order to form silicon nanocrystals can be carried out after etching of the SiOx (i.e., after the steps of
But, if the SiOx is deposited in particular via PECVD, its thickness diminishes during annealing. In this case, it is preferable to insert the annealing step immediately after the SiOx deposition and prior to any etching step (and in particular the step of
Once the guide has been formed and etched, a SiO2 cap layer 60 can be made (
Using this technique, the slotted guide is made in the form of 3 layers 36, 42, 44 (in fact: the wall 36 and the two depositions 42, 44 made on either side of this wall) arranged perpendicular to the support substrate, either the Si substrate 20 and the layer 22 of SiO2, in the case of
The invention is particularly advantageous for a slot shape factor (as defined above in connection with
The invention applies in particular to the field of optical interconnections, to that of intra-chip optical interconnections, or else to optical telecommunications.
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