Patent Application
20080157911
The field of invention relates generally to on-die inductively coupled wires, and, more specifically, to on-die inductively coupled wires having improved electrical power consumption efficiency through reduced eddy currents.
Referring to
In order to create a strong “coupling” between the induced signal Is and the primary signal Ip, the magnetic properties of the magnetic core 104 should be sufficiently “soft”. Referring to the hysteresis loop 140 of
The strength of the magnetic field strength H may be made to increase for a given primary signal by looping the primary wire around the magnetic core a number of times. Similarly, the magnitude of the response signal Is may be made to increase by looping the secondary wire a number of times around the magnetic core 104. The magnetic properties of the core 104 and the number of windings associated with the primary and/or secondary signals may be specially designed so that the inductively coupled wires can be used as a transformer where the amplitudes of the primary and secondary signals have a specific designed for ratio. In the case of a 1:1 primary:secondary winding ratio (i.e., each wire runs once through the core) the inductively coupled wires effectively form an inductor in which a voltage V appears across the secondary wire as a function of K(δIp/δt).
A problem with inductively coupled wires is the generation of eddy currents within the magnetic core. Here, the phenomena described by Faraday's law induces electrical currents to flow within the magnetic core 104. These currents cause the magnetic core to consume electrical power owing to the electrical power consumption relationship P=I2R where P is the electrical power consumed by the magnetic core, I is the magnitude of an eddy current that flows through the magnetic core and R is the electrical resistance of the magnetic core through which the eddy current flows. The power consumption of the magnetic core can be reduced by increasing the inherent resistivity of the magnetic core 104. Here, a higher resistivity will result in less eddy current in the magnetic core. This, in turn, drops the overall power consumption of the core because power consumption is a function of the square of the eddy current flow.
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
a through 4d show a laminated-like soft magnetic layer formed with alternating layers of soft magnetic material and an ion implanted surface of soft magnetic material;
In the manufacture of electronic systems, there exists economic efficiency in integrating as many electronically interconnected components as possible with a single manufacturing process. This often results in a motivation to combine as many electronic components as possible onto a single “die” of processed semiconductor material. Moreover, it is not uncommon for a packaged semiconductor chip to be designed to use a voltage regulator that that is located external to the semiconductor chip package on the same “planar” or “PC board” that the semiconductor chip package is mounted to. The voltage regulator essentially suppresses variations in a power supply voltage that is ideally a constant, DC voltage. As is well known in the art, voltage regulators may be built with an “LC” filter where L corresponds to an inductor that physically resides external to the semiconductor chip package.
With the need for a voltage regulator and the need to integrate as many electronic components onto a semiconductor die as is possible, a motivation exists to build “on-die” voltage regulators. That is, a motivation exists to construct a voltage regulator into the various layering of conductive and dielectric materials that are processed onto a semiconductor wafer, which is subsequently cut into a “die” and packaged.
By eliminating the need for an external voltage regulator, printed circuit board space is conserved which should lower the manufacturing costs of the printed circuit board end-product.
According to the on-die inductively coupled wiring design of
In order to reduce the detrimental effects of eddy currents, the magnetic core material constructed from magnetic layers 204, 213 should exhibit sufficiently high electrical resistance while maintaining sufficiently “soft” magnetic properties. As described in the background, high electrical resistance suppresses the flow of any induced eddy currents. That is, the overall magnitude of induced electrical current flow from eddy currents will be lower in a magnetic core material having higher electrical resistance than an otherwise identical magnetic core material having lower electrical resistance. Because the magnitude of the induced eddy currents is lower, the energy loss (or power consumption) of the inductively coupled wires will be reduced resulting in a more electrically efficient device. Also, for the reasons discussed above in the background with respect to the hysteresis loop of
The following dimensions as depicted in
According to this design, sufficiently soft magnetic properties for both the lower and higher magnetic layers 204, 213 corresponds to a saturation magnetic flux density (βSAT) of greater than 1.0 Tesla (T) and a magnetic coercivity (Hc) of less than 10.0 Oersteads (Oe)). Moreover, in order to sufficiently suppress the magnitude of induced eddy currents, both the lower and higher magnetic layers 204, 213 are also designed to have resistivities higher than 140 ρΩ·cm and preferably at least as high as 400 μΩ·cm. Here, note that the magnetic flux density and the coercivity are each measured along the x axis while the resistivity is measured along the z axis of
FIGS. 3_A through 3_G show a process flow for forming on die inductively coupled wires as described above including magnetic layering having both sufficiently soft magnetic properties to maintain magnetic coupling efficiency and sufficiently high resistivity to improve power dissipation efficiency. According to FIG. 3_A, a nitride passivation layer 301 (e.g., Si3N4) is coated over the highest interconnect metal wiring level 300 that has been formed over the semiconductor die. Then, a seed layer 302 for promoting the deposition of the lower magnetic layer, discussed in more detail below, is deposited by plasma vapor deposition (PVD) over the nitride layer 301. According to one possible approach, the seed layer 302 may be any of Copper (Cu), Cobalt (Co), Platinum (Pt), Palladium (Pd), Nickel (Ni), or an alloy of NixFe1-x (where x is within a range of 0-1). Ranges of process parameters suitable for depositing the seed layer by PVD include: 1) wafer pressure=3000-6000 mtorr; 2) DC power=4000-40000 Watts; 3) Ar gas flow=2-20 sccm; 4) temperature set point=20-35° C.°.
After the seed layer 302 is deposited, a layer of photoresist 303 is coated over the wafer (e.g., by being spun on) and is patterned with photolithography techniques to form an opening where the lower magnetic layer is to be formed. The lower magnetic layer 304 is then formed. Different approaches are herein described for forming lower magnetic layer 304. Specifically, a first approach which forms a laminated-like lower magnetic layer 304 is depicted in
Each of these approaches effectively fabricate a structure that includes both: 1) a soft magnetic material (potentially having a low electrical resistivity) to ensure that the lower magnetic layer 304 has soft magnetic properties; and, 2) regions of high electrical resistivity (e.g., a dielectric) to ensure that the lower magnetic magnetic layer, as a whole, exhibits high electrical resistivity. Each of the three different approaches are discussed in succession immediately below.
a through 4d show fabrication of lower magnetic layer 304 of
The theory behind the formation of the multi-layer structure observed in
According to one perspective, the introduction of the ion-implanted dopant atoms into the soft magnetic layers 404_1, 404_3 results in the formation of a dielectric material having sufficiently high resistance that differs from the material of which the soft magnetic layer is composed (as characterized by its atomic composition, atomic locations and crystal lattice phases). The specific material that is formed is apt to be a function of anneal temperature. The appropriate anneal temperature may be defined through rudimentary optimization (e.g., for any type of ion-implant dopant, varying dopant density and anneal temperature across a number of different samples). For example, the reader is referred to Liu et. al., “Effect Of O-Implantation On The Structure And Resistance Of Ge2Sb2Te5 Film”, Applied Surface Science 242 (2005) 62-69 and Sargunas, et. al., “High Resistivity In n-Type InP By He+ Bomardment At 300 and 60 K”, Solid-State Electronics, Vol. 38, Issue 1, January 1995, pp. 75-81. Note however, because the lower magnetic layer 304, 404 is manufactured above the highest level of metal interconnect 300, 400 it is essentially subject to only the lower temperatures typically associated with passivation and I/O interconnect “back-end” processing (e.g., no higher than 400° C.) that are not capable of causing the ion-implanted layer to anneal.
In an embodiment, each of the ion-implanted layers 404_2, 404_4 are formed to a thickness of 100-200 Å (that is, the ion-implantation depth is 100-200 Å) and the soft magnetic layers are formed to a thickness of (i.e., prior to implantation) 5000 Å. Thus, in the finished structure, the ion-implanted layers have a thickness of 100-200 Å and the soft magnetic layers have a thickness of 4800-4900 Å. This corresponds to an ion-implantation thickness-to-soft magnetic layer thickness ratio of 1:24.
Those of ordinary skill will be able to readily achieve a specific ion-implantation region thickness. However, it is expected that to effect thicknesses within a range of 100-200 Å, low to moderate energies (e.g., within a range of 1.1 to 20 keV, inclusive) are apt to be used for implantation of ionized atoms of any of Carbon (C), Oxygen (O), Silicon (Si), Boron (B), Phosphorous (P), Germanium (Ge) or Helium (He). The density of implanted ions may be within a range of 1 E12 to 1E18 cm−2 depending on the extent of the compositional change within the soft magnetic film. Depending on the extent of surface oxidation on an implanted surface, a thin initiation layer (e.g., a monolayer) of Pd may be applied by wet methods over an ion-implanted layer and prior to the plating of the next, subsequent soft magnetic layer to essentially form a seed layer for the next soft magnetic layer.
In an embodiment, each soft magnetic layer 404_1, 404_3 is a Cobalt (Co) alloy, Nickel (Ni) alloy or a Cobalt-Iron alloy (CoxFe1-x)formed by electroless plating. Possible examples include CoxW1-x (where x is within a range of 0.80 to 0.95), CoxWyBz (where percentages of Co and W may respectively vary within ranges of 80-95% and 5-20%), CoxB1-x (where x is within a range of 0.90 to 0.98), CoxWyPz (where percentages of Co and W may respectively vary within ranges of 80-95% and 5-20%), NixB1-x, NixWyBz(where percentages of Ni, W and B may respectively vary within ranges of 80-95%, 5-20% and 2-10%), CoxFeyBz (where percentages of Co, Fe and B may respectively vary within ranges of 80-95%, 2-15% and 2-10%) and CowFexWyBz (where percentages of Co, Fe, W and B may respectively vary within ranges of 80-95%, 2-15%, 5-15% and 2-10%). . . .
Electroless plating processes for the above materials are known in the art. Electroless plating is used because it is preferable to avoid the use of an electrical contact seed layer (which is apt to be the case if electroplating where employed instead), and the surface of the implanted plated layer will remain catalytic to further electroless plating. A potential exemplary electroless plating deposition bath for CoWBP is: 1) 0.01-0.05 M of [Co2+]; 2) 0.1-0.5 M of citrate as a complexing agent so Co is not precipitated at high pH levels; 3) 0.001-0.05 M of [WO42]; 4) 0.5-1.0 M of [BO33]; 5) 0.02-0.1 M of ammonium hypophosphite; 6) 0.02-0.1 M of dimethylamineborane; 7) pH=8.3-9.7; and, 8) temperature=60°-70° C.
Here, the introduction of the nanocomposites to the layer 504 increases the electrical resistance of the layer 504 because of their non-conductive exterior. In order to effect a high resistive material, a high concentration of nanocomposites should be deposited so that the overall layer is less of a transition metal alloy layer than it is a tightly packed agglomeration of nanocomposites. Better said, the closer the packing density of the overall layer, the more electrically resistive the layer should be because the dielectric exteriors of the noncomposites will be in greater contact with one another resulting in a more electrically resistive layer, with a minimum of 50% nanocomposite loading required for a 100× increase in overall resistivity. But at the same time, their introduction to the layer 504 does not substantially deplete the soft magnetic properties of the layer because of their soft magnetic inner core. BSAT for layer 504 can be greater than 1 Tesla even where the nanocomposites make up over 80% of the layer 504 by volume.
With respect to the plating process itself, the nanocomposite particles are suspended in an aqueous solution or electroplating bath through the use of appropriate surfactants. The bath may be agitated (e.g., by pumping) in order to maintain suspension of the particles. Seed layer 502 provides either an initiation source for electroless deposition or an electrical contact for electroplating. Preferred materials for seed layer 502 include Cu, Pd, Co or Ni. An example of a plating bath for deposition of a CoWB layer having nanocomposites with a Co core and SiO2 exterior is as follows: 1) 0.01-0.05M of [Co2+]; 2) 0.1-0.5M of citrate; 3) 0.001-0.05M of [WO42]; 4) 0.5-1.0M of [Bo33]; 5) 0.02-0.1 M of dimethylamineborane; 6) 50-200 ppm of surfactant; 7) nanocomposites with 30 nm average diameter with solution loading of 0.5-1.0 g/L; 8) pH=8.3-9.7; 9) Temp.=60-80° C.
In fabricating this structure, first the seed layer 602 is deposited. The seed layer 602 may be formed and be made from the same materials as described above with respect to seed layer 302 of
It is expected that the pores will not be open at the bottom of layer 650 so as to expose the seed layer, therefore requiring a thin catalyst layer 651 to be deposited on the bottoms of the pores that will serve as a seed layer to promote the deposition of the soft magnetic material 652 within the pores themselves. According to one approach, the catalyst layer material includes Pd and is deposited using an approach similar to the described in Severin et al., “A Study on Changes in Surface Chemistry During the Initial Stages of Electroless Ni(P) Deposition on Alumina”, J. Electrochem. Soc., 140(3), 682. Specifically, the substrate is immersed in the following solutions, in order: (a) DI water for 1-5 min at 20-50 C, for cleaning; (b) 0.1-5% HF for 1-5 min at 20-30 C, for etching; (c) 10-100 g/L aqueous SnCl2 for 1-5 min at 20-30 C, for sensitizing; (d) DI water for 1-5 min at 20-50 C, for rinsing; (e) 0.1-0.5 g/L aqueous PdCl2 mixed with 1-5 mL/L HCl for 1-5 min at 20-30 C, for activating.
After the catalytic layer is deposited, the remaining empty portions of the pores are substantially filled with soft magnetic material 652 by electroless plating. As discussed above with respect to layers 404_1 and 404_3 of
Electroless plating processes for the above materials are known in the art. Electroless plating is used because it is preferable to avoid the use of an electrical contact seed layer. A potential exemplary electroless plating deposition bath for CoWBP is: 1) 0.01-0.05 M of [Co2+]; 2) 0.1-0.5 M of citrate as a complexing agent so Co is not precipitated at high pH levels; 3) 0.001-0.05 M of [WO42]; 4) 0.5-1.0 M of [BO33]; 5) 0.02-0.1 M of ammonium hypophosphite; 6) 0.02-0.1 M of dimethylamineborane; 7) pH=8.3-9.7; and, 8) temperature=60°-70°.
Referring back to FIG. 3_B, after the lower magnetic layer 304 is formed, the photoresist layer 303 (see
After etching any nitride layer 301 that resides over an I/O wire 306 to expose the I/O wire 306 (noting that the portions of the nitride layer 301 beneath magnetic layer 304 and lower dielectric layer 305 are not removed by the etch because they are protected by respective layers 304, 305), referring now to
Another layer of photoresist 350 is deposited, patterned and etched to create regions where electrically conductive wiring such as contact via 308 and primary and secondary wires 309 and 310, respectively are later deposited. In one embodiment the electrically conductive wiring is composed of Cu. In this case, the barrier/seed layer 307 acts as a barrier layer for the Cu contact via 308 and primary, secondary wiring metal 309, 310. After removing the photoresist 350, the higher layer dielectric 311 is then deposited or spun on over the wafer as depicted in FIG. 3_E.
Another layer of photoresist (not shown) is subsequently applied, patterned and etched to expose openings over any contact vias (such as contact via 308) and over the lower magnetic layer 304 where the interlayer lower and higher magnetic layers are to be connected. As depicted in FIG. 3_F, after removing the photoresist, another seed layer 312 similar to seed layer 302 is then deposited over the wafer. According to one embodiment, seed layer 312 (like seed layer 302) is formed by depositing Cu, Co, Pt, Pd, an Al alloy or an AlxCu1-x alloy. Another layer of photoresist 351 is then applied, patterned and etched to form an opening where the higher magnetic layer 313 is to be deposited.
As depicted in FIG. 3_G, the higher magnetic layer 313 is formed. Like lower magnetic layer 304, higher magnetic layer 313 may be a layer comprising dielectric material and soft magnetic material as discussed above with respect to
Referring to
It will be evident to one of ordinary skill that the secondary wire 210, 310 of
The semiconductor die on which the inductively coupled wires are integrated may be a semiconductor die used to implement a component within a computing system.
The one or more processors 701 execute instructions in order to perform whatever software routines the computing system implements. The instructions frequently involve some sort of operation performed upon data. Both data and instructions are stored in system memory 703 and cache 704. Cache 704 is typically designed to have shorter latency times than system memory 703. For example, cache 704 might be integrated onto the same silicon chip(s) as the processor(s) and/or constructed with faster SRAM cells whilst system memory 703 might be constructed with slower DRAM cells. By tending to store more frequently used instructions and data in the cache 704 as opposed to the system memory 703, the overall performance efficiency of the computing system improves
System memory 703 is deliberately made available to other components within the computing system. For example, the data received from various interfaces to the computing system (e.g., keyboard and mouse, printer port, LAN port, modem port, etc.) or retrieved from an internal storage element of the computing system (e.g., hard disk drive) are often temporarily queued into system memory 703 prior to their being operated upon by the one or more processor(s) 701 in the implementation of a software program.
Similarly, data that a software program determines should be sent from the computing system to an outside entity through one of the computing system interfaces, or stored into an internal storage element, is often temporarily queued in system memory 703 prior to its being transmitted or stored. The ICH 705 is responsible for ensuring that such data is properly passed between the system memory 703 and its appropriate corresponding computing system interface (and internal storage device if the computing system is so designed).
The MCH 702 is responsible for managing the various contending requests for system memory 703 access amongst the processor(s) 701, interfaces and internal storage elements that may proximately arise in time with respect to one another. One or more I/O devices 708 are also implemented in a typical computing system. I/O devices generally are responsible for transferring data to and/or from the computing system (e.g., a networking adapter); or, for large scale non-volatile storage within the computing system (e.g., hard disk drive). ICH 705 has bi-directional point-to-point links between itself and the observed I/O devices 708.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
