Claims
- 1. A semiconductor etch process comprising:
- providing a semiconductor wafer topography, wherein said semiconductor wafer topography comprises a semiconductor substrate and a patterned metal layer on said substrate, said patterned metal layer comprising densely patterned trace elements and sparsely patterned trace elements;
- depositing an oxide layer upon said semiconductor wafer topography;
- spin depositing a silicate material upon said oxide layer, wherein a first thickness of said silicate material over said densely patterned trace elements is less than a second thickness of said silicate material over said sparsely patterned trace elements; and
- performing a single step etch of said silicate material in a plasma etch reactor chamber with an etchant comprising CHF.sub.3, O.sub.2, and Ar with approximate flow rates of 60 sccm, 15 sccm, and 266 sccm, respectively, wherein said etchant etches said silicate material at a rate approximately 1.5 times the rate at which said etchant etches said oxide layer such that there is less than a 3.0% variance in the uniformity of the remaining SOG thickness relative to the uniformity of the initial SOG thickness across the entire semiconductor wafer topography.
- 2. The process of claim 1, wherein the step of depositing said oxide layer comprises depositing oxide formed from a TEOS source.
- 3. The process of claim 1, wherein said silicate material comprises spin-on glass material.
- 4. The process of claim 1 wherein said etchant is maintained at a pressure of approximately 755 to 845 millitorrs.
- 5. A semiconductor etch process comprising:
- providing a semiconductor topography;
- forming an oxide layer upon said semiconductor topography;
- forming a variable thickness organic silicate layer upon said oxide layer; and
- performing a single step etch of said organic silicate layer in a plasma etch chamber reactor, wherein an ambient within said chamber reactor comprises CHF.sub.3, O.sub.2, and Ar with approximate flow rates of 60 sccm, 15 sccm, and 266 sccm, respectively, such that said organic silicate layer is etched at a rate greater than 1.5 times the rate at which said oxide layer is etched, and such that there is less than a 3.0% variance in the uniformity of the remaining SOG thickness relative to the uniformity of the initial SOG thickness across the entire semiconductor wafer topography.
- 6. The process of claim 5 wherein said organic silicate layer comprises spin-on glass.
- 7. The process of claim 5 wherein said oxide layer comprises an oxide layer formed from a TEOS source in a plasma enhanced CVD reactor.
- 8. The process of claim 5 wherein said semiconductor topography comprises a patterned metal layer upon a semiconductor substrate.
Parent Case Info
This application is a division of application Ser. No. 08/520,311, filed Aug. 28, 1995, now abandoned.
US Referenced Citations (15)
Foreign Referenced Citations (2)
Number |
Date |
Country |
2240923 |
Sep 1990 |
JPX |
5129247 |
May 1993 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Wolf, "Silicon Processing for the VLSI Era Process Integration", p. 198, 1990. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
520311 |
Aug 1995 |
|