Patent Application
20190181291
The present disclosure relates to a solar cell and a method for manufacturing the solar cell.
As a solar cell having a high power generation efficiency, there is known a solar cell in which crystalline silicon is laminated with an amorphous silicon layer. For a solar cell like this, a method is adopted in which an amorphous silicon layer is formed on a cleaned surface of crystalline silicon through a chemical vapor deposition (CVD) method employing a silicon containing gas such as silane gas.
On the other hand, there is disclosed a technique for making a surface of crystalline silicon amorphous by irradiating a laser beam on the surface of the crystalline silicon.
Incidentally, a vacuum device needs to be used in the amorphous silicon layer forming method employing CVD. When forming an amorphous silicon layer on crystalline silicon employing CVD, impurities remain on an interface between the crystalline silicon and the amorphous silicon layer. These impurities affect the crystalline properties of amorphous silicon formed on the surface of the crystalline silicon, on which the impurities remain, or the electric properties of a completed solar cell. Due to this, less or no such impurities preferably remain on the interface. However, it is difficult to prevent the adherence of impurities to a crystalline silicon substrate in a process of carrying the crystalline silicon substrate into the vacuum device.
The present disclosure has been made in view of these situations, and it is an advantage of the present disclosure to provide a method for manufacturing a solar cell and a solar cell that can reduce impurities on an interface between crystalline silicon and an amorphous silicon layer.
A method for manufacturing a solar cell of the present disclosure includes a first step of forming an amorphous silicon layer by irradiating a crystalline silicon substrate with a laser beam to make a surface of the crystalline silicon substrate amorphous, and a second step of introducing hydrogen into the amorphous silicon layer.
A solar cell of the present disclosure is a solar cell including an amorphous silicon layer on a surface of a crystalline silicon substrate, and an oxygen concentration on an interface between the crystalline silicon substrate and the amorphous silicon layer is the same as an oxygen concentration in a bulk of the crystalline silicon substrate.
According to the present disclosure, the solar cell can be provided by forming the amorphous silicon layer without employing CVD.
The figures depict one or more implementations in accordance with the present teaching, by way of example only, not by way of limitations. In the figures, like reference numerals refer to the same or similar elements.
Hereinafter, referring to drawings, embodiments of the present disclosure will be described in detail. In the description of the drawings, like reference numerals are given to like elements, and that repeated descriptions are omitted as appropriate.
The semiconductor substrate 10 has a first main surface A provided on the light receiving surface side and a second main surface B provided on the rear surface side. The semiconductor substrate 10 absorbs mainly light incident on the first main surface A and generates electrons and positive holes as carriers. The semiconductor substrate 10 is made up of a crystalline silicon substrate such as a crystalline silicon wafer having a conductivity type that is n type or p type. The semiconductor substrate 10 includes a bulk portion 10a having a low doping concentration and a surface portion 10b having a high doping concentration, the bulk portion 10a and the surface portion 10b having a conductivity type that is n type or p type, and an amorphous silicon layer, which will be described later. The bulk portion 10a and the surface portion 10b make up a crystalline semiconductor layer. A texture structure for scattering incident light may be given to the first main surface A of the semiconductor substrate 10. On the other hand, no texture structure is preferably formed on the second main surface B of the semiconductor substrate 10 because the first conductivity-type layer 12n and the second conductivity-type layer 12p, which will both be described later, are provided on the second main surface B in such a way as to be interlaid with each other. The semiconductor substrate 10 of this embodiment includes the bulk portion 10a of an n-type single crystal silicon and the surface portion 10b of an n+ type, and the amorphous silicon layer, which will be described later.
Here, the light receiving surface means a main surface of the solar cell 100 on which light (solar light) is incident, and specifically means a surface on which most of the light incident on the solar cell 100 is incident. On the other hand, the rear surface means the other main surface that is opposite to the light receiving surface. Specifically, the light receiving surface side of the solar cell 100 is disposed so as to face a light transmitting base material (not shown) such as a glass substrate when a solar cell module is formed.
The amorphous silicon layer (the intrinsic amorphous layer 12i, the first conductivity-type layer 12n, the second conductivity-layer 12p) is provided on the second main surface B of the semiconductor substrate 10. In this embodiment, the first conductivity-type layer 12n and the second conductivity-type layer 12p are an n type conductivity and a p type conductivity, respectively and are formed so as to correspond to the n-side electrode 16n and the p-side electrode 16p, respectively. As illustrated in
In this embodiment, the first conductivity-type layer 12n and the second conductivity-type layer 12p may contain microcrystal silicon. The microcrystal silicon refers to a semiconductor in which crystal silicon is precipitated in amorphous silicon.
The intrinsic amorphous layer 12i is made up of an i-type amorphous silicon containing hydrogen (H). The first conductivity-type layer 12n is made up, for example, of an n-type amorphous silicon to which a dopant such as phosphorus (P), arsenic (As) or the like is added and which contains hydrogen (H). The second conductivity-type layer 12p is made up, for example, of a p-type amorphous silicon to which a dopant such as boron (B) or the like is added and which contains hydrogen (H). The intrinsic amorphous layer 12i, the first conductivity-type layer 12n and the second conductivity-type layer 12p each have a thickness, for example, in the order of several nm to 100 nm. The i-type amorphous silicon is an amorphous silicon film containing dopants substantially equal to the dopant concentration of the semiconductor substrate 10 and has a dopant concentration of 1×1017 cm−3 or smaller. On the other hand, the n-type amorphous silicon and the p-type amorphous silicon have a dopant concentration of 5×1021 cm−3 or smaller, as a typical example.
The insulation layer 14 is formed on the intrinsic amorphous layer 12i, the first conductivity-type layer 12n and the second conductivity-type layer 12p. The insulation layer 14 is provided so as to straddle the first conductivity-type layer 12n and the second conductivity-type layer 12p from the intrinsic amorphous layer 12i and is not provided at central portions of the first conductivity-type layer 12n and the second conductivity-type layer 12p in the X direction. The n-side electrode 16n and the p-side electrode 16p are provided on areas where the insulation layer 14 is not provided.
The insulation layer 14 is formed, for example, of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON) or the like. The insulation layer 14 is desirably formed of silicon nitride and preferably contains hydrogen.
The n-side electrode 16n, which collects electrons, is formed on the first conductivity-type layer 12n. The p-side electrode 16p, which collects positive holes, is formed on the second conductivity-type layer 12p. The insulation layer 14 is disposed between the n-side electrode 16n and the p-side electrode 16p, and the n-side electrode 16n and the p-side electrode 16p are electrically insulated by the insulation layer 14 in the X direction.
The n-side electrode 16n and the p-side electrode 16p can be made up of a metallic layer or a transparent conductive layer. For example, a transparent conductive oxide (TCO) such as tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (ITO) or the like is preferably provided on areas of the n-side electrode 16n and the p-side electrode that are brought into contact with the first conductivity-type layer 12n or the second conductivity-type layer 12p. In addition, for example, the n-side electrode 16n and the p-side electrode 16p preferably contain metal such as copper (Cu), tin (Sn), gold (Au), silver (Ag), aluminum (Al) or the like on the transparent conductive oxide. The n-side electrode 16n and the p-side electrode 16p are preferably made up of a laminated body of conductive layers. In this embodiment, this is a laminated structure of an aluminum (Al) layer, a barrier metal layer and a copper (Cu) layer.
A method for forming the n-side electrode 16n and the p-side electrode 16p is not particularly limited, and the n-side electrode 16n and the p-side electrode 16p can be formed by a film forming method such as a sputtering method, a chemical vapor deposition (CVD) method, and the like, a plating method, a combination thereof, and the like.
A passivation layer may be provided on the first main surface A of the semiconductor substrate 10. The passivation layer is formed, for example, of an i-type amorphous silicon containing hydrogen and should be given a thickness in the order of several nm to 25 nm. Additionally, a diffusion layer having an n type or p type conductivity may be provided on the first main surface A of the semiconductor substrate 10.
An insulation layer having a function of a reflection prevention film and a protection film may be provided on the first main surface A of the semiconductor substrate 10. An insulation layer functioning as a reflection prevention film may be formed, for example, of silicon oxide, silicon nitride, silicon oxynitride, or the like. A film thickness is in the order of 80 nm to 1000 nm.
Following this, referring to
Firstly, a texture structure is formed on the first main surface A of the semiconductor substrate 10. The texture structure is formed by submerging a silicon single crystal substrate of a crystal orientation (100) in an alkaline aqueous solution of sodium hydroxide (NaOH) or the like to expose a crystal orientation (111) surface through anisotropic etching.
Next, as illustrated in
Next, as illustrated in
By treating in this way, an area that is at a depth of several nm or greater to 100 nm or smaller from the surface of the second main surface B of the semiconductor substrate 10 is made amorphous. At the same time, the n-type dopant and the p-type dopant are diffused from the n-type dopant diffusion layer 20n and the p-type dopant diffusion layer 20p, respectively, and the first conductivity-type layer 12n and the second conductivity-type layer 12p are formed below the areas where the n-type dopant diffusion layer 20n and the p-type dopant diffusion layer 20 are formed. Then, the area where the n-type dopant diffusion layer 20n and the p-type dopant diffusion layer 20p are not formed constitutes the intrinsic amorphous layer 12i.
As this occurs, since an interface between the semiconductor substrate 10, and the intrinsic amorphous layer 12i, the first conductivity-type layer 12n and the second conductivity-type layer 12p, is not exposed externally, the oxygen concentration of the semiconductor substrate 10 and the oxygen concentration in the intrinsic amorphous layer 12i, the first conductivity-type layer 12n and the second conductivity-type layer 12p become substantially the same. The oxygen concentration can be measured by secondary ion mass spectroscopy (SIMS). Here, the oxygen concentrations being substantially the same means that a difference in oxygen concentration between oxygen concentrations measured by SIMS is no more than a 10-fold difference.
Next, as illustrated in
An annealing treatment is preferably performed after or during the formation of the insulation layer 14. Hydrogen is introduced from the insulation layer 14 into the intrinsic amorphous layer 12i, the first conductivity-type layer 12n and the second conductivity-type layer 12p by heat generated from the annealing treatment, whereby defects within the intrinsic amorphous layer 12i, the first conductivity-type layer 12n and the second conductivity-type layer 12p are inactivated (passivation).
Thereafter, as illustrated in
The surfaces of the first conductivity-type layer 12n and the second conductivity-type layer 12p that are exposed from the partially removed insulation layer 14 may be re-crystallized before the n-side electrode 16n and the p-side electrode 16p are formed. A laser annealing technique should be applied to the re-crystallization. By doing this, an interface resistance between the first conductivity-type layer 12n and the n-side electrode 6n and an interface resistance between the second conductivity-type layer 12p and the p-side electrode 16p can be reduced.
The solar cell 100 of this embodiment can be formed by the manufacturing method described heretofore. By forming the solar cell 100 using the manufacturing method, a good junction interface between the crystalline semiconductor and the amorphous silicon layer of the semiconductor substrate 10 can be formed. In the solar cell employing the crystalline silicon substrate, the passivation layer is provided on the surface thereof to reduce the defect level of the surface of the substrate. Conventionally, silicon oxide, silicon nitride, and amorphous silicon that are formed by a vacuum film forming method such as the chemical vapor deposition method are used as the passivation layer. However, when forming the passivation layer using the chemical vapor deposition method, impurities are occasionally mixed into between the crystalline semiconductor and the passivation layer. According to the method for manufacturing a solar cell of this embodiment, since the interface between the crystalline semiconductor and the amorphous silicon layer is not exposed externally, impurities can be restricted from being mixed into the interface. This can reduce the defect level of the interface between the crystalline semiconductor and the amorphous silicon layer, whereby carriers can be collected with good efficiency.
In this embodiment, hydrogen is introduced to the surface of the semiconductor substrate 10 that is made amorphous, such as the intrinsic amorphous layer 12i, the first conductivity-type layer 12n and the second conductivity-type layer 12p, by performing the annealing treatment after the insulation layer 14 is formed. However, the method for introducing hydrogen to the surface of the semiconductor substrate 10 that is made amorphous is not limited to the method described above. For example, there are adopted methods such as a method in which the surface of the semiconductor substrate 10 is exposed to an atmospheric pressure plasma of hydrogen, a method in which a hydrogen plasma treatment is applied to the surface of the semiconductor substrate 10 in a vacuum environment, and a method in which an ion injection treatment and a hydrogen plasma treatment are applied to the surface of the semiconductor substrate 10.
In this embodiment, the semiconductor substrate 10 is described as including the bulk portion 10a of the n-type single crystal silicon and the n+-type surface portion 10b. However, the semiconductor substrate 10 may include only the bulk portion 10a without providing the surface portion 10b. This will be true with a surface portion 110b of another embodiment of the present disclosure, which will be described later.
Hereinafter, referring to
Firstly, a texture structure is formed on the first surface A of the semiconductor substrate 10. Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Surfaces of the first conductivity-type layer 12n and the second conductivity-type layer 12p may be re-crystallized at the same time as the first conductivity-type layer 12n and the second conductivity-type layer 12p are formed.
Thereafter, an n-side electrode 16n and a p-side electrode 16p are formed. The n-side electrode 16n and the p-side electrode 16p can be formed by applying the sputtering technique or the like as done in the embodiment described above. This can form a solar cell 100 having a like structure to that illustrated in
In the solar cell 100 of the embodiment described above, the second conductivity-type layer 12p to which the p-type dopant is added is described as being formed by irradiating the laser. However, the configuration is not limited thereto. As illustrated in
In this case, only an n-type dopant diffusion layer 20n is formed on the second main surface B of the semiconductor substrate 10, and a first conductivity-type layer 12n and an intrinsic amorphous layer 12i are formed by irradiating a laser. Thereafter, a second conductivity-type layer 22p to which a p-type dopant is added is formed on the first conductivity-type layer 12n and the intrinsic amorphous layer 12i by applying the conventional chemical vapor deposition (CVD) method such as the plasma CVD method or the like. Thereafter, as in the embodiment described above, an insulation layer 14, an n-side electrode 16n, and a p-side electrode 16p are formed.
In the embodiment described above, while the present disclosure of this patent application is described as being applied to the rear surface junction-type solar cell, the present disclosure of this patent application can be applied not only to the rear surface junction-type solar cell but also to other solar cells.
Hereinafter, referring to
The semiconductor substrate 110 has a first main surface A provided on the light receiving surface side and a second main surface B provided on the rear surface side. A similar silicon wafer to that of the embodiment described above can be used for the semiconductor substrate 110. In this embodiment, the semiconductor substrate 110 includes a bulk portion 110a of an n-type single crystal silicon, n+-type surface portions 110b, and amorphous silicon layers, which will be described later.
The amorphous silicon layers (a first conductivity-type layer 112n, a second conductivity-type layer 112p) are provided on the first main surface A and the second main surface B of the semiconductor substrate 110, respectively. In this different embodiment, the first main surface A is covered substantially entirely by the first conductivity-type layer 112n, and the second main surface B is covered substantially entirely by the second conductivity-type layer 112p. In this different embodiment, the first conductivity-type layer 112n and the second conductivity-type layer 112p may contain microcrystal silicon.
The first conductivity-type layer 112n is made up, for example, of an n-type amorphous silicon to which a dopant such as phosphorus (P), arsenic (As) or the like is added and which contains hydrogen (H). The second conductivity-type layer 112p is made up, for example, of a p-type amorphous silicon to which a dopant such as boron (B) or the like is added and which contains hydrogen (H). The first conductivity-type layer 112n and the second conductivity-type layer 112p each have a thickness, for example, of the order of several nm to 100 nm. The n-type amorphous silicon and the p-type amorphous silicon have a dopant concentration of 5×1021 cm−3 or smaller, as a typical example. An intrinsic amorphous layer, not shown, is preferably provided between the semiconductor substrate 110 and the first conductivity-type layer 112n and between the semiconductor substrate 110 and the second conductivity-type layer 112p.
The n-side transparent conductive layer 115n and the n-side electrode 116n are formed on the first conductivity-type layer 112n to collect electrons. The p-side transparent conductive layer 115p and the p-side electrode 116p are formed on the second conductivity-type layer 112p to collect positive holes. The n-side transparent conductive layer 115n and the p-side transparent conductive layer 115p preferably contain transparent conductive oxide (TCO) such as tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (ITO) or the like. The n-side electrode 116n and the p-side electrode 116p preferably contain metal such as copper (Cu), tin (Sn), gold (Au), silver (Ag), aluminum (Al) or the like. The n-side transparent conductive layer 115n and the p-side transparent conductive layer 115p are provided in such a manner as to cover the first conductivity-type layer 112n and the second conductivity-type layer 112p, respectively, substantially entirely. The n-side electrode 116n and the p-side electrode 116p are provided in such a manner as to expose partially surfaces of the first conductivity-type layer 112n and the second conductivity-type layer 112p, respectively.
A method for forming the n-side transparent conductive layer 115n and the p-side transparent conductive layer 115p is not particularly limited, and hence, the n-side transparent conductive layer 115n and the p-side transparent conductive layer 115p can be formed using the thin film forming method such as the sputtering method, the chemical vapor deposition (CVD) method, or the like. A method for forming the n-side electrode 116n and the p-side electrode 116p is not particularly limited, and hence, the n-side electrode 116n and the p-side electrode 116p can be formed, for example, by using a printing method such as a screen print method or an ink jet method, a plating method such as electrolytic plating, or a combination thereof.
Following this, referring to
As illustrated in
Next, as illustrated in
As this occurs, since an interface between the semiconductor substrate 110 and the first conductivity-type layer 112n is not exposed externally, an oxygen concentration of the semiconductor substrate 110 becomes substantially equal to an oxygen concentration of the first conductivity-type layer 112n.
Next, as illustrated in
An annealing treatment is preferably performed after or during formation of the insulation layer 114n. By doing this, hydrogen is introduced from the insulation layer 114n into the first conductivity-type layer 112n due to heat generated by the annealing treatment, whereby defects in the first conductivity-type layer 112n are inactivated (passivation).
Thereafter, as illustrated in
The solar cell 200 of this embodiment can be formed by the manufacturing method that has been described heretofore. Thus, as in the embodiment described above, a good junction interface between the crystalline semiconductor and the amorphous silicon layer of the semiconductor substrate 110 can be formed.
Thus, while the present disclosure has been described by reference to the embodiments and the modified examples, the present disclosure is not limited to the embodiments, and what results from combining or replacing the configurations of the embodiments as required is also included in the present disclosure.
10, 110 semiconductor substrate; 10a, 110a bulk portion; 10b, 110b surface portion; 12i intrinsic amorphous layer; 12n, 112n first conductivity-type layer; 12p, 112p second conductivity-type layer; 14, 114n, 114p insulation layer; 16, 116 electrode layer; 16n, 116n n-side electrode; 16p, 116p p-side electrode; 20n, 120n n-type dopant diffusion layer; 20p, 120p p-type dopant diffusion layer; 22p second conductivity-type layer; 100, 102, 200 solar cell.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-164965 | Aug 2016 | JP | national |
This application is a U.S. continuation application of PCT International Patent Application Number PCT/JP2017/025568, filed Jul. 13, 2017, claiming the benefit of priority of Japanese Patent Application Number 2016-164965, filed Aug. 25, 2016, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2017/025568 | Jul 2017 | US |
| Child | 16279359 | US |
