Solid-state imaging device and method for driving the same

Abstract

A pixel array is provided in which cells are arranged in a matrix. Each cell includes a photodiode, an FD, a transfer transistor, a reset transistor, an amplifying transistor having a gate electrode connected to the FD, a drain connected to a power supply line, and a source connected to a vertical signal line, and an FD wire. The FD wire is provided in a first wiring line, and the vertical signal line is provided in a second wiring line positioned over the first wiring layer. Since the potential of the FD wire follows the potential of the vertical signal line, it is possible to suppress a variation in capacitance occurring in the FD when a position of the vertical signal is shifted, depending on a position of the cell.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1C are plan views illustrating a layout of a pixel array of a MOS solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the solid-state imaging device of the first embodiment, taken along line II-II of FIGS. 1A to 1C.

FIG. 3 is a circuit diagram illustrating a cell in the solid-state imaging device of the first embodiment.

FIG. 4 is a diagram illustrating an outline of a configuration of a pixel array 400 and its surrounding circuits of the solid-state imaging device of this embodiment.

FIG. 5 is a plan view illustrating a layout of a pixel array of a solid-state imaging device according to a first variation of the first embodiment.

FIG. 6 is a plan view illustrating a layout of a pixel array of a solid-state imaging device according to a second variation of the first embodiment.

FIG. 7 is a plan view illustrating a layout of a pixel array of a solid-state imaging device according to a third variation of the first embodiment.

FIGS. 8A to 8C are plan views illustrating a layout of a pixel array of a solid-state imaging device according to a fourth variation of the first embodiment.

FIGS. 9A to 9C are plan views illustrating a layout of a pixel array of a solid-state imaging device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view of the solid-state imaging device of the second embodiment, taken along line X-X of FIGS. 9A to 9C.

FIGS. 11A to 11C are plan views illustrating a layout of a pixel array of a solid-state imaging device according to a third embodiment of the present invention.

FIG. 12 is a circuit diagram illustrating a portion of a pixel array of a solid-state imaging device according to a fourth embodiment of the present invention.

FIGS. 13A to 13C are plan views illustrating a layout of an effective pixel region of a solid-state imaging device according to the fourth embodiment.

FIG. 14 is a circuit diagram illustrating a cell of a MOS solid-state imaging device according to a fifth embodiment of the present invention.

FIG. 15 is a diagram illustrating an outline of a circuit diagram of the solid-state imaging device of the fifth embodiment.

FIGS. 16A to 16C are plan views illustrating a layout of the pixel array of the solid-state imaging device of the fifth embodiment of the present invention.

FIG. 17 is a cross-sectional view of the solid-state imaging device of the fifth embodiment, taken along line XVII-XVII of FIG. 16C.

FIG. 18 is a plan view illustrating a layout of a pixel array of a solid-state imaging device according to a sixth embodiment of the present invention.

FIG. 19 is a plan view illustrating a layout of a pixel array of a solid-state imaging device according to a seventh embodiment of the present invention.

FIG. 20 is a plan view schematically illustrating a layout of a pixel array of a solid-state imaging device according to an eighth embodiment of the present invention.

FIG. 21 is a plan view schematically illustrating a pixel array of a solid-state imaging device according to a ninth embodiment of the present invention.

FIGS. 22A to 22C are plan views illustrating a layout of a light-shielded pixel region of the solid-state imaging device of the ninth embodiment.

FIG. 23 is a cross-sectional view of the solid-state imaging device of the ninth embodiment, taken along line XXIII-XXIII of FIG. 22C.

FIGS. 24A to 24C are plan views illustrating a layout of cells provided in the wiring layer changing region of the solid-state imaging device of the ninth embodiment.

FIG. 25A is a flowchart illustrating an example of the signal processing method of this embodiment. FIG. 25B is a block diagram illustrating an exemplary configuration of a solid-state imaging device in which the signal processing method of the tenth embodiment is implemented.

FIG. 26 is a diagram illustrating an outline of a pixel array of a solid-state imaging device according to an eleventh embodiment of the present invention.

FIGS. 27A to 27C are plan views illustrating cells in a MOS solid-state imaging device according to a first conventional example.

FIG. 28 is a diagram illustrating a cross-section of the solid-state imaging device of the first conventional example, taken along line XXVIII-XXVIII of FIG. 27C.

FIG. 29 is a diagram illustrating an outline of the pixel array of the conventional solid-state imaging device.

FIG. 30 is a schematic diagram illustrating another exemplary pixel array of a conventional solid-state imaging device.

FIG. 31 is a circuit diagram illustrating a cell of a general MOS solid-state imaging device.

FIGS. 32A to 32C are plan views illustrating an exemplary layout of a conventional pixel array (second conventional example).

FIG. 33 is a diagram illustrating an exemplary conventional layout of a pixel array (third conventional example).

FIG. 34 is a diagram illustrating an exemplary cross-section in an effective pixel region of the pixel array of the conventional solid-state imaging device.

Claims

1. A solid-state imaging device comprising: a pixel array including photodiodes for accumulating an amount of electric charges corresponding to the intensity of received light, floating diffusions to which electric charges accumulated by the photodiodes are transferred, transfer transistors for controlling transfer of electric charges from the photodiodes to the floating diffusions, and amplifying transistors having a source from which a signal corresponding to electric charges transferred to the floating diffusion is output, wherein a plurality of cells are provided in the pixel array;at least a power supply line provided over the pixel array and connected to drains of the amplifying transistors;at least a vertical signal line provided over the pixel array and connected to sources of the amplifying transistors; anda plurality of floating diffusion wires provided over the pixel array, connecting gate electrodes of the amplifying transistors and the transfer transistors,wherein, in each of the plurality of cells, at least a pair of the photodiode and the transfer transistor connected to the photodiode is provided, andthe floating diffusion wire is provided in a first wiring layer while the vertical signal line is provided in a second wiring layer positioned over the first wiring layer, over at least a partial region of the pixel array.

2. The solid-state imaging device of claim 1, wherein the photodiodes are arranged in a matrix in the pixel array, andthe vertical signal line and the power supply line are extended in a column direction of the photodiodes and are provided for each column of the photodiodes.

3. The solid-state imaging device of claim 2, wherein over the at least a partial region of the pixel array, the vertical signal line is increasingly shifted toward a center line extending in the column direction of the pixel array as a distance between the vertical signal line and the center line of the pixel array increases.

4. The solid-state imaging device of claim 2, further comprising: contacts provided at positions in the column direction when viewed from the photodiodes, over the plurality of cells, contacting the sources of the amplifying transistors and the vertical signal line, and connecting the first wiring layer and the second wiring layer.

5. The solid-state imaging device of claim 2, further comprising: contacts provided at positions in a row direction when viewed from the photodiodes, over the plurality of cells, contacting the sources of the amplifying transistors and the vertical signal line, and connecting the first wiring layer and the second wiring layer.

6. The solid-state imaging device of claim 2, further comprising: first contacts provided at positions in the column direction when viewed from the photodiodes, over the plurality of cells, contacting the sources of the amplifying transistors and the vertical signal line, and connecting the first wiring layer and the second wiring layer; andsecond contacts provided at positions in a row direction when viewed from the photodiodes, over the plurality of cells, contacting the sources of the amplifying transistors and the vertical signal line, and connecting the first wiring layer and the second wiring layer.

7. The solid-state imaging device of claim 2, wherein the vertical signal lines provided in the second wiring layer are provided as if the vertical signal lines partitioned a region over the photodiodes provided in the plurality of cells, anda space provided at a portion at which the vertical signal lines adjacent in the row direction to each other in the second wiring layer are closest to each other, has a minimum width in the same layer in the pixel array.

8. The solid-state imaging device of claim 7, wherein the space is provided at a corner position of the photodiode when viewed from the top.

9. The solid-state imaging device of claim 8, wherein the space is provided adjacent to a portion of the vertical signal line at which a distance in the row direction from the center line of the pixel array is maximum.

10. The solid-state imaging device of claim 1, wherein the power supply line is provided in the first wiring layer.

11. The solid-state imaging device of claim 1, wherein each of the plurality of cells includes a reset section connected to the floating diffusion and for initializing a state of the floating diffusion.

12. The solid-state imaging device of claim 2, wherein at least a partial region of the pixel array is an effective pixel region,the pixel array further includes a light-shielded pixel region provided around the effective pixel region, andthe vertical signal line is provided in the first wiring layer and the power supply line is provided in the second wiring layer over the light-shielded pixel region, and the vertical signal line and the power supply line cover over the entirety of the plurality of cells in the light-shielded pixel region.

13. The solid-state imaging device of claim 12, wherein the pixel array further includes a wiring layer changing region provided between the effective pixel region and the light-shielded pixel region and adjacent in the column direction to the effective pixel region, andover the plurality of cells provided in the wiring layer changing region, at least one of a third contact for changing wiring layers in which the vertical signal line is provided, from the second wiring layer to the first wiring layer, and a fourth contact for changing wiring layers in which the power supply line is provided, from the first wiring layer to the second wiring layer, is provided.

14. The solid-state imaging device of claim 13, wherein over the plurality of cells provided in the wiring layer changing region, both the third contact and the fourth contact are provided.

15. The solid-state imaging device of claim 13, wherein over the plurality of cells provided in the wiring layer changing region, at least either of a plurality of the third contacts and a plurality of the fourth contacts is provided.

16. The solid-state imaging device of claim 13, further comprising: a wire changing pixel determining section for determining whether or not the signal read via the vertical signal line is a signal output from the source of the amplifying transistor provided in the wiring layer changing region;a dummy signal generating section for outputting a dummy signal instead of the signal when it is determined that the signal is a signal output from the source of the amplifying transistor provided in the wiring layer changing region; anda video signal processing section for processing the signals output from the sources of the amplifying transistors provided in the effective pixel region and the light-shielded pixel region, and invalidating the dummy signal.

17. The solid-state imaging device of claim 13, wherein, of the transfer transistors, a transfer transistor provided in the wiring layer changing region is invariably in an inactive state.

18. A method for driving a solid-state imaging device, wherein the solid-state imaging device comprises a pixel array including a plurality of cells arranged in a matrix, each cell includes a photodiode for accumulating an amount of electric charges corresponding to the intensity of received light and an amplifying transistor having a source from which a signal corresponding to electric charges transferred from the photodiode is output, the pixel array includes an effective pixel region in which a power supply line to which a drain of the amplifying transistor is connected is provided in a first wiring layer, and a vertical signal line to which the source of the amplifying transistor is connected is provided in a second wiring layer positioned over the first wiring layer, a light-shielded pixel region which is provided around the effective pixel region and in which the vertical signal line is provided in the first wiring layer and the power supply line is provided in the second wiring layer, and a wiring layer changing region which is provided between the effective pixel region and the light-shielded pixel region and adjacent in the column direction to the effective pixel region and is used for changing the wiring layers in which the vertical signal line and the power supply line are provided, and the solid-state imaging device processes the signal read from the pixel array, and the method comprises the steps of: (a) reading the signal from the source of the amplifying transistor provided in any one of the plurality of cells via the vertical signal line;(b) determining whether or not the signal is a signal output from the source of the amplifying transistor provided in the wiring layer changing region;(c) generating a dummy signal instead of the signal when it is determined that the signal is a signal output from the source of the amplifying transistor provided in the wiring layer changing region; and(d) processing the dummy signal as an invalid signal.

19. The method of claim 18, further comprising: (e) processing the signal to generate video when it is determined in step (b) that the signal is not a signal output from the source of the amplifying transistor provided in the wiring layer changing region.