Claims
- 1. A solid state image sensor comprising;
- a substrate having insulation surface,
- an active layer of non-single crystal silicon layer provided on said insulation surface, having at least a source region and a drain region,
- a gate electrode layer provided on light receiving region between said source region and said drain region on said active layer through a gate insulation layer,
- a source electrode layer and a drain electrode layer each provided on said source region and said drain region, respectively,
- trap density of said active layer being less than 5.times.10.sup.11 /cm.sup.2,
- said gate electrode layer being provided a predetermined bias potential, and
- electrical output of current between said source electrode layer and said drain electrode layer being provided depending upon input light which illuminates said light receiving region on said active layer.
- 2. A solid state image sensor according to claim 1, wherein said gate electrode layer is made of an Indium-Tin-Oxide, ITO, layer, and said input light is introduced to said light receiving region through said gate electrode layer.
- 3. a solid state image sensor according to claim 1, wherein said substrate is transparent for input light, and said input light is introduced to said light receiving region through said substrate.
- 4. a solid state image sensor according to claim 1, wherein said bias potential is determined so that a circuit between a source electrode and a drain electrode is in an ON state.
- 5. A solid state image sensor according to claim 1, wherein absolute value of said bias potential is less than 7.5 V.
- 6. A solid state image sensor according to claim 1, wherein said bias potential is determined so that a circuit between a source electrode and a drain electrode is in an OFF state.
- 7. A solid state image sensor according to claim 1, wherein said substrate is made of non-single crystal silicon.
- 8. A solid state image sensor according to claim 1, wherein said substrate is made of glass.
- 9. A solid state image sensor according to claim 1, wherein said active layer is a non-single crystal silicon layer which is obtained by crystallizing amorphous silicon layer through anneal process with a laser pulse and hydrogenation process.
- 10. A solid state image sensor according to claim 1, wherein a thickness of said active layer is in the range between 20 nm and 1000 nm, a thickness of said gate insulation layer is in the range between 20 nm and 300 nm, and said active layer is a non-single crystal silicon layer obtained by crystallizing said amorphous silicon layer through anneal process at higher than 600.degree. C., and hydrogenating the same.
- 11. A solid state image sensor according to claim 1, wherein said substrate mounts thin film MOS transistors for a switching element and a shift register for operating said image sensor.
Priority Claims (2)
Number |
Date |
Country |
Kind |
5-63789 |
Mar 1993 |
JPX |
|
5-314135 |
Nov 1993 |
JPX |
|
Parent Case Info
This is a divisional of copending U.S. application Ser. No. 08/343,492, filed Nov. 22, 1994, which is a 35 USC 371 National Stage of PCT International Application PCT/JP94/00452, filed Mar. 22, 1994, which claims priority from Japanese Patent Application 63789/1993 filed Mar. 23, 1993 and Japanese Patent Application 314135/1993 filed Nov. 19, 1993.
US Referenced Citations (7)
Foreign Referenced Citations (7)
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Divisions (1)
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Number |
Date |
Country |
Parent |
343492 |
Nov 1994 |
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