Patent Application
20140191115
This application claims priority from Great Britain Application for Patent No. 1300334.8 filed Jan. 9, 2013, the disclosure of which is incorporated by reference.
This application relates to sensor circuits which comprise a Single-Photon Avalanche Diode (SPAD) and in particular to such circuits providing active recharge of the SPAD.
The avalanche process in solid-state devices has been known since 1953, as has its application to photo-multiplication. An avalanche is triggered when reverse biasing a PN-junction to around the breakdown voltage. This effect can be used in two modes of operation. Commonly, the avalanche photodiodes are biased just below the breakdown voltage, the photocurrent remaining proportional to the incoming light intensity. Gain values of a few hundreds are obtained in III-V semiconductors as well as in silicon.
Single-Photon Avalanche Diodes (SPADs) are solid-state photo detectors which utilize the fact that p-n diodes can be stable for a finite time above their breakdown voltage. When an incident photon with sufficient energy to liberate an electron arrives, avalanche multiplication of the photo-generated electron occurs due to the high electric field. This produces a measurable current pulse signaling the arrival of the photon which negates the need for amplification due to the internal gain of the device.
Essentially SPADs are photodiodes that are biased above the breakdown voltage in the so-called Geiger mode. This mode of operation requires the introduction of a quenching mechanism to stop the avalanche process. Each incoming photon results in a strong current pulse of few nanoseconds duration. The device works in a way that resembles, in some respects, an optical Geiger counter.
Single photon counting devices have only recently been successfully integrated in CMOS technologies opening the way to non-photomultiplier tube (PMT) based fully solid-state single photon sensing devices.
Conventionally, SPADs are sensitive at short wavelengths, which is largely due to the use of shallow source-drain implants to form the avalanche region. SPADs have been created in a variety of CMOS geometries from 0.8 μm to 65 nm. Process variants such as Silicon-on-Insulator (SOI), high voltage and BiCMOS process variants have been employed, making use of additional wells and implants to create suitable guard ring structures and avalanche breakdown regions.
Recently there has been developed a SPAD design (hereinafter referred to as Deep SPAD) which addresses the issue of improving red and NIR (long wavelength) sensitivity in standard CMOS processes. This is described in published PCT Application No. PCT/GB2011/051686 (the disclosure of which is incorporated by reference). Modern CMOS processes are fabricated on an epitaxial layer grown on top of a substrate which results in decreasing doping concentration towards the surface. This feature is combined with the diffusion and implantation characteristics of the n-well and deep n-well (DNW) implants to create the cathode and guard ring. The implanted ions diffuse during subsequent processing steps, creating lower doped regions at the edges of the Deep SPAD which acts as a guard ring. Additionally the guard ring structure may use a p-well blocking layer to create a space between n-well and p-well implants where p-well formation is prohibited. Moreover, the prohibited p-well space is not above a deep n-well implant and is adjacent to the biased region of the device. The net result is a SPAD in CMOS which has a deeper junction and thus much improved long wavelength sensitivity due to the electromagnetic properties of light.
Red and NIR response is a particularly important feature for SPADs because of two main application areas: range detection and lifetime analysis. NIR wavelengths of 850 nm are commonly used in ranging systems because this is invisible to the human eye. Moreover, SPADs have been used in biological experiments for lifetime estimation which potentially may have cell-sorting applications. However, a fundamental problem of existing SPADs is that their peak detection efficiency is blue light. Since blue corresponds to high energy photons, it has the disadvantage of killing the cells which are to be observed. Red light, as it is of lower energy, does not have this problem. Additionally, red sensitivity improvements allow the use of SPADs in digital communication systems using optical fibers because the attenuation of red light is lower than blue light.
As mentioned above, SPAD operation requires quenching. Quenching is required to stop the avalanche process, which is done by reducing the SPAD's reverse bias below its breakdown voltage. The simplest quenching circuit is commonly referred to as passive quenching. Usually, passive quenching is simply performed by providing a resistance in series to the SPAD. The avalanche current self-quenches simply because it develops a voltage drop across the resistance (a high-value ballast load), reducing the voltage across the SPAD to below its breakdown voltage. After the quenching of the avalanche current, the SPAD's bias slowly recovers to at or above the breakdown voltage and the detector is ready to be triggered again.
An alternative to passive quenching is active quenching. There are a number of different active quenching arrangements, although in general active quenching refers to detection of a breakdown event by some subsequent digital logic connected to the SPAD output, and actively pulling the SPAD moving node to a voltage below breakdown, quenching the avalanche. Active quenching is desirable for several reasons such as reduced dead time, the ability to time gate the SPAD, and improved photon counting rate at high light levels enabling a dynamic range extension. Active quenching is essential in many applications of SPAD technology.
An active quench circuit for is not available for the above described Deep SPAD, or any other high voltage positively driven SPAD implemented in a triple-well CMOS process, at present.
It is desirable to be able to provide active quenching for such a Deep SPAD design.
In a first aspect there is provided a sensor circuit comprising: a single photon avalanche diode (SPAD), requiring application of a bias voltage to operate; a charge pump final stage operable to generate said bias voltage from a first voltage and a second voltage, said bias voltage being higher than the breakdown voltage of the SPAD junction, each of said first voltage and said second voltage being lower than the breakdown voltage of the SPAD junction; wherein said final stage is operable to isolate the bias voltage on an electrode of the SPAD, thereby biasing said SPAD.
Said charge pump final stage and said SPAD may be on a common substrate. Said common substrate may form one half of the SPAD's multiplication junction.
Said circuit may be operable such that the bias voltage is stored on the SPAD's capacitance, which comprises the junction capacitance, coupling capacitance, and any parasitic capacitance. Said final stage may be operable to isolate the bias voltage on the SPAD's cathode.
Said final stage may comprise at least one diode at its output to isolate said bias voltage on the SPAD's electrode. Said at least one diode may be integrated within the SPAD. Said diode may comprise a diode implant formed within an implant which forms one half of the SPAD's multiplication junction. Alternatively said diode may be comprised within a separate well implant. Said circuit may comprise a capacitor operable to DC-isolate output devices from said bias voltage, wherein said second voltage is applied to the SPAD's electrode via said capacitor.
Said final stage may be operable to stack the said first and second voltages on one of its nodes so as to generate said bias voltage. Said charge pump final stage may comprise one or more devices isolated from said substrate in a well implant. Said node may comprise a drain or source implant of a MOSFET device. In particular, the charge pump final stage may comprise NMOS transistors isolated from the substrate inside a p-well or PMOS transistors isolated from the substrate inside an n-well. Said node on which said voltage is stacked in order to generate the bias voltage may comprise a drain or source implant of one of said NMOS transistors.
Said final stage may be operable in alternate phases of charging a capacitance with said first voltage and outputting the voltage stored on said capacitance in series with said second voltage. In one specific embodiment, the final stage comprises two capacitances and four MOSFET devices, a first two of said MOSFET devices being operable to selectively connect the first voltage to respective ones of said capacitances and a second two of said MOSFET devices acting as diodes being operable to isolate the voltage on the SPAD cathode from the output of said output stage.
Said circuit may be operable such that the charge pump final stage is enabled at periodic intervals. Said periodic intervals may be selected to be sufficient to counteract leakage from the SPAD cathode. Alternatively said circuit may comprise means operable to sense that the SPAD has triggered and on sensing such a trigger event, actively enabling the charge pump. In the latter case, the circuit may further comprise means operable to enable a correlated emission source.
In an embodiment said charge pump may provide a biasing voltage for a further transistor, connected between said charge pump and the SPAD cathode, said further transistor being configured to operate as a quenching resistor. Said further transistor may be provided within a well implant comprised within said SPAD.
Said second voltage may be provided by a periodic clock signal. Said final stage may be double-sided with said second voltage being provided by two non-overlapping periodic clock signals, the final stage being operable to pump on positive and negative edges of one of said clock signals.
Said sensor circuit may comprise: a plurality of SPAD's; a plurality of charge pump final stages; and a single charge pump operable to generate said first voltage for each of the charge pump final stages.
Each SPAD may comprise a dedicated charge pump final stage.
Embodiments of the invention will now be described, by way of example only, by reference to the accompanying drawings, in which:
The terms active quench and active recharge are often used interchangeably. Indeed, the term ‘quenching’ is often used incorrectly and/or to refer to the recharging process instead. Active quench means that soon after a breakdown event is detected by some subsequent digital logic connected to the SPAD output, the SPAD moving node is actively pulled to a voltage below breakdown, quenching the avalanche. Active quench was mostly developed initially for discrete SPADs which had large capacitances, slow breakdowns, long dead-times and high after-pulsing probability. Active quench gains little performance with fully integrated SPADs in CMOS because the breakdown time is comparable to the switching time period of a MOS device and the after-pulsing probability of integrated SPADs is very low.
Active recharge refers to the ability to actively switch the SPAD above breakdown voltage after a delay generated from some digital logic connected to the SPAD output. The benefits of active recharge are pronounced, even in CMOS integrated SPADs. Active recharge enables variable control over the dead time and hence the after-pulsing probability. Importantly, active recharge enables the SPAD to operate at higher light levels than can be achieved with passive recharge. This is because active recharge drives the output of the SPAD past the digital logic threshold on each recharge event. Passive quench, by comparison, has an R-C recharge time constant and can break down again before the digital logic threshold is reached. This can lead to saturation and eventually reduction in the number of photons detected by a passively recharged SPAD as the light level is increased. This means that the photon count does not track the light level linearly which causes problems in some applications. With active recharge the SPAD output has a more linear photon count response to light level.
Moreover, active recharge further improves the photon detection probability (PDP) of a detector as it prevents the non-linear increase in electric field in the device which arises from an R-C recharge. Passively recharged devices suffer from reduced photon detection probability after the inverter threshold is passed but before the total excess bias is reached. Whereas in an actively quenched system, because the rise to above breakdown is near instantaneous, there is almost no period of time when the PDP is changing and the SPAD is armed.
Additionally, active recharge enables SPADs to be used in ‘time-gated’ mode. Time gating is often used in some ranging techniques where the SPAD is ‘armed’ at the same time or after a correlated light source is pulsed as this can improve the signal to noise ratio or simplify the digital processing.
However, the fundamental disadvantage of all active quench and active recharge circuitry is that they take up much more space than a simple passive quench component in most cases. The large area requirements of active quench/recharge reduce the fill factor of SPAD arrays and therefore reduce the sensitivity to light. Therefore, the use of passive or active quench is a classic engineering trade-off and which approach is better depends on the target application.
The Deep SPAD structure uses the substrate as one half of its multiplication p-n junction. Because of this, the anode terminal has to be common to the rest of the chip (usually ground). Therefore, the only method of connecting a bias voltage to the SPAD is to the cathode terminal, which requires a positive polarity in order to reverse bias the diode (obviously this is reversed for an n-type substrate). The breakdown voltage of such a SPAD constructed from deep n-well (DNW) and the substrate will usually be relatively high because of the low doping concentrations involved.
However, the high positive breakdown voltage of the proposed device is not compatible with standard CMOS transistor gates. Therefore, one method of creating a high voltage compatible ‘quench’ resistor in CMOS is to use a highly resistive polysilicon resistor to connect the cathode of the SPAD to a positive breakdown voltage supply. Moreover, the SPAD cathode, which is the moving node that falls in response to the avalanche current, cannot be directly connected to the CMOS inverter gates because it is also at a high DC bias level. Therefore, it is required to AC-couple the SPAD moving node to subsequent digital CMOS logic to ensure DC compatibility.
The Deep SPAD structure complicates the active quench versus passive quench trade off more than that simply given above. This is because the highly resistive poly resistor takes up significantly more space in CMOS than a MOSFET device which is normally used as a quench resistor in traditional CMOS SPADs. Moreover, high voltage capacitors are generally more compact than high voltage resistors so it is favorable to use capacitors rather than poly resistors where possible.
For low cost and simple integration of SPADs into CMOS products it needs to be possible to generate the high breakdown voltage supply on chip. This presents a problem for the Deep SPAD structure because any high voltage supply would generate the high voltage on the DNW-substrate or n+-p-well diode. Therefore, the SPAD junction and supply would break down at the same voltage (or lower for n+-p-well) making Geiger-mode operation impossible.
It is therefore proposed to use a hybrid of active quench and charge pump circuit theory. Charge pumps are circuits which provide the ability to generate voltages higher than the chip supply voltage by using capacitors and switches or diodes in multiple stages, and are well known in the art. The connection of the MOS devices in charge pumps allows operation at high voltages by ensuring that each MOS transistor only ever sees a voltage difference within its allowed specification, while every terminal sits at the same common DC-bias level. For example, this means that a 3.3V rated NMOS transistor could safely conduct if the body was at 10V, source at 10V, drain at 13.3V, and the gate at 13.3V. The cascading of MOS-devices like a charge pump allows switching operation to occur at high voltage so as to be able to actively drive the Deep SPAD.
Triple-well CMOS processes offer the ability to isolate NMOS transistors from the substrate inside their own p-well surrounded by n-well and deep n-well (DNW). Indeed, it is the deep n-well feature that allows the Deep SPAD to work. Therefore, the active quench and active recharge circuit makes it possible to store the high voltage on an NMOS's n+ source/drain implant inside its own p-well. The n+-p-well diode inside the DNW-substrate diode enables voltages to be pumped above the breakdown voltage of the DNW-substrate junction by a clock voltage at each stage of the charge pump.
Charge pump final stage 200 comprises two capacitances CCK1, CCK2 and four NMOS transistors: two in cross-coupled configuration MP1, MP2, and two in diode configuration MP3, MP4. A high voltage bias signal VHV, which is at a level below the breakdown voltage of the DNW-substrate junction of SPAD SD, is provided from a standard high-efficiency charge pump or external high positive voltage supply. In particular, the high voltage bias signal VHV may be obtained from an on-chip charge pump CP which, because it shares the same substrate as the SPAD SD, should not be allowed to generate voltages at or above the breakdown voltage of the DNW-substrate junction. Non-overlapping clocks CK,
It is preferable to use short duty cycle edges so that the transition on the SPAD node is fast as the voltage is pumped on the positive edges of clock CK and notclock
A sensor may comprise an array of SPADs, all biased by a single high voltage charge pump via a plurality of final stages 200, with the single high voltage charge pump generating a voltage just below the SPAD breakdown voltage, and each individual stage generating the remaining breakdown voltage. In one such embodiment, every SPAD is biased via a dedicated final stage.
As with the Deep SPAD, a guard ring is required around the outside of the charge pump to prevent the lateral junction between p-well and n-well breaking down before the SPAD DNW-substrate junction. As already mentioned, the guard ring in this example is achieved by reducing the p-doping around the periphery of n-well by preventing p-well formation. However, any other guard ring constructions, including all those described in patent application PCT/GB2011/051686, are also valid.
The advantage of the charge pump circuit 200 is that there is a very low parasitic capacitance present on the SPAD cathode: only that which results from the coupling capacitor and n+ MOS implant, which can both be very small, as well as the negligible contribution from the metal interconnect. The high voltage MOS diodes MP3, MP4 isolate the charge pumping capacitors CCK1, CCK2 from the SPAD and limits the maximum charge per pulse and hence reduces the after-pulsing probability. This is substantially different from prior active quench circuits using capacitors, where the capacitor is commonly directly connected to the SPAD's moving node, increasing the parasitic capacitance and therefore after-pulsing.
The high voltage from a charge pump or external supply VHV is connected to the p+ implant 700 (or p+ in p-well), charging the SPAD DNW 720 to a voltage VHV−Vdiode, where Vdiode is the forward-bias turn-on voltage of the diode. A positive pulse of a voltage applied to the other side of capacitor CC (e.g. system voltage VDD applied via MOSFET MP) will pull the DNW 720 to a voltage equal to VHV−Vdiode+VDD, which should be sufficient to bias the SPAD in Geiger mode: i.e. the voltage levels should be such that (VHV−Vdiode+VDD)>VBD. The positive pulse of amplitude VDD may be initially provided by transistor MP and then subsequently provided by detecting the SPAD falling edge and recharging the capacitor voltage CC by means of an active quench circuit AQ.
A main advantage of this embodiment is compactness, with the diode being formed within the SPAD, at the expense of some quantum efficiency loss in the diode D1 junction.
In normal operation, diode D1 will experience reverse bias voltages of around VDD, within normal tolerances and far below the breakdown voltage. As before the voltage on the n+ implant will be initially VHV−Vdiode. A rising edge of amplitude VDD is applied to the capacitor CC by a conventional SPAD active quench circuit (or external clock), reverse biasing diode D1 and raising the SPAD voltage to VHV−Vdiode+VDD, substantially above the SPAD breakdown. Both p-well and n-well are biased at VHV so there is no issue with breakdown of the p-well/n-well/DNW junctions. The n-well/DNW to p-substrate junction of diode D1 is constructed in a similar way to the SPAD and so by definition will not experience breakdown when biased at VHV.
Photons triggering the SPAD will cause breakdown, lowering the SPAD voltage below the active quench circuit AQ threshold. The active quench circuit AQ will respond after a suitable delay (quench time) by resetting the capacitor CC to VDD through transistor MP and hence also resetting the SPAD cathode.
In both constructions capacitor CC should be chosen sufficiently large in comparison to the sum of SPAD and diode capacitances such that the VDD pulse is not substantially attenuated at the SPAD cathode. The circuits described herein can be cascaded to generate any voltage higher than the DNW-substrate breakdown voltage up to the n+-p-well breakdown voltage or the gate oxide breakdown, whichever comes first. This could then be used with a high resistance polysilicon quench resistor for applications where high fill factor is important. However, if the voltage is pumped too high eventually inefficiencies will appear due to the large depletion regions formed around the source and drain implants and the difference between the source/drain voltage and the transistor body (p-well).
The circuits described herein differ from traditional capacitively coupled time gated SPAD circuits which arm the SPAD to a high voltage through a coupling capacitor because of the implementation of the high voltage diode between n+ and p-well of the isolated NMOS device. Critically, this keeps the high voltage on the SPAD cathode even when the clock returns low again (minus leakage current), which simplifies the digital circuitry required to reset the SPAD over a traditional time-gated circuit. As with the Deep SPAD invention, this active quench circuit is compatible with any CMOS process which includes a deep n-well mask with an epitaxial layer grown on top of a substrate.
The previously described circuit can be thought of as an “active quench circuit” because although there are no MOS devices present that actively pull down the SPAD to a lower voltage than breakdown, the SPAD is at no point directly connected to a higher DC voltage supply than the breakdown voltage. This negates the need for traditional “active quench” operation where a MOS (or otherwise) switch is implemented to pull the SPAD to below breakdown, because the SPAD pulls itself to below breakdown and there is nothing pulling it up so it remains low, mimicking “active quench” operation.
There are several ways that the circuit can be operated in active recharge mode depending on the desired digital logic. However, each method requires a mechanism of resetting the voltage on the SPAD cathode to account for leakage current through the SPAD which does not trigger breakdown, such as leakage through the guard ring which reduces the excess bias voltage over time. This can simply be achieved by applying a regular clock pulse to the charge pump with sufficient frequency to compensate for the voltage decay due to leakage.
A first, and simplest, method of continuous operation of the SPAD and charge pump circuit is to connect the SPAD enable input SE (
A second method is more complicated and requires some digital logic to function. The SPAD enable terminal could be connected to a digital state machine of some description which could intelligently perform arming and recharge the SPAD after a breakdown event has been detected. For example, the SPAD could initially be set to the armed, pre-breakdown, state by an application of a SPAD enable pulse. The SPAD would then break down on photon arrival and this would be coupled to the output. The digital logic could then detect the fact that the SPAD has broken down and re-arm the SPAD to a high state after a user-specified time delay. This method has the advantage of a much higher maximum pulse rate and a well-defined dead time of the system. However, it requires more advanced digital logic circuitry. In
A third method is similar to the second, but the initial arming state could be coupled to a correlated light source to enable the SPAD at a similar time to the emission of a light pulse from a ranging system. This would be similar to time-gating but with the advantage that the SPAD would be off when not required. Additionally, the noise performance could be improved through the use of time gating, as discussed above.
An additional potential use of the concepts disclosed herein is to implement a higher fill factor passively quenched system. This could be achieved by using a single NMOS transistor inside its own p-well, biased to behave as a high voltage resistor. This is achieved with an almost identical layout to the charge pump circuits described herein, but with the transistor designed to have a high resistance when on, or biased sufficiently. This may have a smaller area requirement than a polysilicon resistor while remaining high-voltage compatible.
Indeed, the NMOS transistor could be placed inside the SPAD to improve the fill factor. In one embodiment of the Deep SPAD invention, p-well is placed on top of the device to reduce the photon detection probability in the short wavelength range and increase the signal-to-noise of a ranging system operating at 850 nm by increasing the optical filtering of undesired wavelengths. An NMOS quench transistor could be placed inside this isolated p-well and biased to behave as a resistor. This could potentially vastly improve the fill factor of an array of Deep SPADs as there would be no need for separate area to be taken up with a resistor.
The circuit enables the possibility of generating the required high SPAD supply voltage on the same silicon chip which is important for low cost high portability markets, such as the mobile phone market. Since the Deep SPAD has significantly improved sensitivity than existing SPADs, the power consumption of a ranging system would be significantly reduced. The only required external component for a ranging system, 3D camera, or time-correlated lifetime estimation system is a light source such as an LED or laser diode, as all the other components can be fully integrated into CMOS. The ability of a ranging system or 3D camera to be completely integrated into CMOS potentially opens up new portable applications and potential advancements in human-computer interfaces. Additionally, active recharge's ability to offer a more linear response to incident light level is important for certain applications.
Advantages of the circuits disclosed herein in include: the SPAD is recharged only when necessary after a photon trigger and so no clock is necessary; the charge pump output voltage VHV can be shared between multiple SPADs with only the addition of a single diode per SPAD; and the dead time of the SPAD can be controlled by conventional active quench circuitry.
It should be appreciated that the above description is for illustration only and other embodiments and variations may be envisaged without departing from the spirit and scope of the invention. While the above embodiments are disclosed in relation to the deep SPAD, it is equally applicable to any positively driven SPAD implemented in a triple-well CMOS process. Also, while the embodiments all show a p-doped substrate, an n-doped substrate could equally be used, with the doping of all implants reversed accordingly, and all bias voltages changed appropriately.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1300334.8 | Jan 2013 | GB | national |
