Claims
- 1. In a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in said hardware controlled execution unit, a method of operation including the steps of:
- storing a millicode instruction that includes a field specifying a processor state unit register in which said program status word is stored and a field specifying a millicode general register in which a mask is stored indicating those bits in the program status word which are to be zeros if the program status word is valid;
- fetching said millicode instruction from storage;
- performing a logical AND operation between correspondingly positioned bits in said program status word and bits in said mask;
- storing a millicode load and test access instruction that includes a field specifying a millicode register address and a field specifying a storage address for an access exception to a second operand fetch access exception;
- fetching said millicode load and test access instruction;
- executing said millicode load and test access instruction including testing a load operand operation, setting one condition code when no access exception is found, and blocking an interrupt when an access exception is found and setting another condition code;
- storing a millicode instruction to facilitate translation of string bytes which includes a field that specifies a first millicode general register, a field that specifies a second millicode general register, a field that selects one byte from the first register to be added to the content of the second millicode general register to form an operand address of a byte to be fetched from storage, and a field that specifies a register pair into which said byte to be fetched from storage is to be stored; and
- fetching said millicode instruction to facilitate translation of string bytes, and executing said millicode instruction to facilitate translation of string bytes.
BACKGROUND OF THE INVENTION
This application is a division of application Ser. No. 08/414,154 of Charles F. Webb et al., filed Mar. 31, 1995, now U.S. Pat. No. 5,694,587 entitled "Specialized Millicode Instruction."
Non-Patent Literature Citations (5)
Entry |
Intel "Intel Processor Indentification with the CPUID Instruction" AP-485 pp. 1-18, Oct. 1993. |
Digital "VAX11 Architecture Handbook" p. 236, 1979. |
"Structured Computer Organization" Andrew S. Tanenbaum pp. 235-236 & 267-269, 1984. |
Texas Instruments "Digital Signal Processor Products" pp. 3-7, 1983. |
Motorola "Enhanced 32-bit microprocessor user's manual" pp. 3-66, 1989. |
Divisions (1)
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Number |
Date |
Country |
Parent |
414154 |
Mar 1995 |
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