Specialized processing block for programmable logic device

Abstract

A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and advantages of the invention will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:

FIG. 1 is a high-level diagram of one preferred embodiment of a specialized processing block in accordance with the present invention;

FIG. 2 is a functional diagram of the specialized processing block of FIG. 1;

FIG. 3 is a block diagram of a preferred embodiment of a fundamental processing unit for a specialized processing block in accordance with the present invention;

FIG. 4 is a preferred embodiment of an output stage of a specialized processing block in accordance with the present invention

FIG. 5 is a functional diagram of a specialized processing block in accordance with a first preferred embodiment of the present invention configured as part of a finite impulse response filter;

FIG. 6 is a diagram of round-to-nearest-even logic in accordance with the present invention;

FIG. 7 is a schematic diagram of a portion of a specialized processing block showing rounding and saturation logic in accordance with a first embodiment of the present invention;

FIG. 8 is a schematic diagram of a portion of a specialized processing block showing rounding and saturation logic in accordance with a second embodiment of the present invention;

FIG. 9 is a schematic diagram of a portion of a specialized processing block in cascade mode showing location of rounding and saturation logic in accordance with one embodiment of the present invention;

FIG. 10 is schematic diagram of a portion of a specialized processing block in cascade mode showing location of rounding and saturation logic in accordance with another embodiment of the present invention;

FIG. 11 is a schematic diagram of a portion of a specialized processing block in cascade-mode showing location of rounding and saturation logic in accordance with yet another embodiment of the present invention; and

FIG. 12 is a simplified block diagram of an illustrative system employing a programmable logic device incorporating the present invention.

Claims

1. A specialized processing block for a programmable logic device, said specialized processing block comprising: arithmetic circuitry for providing products of inputs and sums of said products to output a result; androunding circuitry for selectably rounding said result to one of (a) a nearest integer, and (b) a nearest even integer.

2. The specialized processing block of claim 1 wherein said rounding circuitry performs said rounding at a selectable bit position of said result.

3. The specialized processing block of claim 1 wherein: said arithmetic circuitry operates on values in a range that extends up to a most highly positive value and down to a most highly negative value; said specialized processing block further comprising:saturation circuitry for clipping said result to a value inside said range.

4. The specialized processing block of claim 3 wherein said saturation circuitry performs said clipping at a selectable bit position of said result.

5. The specialized processing block of claim 3 wherein said saturation circuitry clips said results symmetrically.

6. The specialized processing block of claim 3 wherein said saturation circuitry clips said results asymmetrically.

7. The specialized processing block of claim 3 wherein said saturation circuitry operates after said rounding circuitry.

8. The specialized processing block of claim 1 wherein said rounding circuitry is programmably locatable to optimize operation of said specialized processing block.

9. The specialized processing block of claim 8 wherein at least a first portion of said rounding circuitry is programmably locatable in parallel with at least a portion of said arithmetic circuitry to operate in a look-ahead mode.

10. The specialized processing block of claim 9 wherein: said portion of said arithmetic circuitry computes said result without rounding;said first portion of said rounding circuitry computes said result with rounding in parallel with computation by said portion of said arithmetic circuitry of said result without rounding; andsaid rounding circuitry further comprises a second portion that selects between said result with rounding and said result without rounding.

11. The specialized processing block of claim 8 wherein: said arithmetic circuitry includes a register creating a critical timing path; andsaid rounding circuitry is programmably locatable in at least one position that is at least one of (a) before, and (b) after, said register so as to be programmably includable in, and excludable from, said critical timing path.

12. The specialized processing block of claim 11 wherein said critical timing path includes results chained from another said specialized processing block.

13. A programmable logic device comprising the specialized processing block of claim 1.

14. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; anda programmable logic device as defined in claim 13 coupled to the processing circuitry and the memory.

15. A printed circuit board on which is mounted a programmable logic device as defined in claim 13.

16. The printed circuit board defined in claim further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

17. The printed circuit board defined in claim 16 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

18. An integrated circuit device comprising the specialized processing block of claim 1.

19. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; andan integrated circuit device as defined in claim 18 coupled to the processing circuitry and the memory.

20. A printed circuit board on which is mounted an integrated circuit device as defined in claim 19.

21. The printed circuit board defined in claim further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

22. The printed circuit board defined in claim 21 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

23. A specialized processing block for a programmable logic device, said specialized processing block comprising: arithmetic circuitry for providing products of inputs and sums of said products to output a result; androunding circuitry for selectably rounding said result to one of (a) a nearest integer, and (b) a nearest even integer.

24. The specialized processing block of claim 23 wherein: said arithmetic circuitry operates on values in a range that extends up to a most highly positive value and down to a most highly negative value; said specialized processing block further comprising:saturation circuitry for clipping said result to a value inside said range.

25. The specialized processing block of claim 24 wherein said saturation circuitry performs said clipping at a selectable bit position of said result.

26. The specialized processing block of claim 24 wherein said saturation circuitry clips said results symmetrically.

27. The specialized processing block of claim 24 wherein said saturation circuitry clips said results asymmetrically.

28. A programmable logic device comprising the specialized processing block of claim 23.

29. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; anda programmable logic device as defined in claim 28 coupled to the processing circuitry and the memory.

30. A printed circuit board on which is mounted a programmable logic device as defined in claim 28.

31. The printed circuit board defined in claim further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

32. The printed circuit board defined in claim 31 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.

33. An integrated circuit device comprising the specialized processing block of claim 23.

34. A digital processing system comprising: processing circuitry;a memory coupled to said processing circuitry; andan integrated circuit device as defined in claim 33 coupled to the processing circuitry and the memory.

35. A printed circuit board on which is mounted an integrated circuit device as defined in claim 34.

36. The printed circuit board defined in claim 35 further comprising: memory circuitry mounted on the printed circuit board and coupled to the programmable logic device.

37. The printed circuit board defined in claim 36 further comprising: processing circuitry mounted on the printed circuit board and coupled to the memory circuitry.