SPIN INJECTION WRITE TYPE MAGNETIC MEMORY DEVICE

Abstract

A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a circuit block diagram of a magnetic memory device according to a first embodiment;

FIG. 2 shows a cross-section of a magnetoresistance effect element;

FIG. 3 shows a block diagram of a current source/sink circuit;

FIG. 4 shows a top plan view of a memory cell array according to the first embodiment;

FIG. 5 to FIG. 7 show top plan views of part of the memory cell array according to the first embodiment;

FIG. 8 shows a perspective view of the memory cell array according to the first embodiment;

FIG. 9 shows a perspective view of a memory cell array according to a first modification of the first embodiment;

FIG. 10 and FIG. 11 show top plan views of part of a memory cell array according to a second modification of the first embodiment;

FIG. 12 shows a perspective view of the memory cell array according to the second modification of the first embodiment;

FIG. 13 shows a perspective view of a memory cell array according to a third modification of the first embodiment;

FIG. 14 shows a top plan view of the memory cell array according to a second embodiment;

FIG. 15 shows a top plan view of the memory cell array according to a third embodiment;

FIG. 16 shows a top plan view of the memory cell array according to a fourth embodiment;

FIG. 17 shows a circuit block diagram of a magnetic memory device according to a fifth embodiment;

FIG. 18 shows a top plan view of a memory cell array according to the fifth embodiment;

FIG. 19 shows a perspective view of the memory cell array according to the fifth embodiment;

FIG. 20 to FIG. 23 show block diagrams of a circuit layout of a magnetic memory device according to a sixth embodiment;

FIG. 24 and FIG. 25 shows top plan views of part of a memory cell array according to a fourth modification of the first embodiment;

FIG. 26 shows a perspective view of the memory cell array according to the fourth modification of the first embodiment; and

FIG. 27 to FIG. 29 shows a top plan view of another memory cell array of the third embodiment.

Claims

1. A spin injection write type magnetic memory device comprising: memory cells having a magnetoresistance effect element and a select transistor, the magnetoresistance effect element having one end connected to a first node, the select transistor having a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node;a select line extending along a first direction and connected to a gate electrode of the select transistor;a first interconnect extending along a second direction and connected to the first node; anda second interconnect extending along the second direction and connected to the second node, whereintwo of the memory cells adjacent along the first direction share the first node,two of the memory cells adjacent along the second direction share the second node.

2. A spin injection write type magnetic memory device comprising: a semiconductor substrate;a first gate electrode provided on a gate insulating film provided on the semiconductor substrate, and extending along a first direction;a first diffusion area and a second diffusion area formed on a surface of the semiconductor substrate and sandwiching the first gate electrode;a first plug provided on the first diffusion area;a second plug provided on the second diffusion area;a first magnetoresistance element provided on the second plug;a second gate electrode provided on a gate insulating film provided on the semiconductor substrate, and extending in parallel with the first gate electrode;a third diffusion area and a fourth diffusion area formed on the surface of the semiconductor substrate and sandwiching the second gate electrode, the first and second gate electrodes sandwiching the second and fourth diffusion areas;a third plug provided on the third diffusion area;a fourth plug provided on the fourth diffusion area;a second magnetoresistance effect element provided on the fourth plug;a first interconnect connected to upper surfaces of the first and third plugs; anda second interconnect connected to upper surfaces of the first and second magnetoresistance effect elements.

3. The device according to claim 2, wherein the first interconnect has a first straight part, a first part projecting from the first straight part above the first plug, and a second part projecting from the first straight part above the third plug, andthe second interconnect has a second straight part, a third part projecting from the second straight part above the second plug, and a fourth part projecting from the second straight part above the fourth plug.

4. The device according to claim 3, wherein the first straight part extends along the second straight part below or above the second straight part.

5. The device according to claim 3, wherein the first to fourth diffusion areas, the first to fourth plugs, the first and second magnetoresistance effect elements, the first and second interconnects form a first unit structure,the device further comprises a second unit structure identical to the first unit structure,the first and second unit structures are adjacent along the first direction.

6. The device according to claim 5, wherein the first and second unit structures are symmetry with respect to an imaginary line along a second direction perpendicular to the first direction.

7. The device according to claim 2, wherein the first interconnect lies above the second interconnect,the second interconnect has a line including a first part extending above the second and fourth plugs, a second part extending along a second direction crossing the first direction from a region above the second plug to an opposite region to the first plug, and a third part extending along the second direction from a region above the fourth plug to an opposite region to the third plug.

8. The device according to claim 7, wherein the first interconnect has a line including a fourth part extending above the second and fourth plugs, a fifth part extending above the first and second plugs, and a sixth part extending above the third and fourth plugs.

9. The device according to claim 8, wherein the first to fourth diffusion areas, the first to fourth plugs, the first and second magnetoresistance effect elements, the first and second interconnects form a first unit structure,the device further comprises a second unit structure identical to the first unit structure,the first and second unit structures are adjacent along the first direction.

10. The device according to claim 9, wherein the first and second unit structures are symmetry with respect to an imaginary line along the second direction.

11. The device according to claim 2, further comprising: a third gate electrode provided on a gate insulating film provided on the semiconductor substrate, and extending in parallel with the first gate electrode, the first and third gate electrodes sandwiching the first plug;a fifth diffusion area formed on the surface of the semiconductor substrate, the first and fifth diffusion areas sandwiching the third gate electrode;a fifth plug provided on the fifth diffusion area;a third magnetoresistance effect element provided on the fifth plug, an upper surface of the third magnetoresistance effect element being connected to the second interconnect;a fourth gate electrode provided on a gate insulating film provided on the semiconductor substrate, and extending in parallel with the second gate electrode, the second and fourth gate electrodes sandwiching the third plug;a sixth diffusion area formed on the surface of the semiconductor substrate, the third and sixth diffusion areas sandwiching the fourth gate electrode;a sixth plug provided on the sixth diffusion area; anda fourth magnetoresistance effect element provided on the sixth plug, an upper surface of the fourth magnetoresistance effect element being connected to the second interconnect.

12. The device according to claim 11, wherein the first interconnect has a first straight part, a first part projecting from the first straight part above the first plug, and a second part projecting from the first straight part above the third plug, andthe second interconnect has a second straight part, a third part projecting from the second straight part above the second plug, a fourth part projecting from the second straight part above the fourth plug, a fifth part projecting from the second straight part above the fifth plug, and a sixth part projecting from the second straight part above the sixth plug.

13. The device according to claim 11, wherein the first straight part extends along the second straight part below or above the second straight part.

14. The device according to claim 11, wherein the first to sixth diffusion areas, the first to sixth plugs, the first to fourth magnetoresistance effect elements, the first and second interconnects form a first unit structure,the device further comprises a second unit structure identical to the first unit structure,the first and second unit structures are adjacent along the first direction.

15. The device according to claim 14, wherein the first and second unit structures are symmetry with respect to an imaginary line along a second direction perpendicular to the first direction.

16. The device according to claim 11, wherein the first interconnect has a first straight part, a first part projecting from the first straight part above the first plug, and a second part projecting from the first straight part above the third plug, andthe second interconnect has a second straight part extending along a imaginary line connecting the second and fifth plugs above the second and fifth plugs, a third part projecting from the second straight part above the fourth plug, and a fourth part projecting from the second straight part above the sixth plug.