Claims
- 1. A memory device, comprising:a plurality of input/outputs (I/Os); and a memory core coupled to the plurality of I/Os arranged to store data as at least a first data word and a second data word, wherein the memory core includes, a first bank segment in close proximity to a first one of the plurality of I/Os, wherein the first bank segment is arranged to store a first portion of the first data word, a second bank segment in close proximity to a second one of the plurality of I/Os wherein the second bank segment is arranged to store a second portion of the first data word, and wherein the second bank segment is logically coupled to the first bank segment to form a first virtual memory bank such that in response to a first bank select signal the first bank segment and the second bank segment respectively output the first portion and the second portions of the first data word, and wherein a first signal path from the first bank segment and the first one of the plurality of I/Os and a second signal path from the second bank segment and the second one of the plurality of I/Os are substantially equal such that a first delay time between the first bank segment and the first one of the plurality of I/Os and a second delay time between the second bank segment and the second one of the plurality of I/Os are substantially equal.
- 2. A memory device as recited in claim 1, wherein the memory core further includes:a plurality of memory cells each of which stores a corresponding data bit arranged in rows and columns, wherein the first bank segment is formed of a first group of the memory cells and wherein the second bank segment is formed of a second group of the memory cells.
- 3. A method of accessing data stored in a memory device that includes a plurality of input/outputs (I/Os) coupled to a memory core that stores the data as a first data word and a second data word wherein the memory core includes a first bank segment and a second bank segment wherein the second bank segment and the first bank segment are logically coupled to form a first virtual memory bank, comprising:in the first bank segment, storing a first portion of the first data word in close proximity to a first one of the plurality of I/Os; in the second bank segment, storing a second portion of the first data word in close proximity to a second one of the plurality of I/Os; and outputting the first portion and the second portions of the first data word in response to a first bank select and a second bank select signal, respectively, such that by proximally positioning the first and the second bank segments with respect to their associated I/Os, a first signal path from the first bank segment to the first one of the plurality of I/Os and a second signal path from the second bank segment to the second one of the plurality of I/Os are substantially equal and wherein a first delay time between the first bank segment and the first one of the plurality of I/Os and a second delay time between the second bank segment and the second one of the plurality of I/Os are substantially equal.
- 4. A computing system, comprising:a memory device having logically coupled and distributed memory bank segments proximally positioned relative to their associated I/Os so as to substantially equalize a respective output delay time for each memory bank segment; a processor coupled to the memory device for performing executable instructions stored in the memory device; and a memory controller coupled to the processor by way of a bi-directional data bus and an address bus.
CROSS-REFERENCE TO A RELATED APPLICATION
This application takes priority under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 60/181,075 filed Feb. 8, 2000, naming Subramani Kengeri as inventor, and assigned to the assignee of the present application which is also incorporated herein by reference in its entirety for all purposes.
US Referenced Citations (4)
Provisional Applications (1)
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Number |
Date |
Country |
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60/181075 |
Feb 2000 |
US |