Claims
- 1. A memory cell with partially buried source and improved coupling ratio comprising:
- a substrate having active and field regions defined;
- a partially buried source line formed therein;
- a plurality of floating gates formed substantially sharing said source line; and
- a plurality of control gates over said plurality of said floating gates.
- 2. The memory cell of claim 1, wherein said partially buried source line is formed in a trench in said substrate.
- 3. The memory cell of claim 1, wherein said trench has a depth between about 700 to 800 .ANG..
- 4. The memory cell of claim 1, wherein said buried source line in said substrate is formed by selective epitaxial growth (SEG) of silicon through chemical vapor deposition of SiHBr.sub.3 at a temperature between about 500 to 600.degree. C.
Parent Case Info
This is a division of patent application Ser. No. 09/072,996, filed date May 6, 1998, now U.S. Pat. No. 6,017,795, A Method Of Fabricating Buried Source To Shrink Cell Dimension And Increase Coupling Ratio In Split-Gate Flash, assigned to the same assignee as the present invention.
US Referenced Citations (7)
Divisions (1)
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Number |
Date |
Country |
Parent |
072996 |
May 1998 |
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