Patent Application
20230013187
The present invention relates generally to complementary metal-oxide semiconductor (CMOS) image sensors. More particularly, embodiments relate to split-SEL (select block) pixel designs for use with CMOS image sensors (CISs).
Many modern electronics applications include integrated digital cameras and/or other imaging systems, which are based on complementary metal-oxide semiconductor (CMOS) image sensor (CIS) technologies. A CIS can typically include an array of pixels, each including a single photo-sensor (e.g., photodiode), or a grouping of multiple photo-sensors. Each pixel can also include supporting hardware, such as a select gate for selecting the pixel and a source-follower transistor for converting the optical responses of the photo-sensors into corresponding electrical signals for use by other components. Performance of a pixel can relate to its size. For example, increasing the size of the photodiode area in the pixel can increase the photodiode's full-well capacitance (FWC), which tends to support higher dynamic range, higher contrast, and/or other image performance improvements. Similarly, increasing the active area of the source-follower transistor can improve the pixel's noise performance, such as by increasing its signal-to-noise ratio (SNR).
For any given pixel size, the footprint must be shared by both the photo-sensor(s) and the supporting hardware. As such, any increase in the size of one forces a decrease in the size of the other, such that the pixel design conventionally represents a trade-off between image performance (relating largely to size and corresponding FWC of the photo-sensors) and noise performance (relating largely to active area of the source-follower transistor). As pixel dimensions continue to decrease, it becomes increasingly difficult to maintain acceptable noise performance while optimizing FWC.
Embodiments provide circuits, devices, and methods for implementing a split-select-block (split-SEL) complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel physical architecture, such as for reducing noise in low-light application contexts. The split-SEL CIS pixel physical architecture can include a pixel block with one or more photodiodes. Above the photodiodes, there can be: a first oxide diffusion region with a reset block and a gain block disposed thereon; and a second oxide diffusion region with a select block disposed thereon. Below the photodiodes, there can be a third oxide diffusion region with a source follower (SF) block (e.g., a square-gate SF transistor) disposed thereon. A trace can be routed through the set of photodiodes to couple the source of the SF block with the select block. The architecture permits an appreciable increase in the physical gate length and/or other features.
According to one set of embodiments, a split-select-block (split-SEL) complementary metal-oxide semiconductor (CMOS) image sensor (CIS) pixel physical architecture is provided. The architecture includes: a pixel block having a set of photodiodes; a first oxide diffusion region above the set of photodiodes and having, disposed thereon, a reset block to reset the pixel block and a gain block to provide dynamic control gain (DCG) to the pixel block; a second oxide diffusion region above the set of photodiodes and having, disposed thereon, a select block to select the pixel block, the select block having a control contact and a read-out contact; a third oxide diffusion region below the set of photodiodes and having, disposed thereon, a source follower block having a source contact, a drain contact, and a gate contact; and a trace routed through the set of photodiodes to couple the source contact with the control contact. In some such embodiments, the source follower block comprises a square-gate source follower (SGSF) transistor.
According to another set of embodiments, a split-SEL source-follower transistor system is provided. The system includes: a source follower transistor disposed on an oxide diffusion region of a pixel architecture, the oxide diffusion region electrically isolated from a select block of the pixel architecture, the source follower transistor comprising: an active layer comprising a source-doped region separated from a first drain-doped region by a first current channel, and separated from a second drain-doped region by a second current channel; and a square-gate layer comprising: a first main-gate region disposed above the first current channel to a first side of the source-doped region; and a second main-gate region, coupled with the first main-gate region, and disposed above the second current channel to a second side of the source-doped region opposite the first side of the source-doped region. In some such embodiments, the oxide diffusion region is a first oxide diffusion region, and the system further includes: a second oxide diffusion region, electrically isolated from the first oxide diffusion region, and having the select block disposed thereon, the select block including a control contact and a read-out contact; and a trace to couple the source-doped region with the control contact.
The accompanying drawings, referred to herein and constituting a part hereof, illustrate embodiments of the disclosure. The drawings together with the description serve to explain the principles of the invention.
In the appended figures, similar components and/or features can have the same reference label. Further, various components of the same type can be distinguished by following the reference label by a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
In the following description, numerous specific details are provided for a thorough understanding of the present invention. However, it should be appreciated by those of skill in the art that the present invention may be realized without one or more of these details. In other examples, features and techniques known in the art will not be described for purposes of brevity.
The pixel 105 also includes additional components to facilitate sage of the photo-sensor block 110 for optical sensing. As illustrated, embodiments can include a gain block 120, a reset block 130, a source-follower block 140, and a select block 150. The gain block 120 can control gain for the pixel 105, such as by implementing dual conversion gain (DCG). The reset block 130 can selectively reset the pixel 105 components. The source-follower block 140 can support conversion of outputs from the photo-sensor block 110 into an electrical signal indicative of optical information detected by the photo-sensor block 110. The select block 150 can support selection of the pixel 105 signals from among the array of pixels 105, for example responsive to a control signal received via a bus 160. For example, the bus 160 may be a column select bus, or the like.
As technology progresses, new applications continue to push for reductions in the sizes of image sensor pixels 105. Indeed, many digital imaging applications are seeking ever-increasing numbers and densities of pixels 105 on their image sensor chips (i.e., driving decreases in pixel 105 sizes), while also demanding that designs continue to meet or exceed multiple performance parameters, such as relating to image contrast, dynamic range, capture frame-rate, signal-to-noise ratio (SNR), power consumption, etc. However, it has been demonstrated that certain performance parameters of pixels 105 tend to be adversely impacted by reducing the sizes of components within the pixel 105. For example, decreasing the size of a photodiode 115 in the photo-sensor block 110 can decrease its full-well capacitance (FWC), which can tend to yield lower dynamic range, lower contrast, and/or other image performance reductions. Similarly, decreasing the active area of the source-follower block 140 can reduce the pixel's 105 noise performance, such as by reducing its signal-to-noise ratio (SNR). For example, decreasing the active area of the source-follower block 140 can tend to increase its susceptibility to low-frequency noise (sometimes referred to as 1/f noise), and/or burst noise (also referred to as random telegraph signal (RTS) noise, impulse noise, bi-stable noise, etc.). Some conventional pixel 105 designs seek to maximize component sizes within the limited footprint of the pixel 105, but the footprint of each pixel 105 is shared by all its components; increasing the size of one component (e.g., the photo-sensor block 110) tends to require decreasing the size of another (e.g., source-follower block 140). As such, conventional pixel 105 designs are often forced into a trade-off between image performance (relating to size and corresponding FWC of the photo-sensors) and noise performance (relating to active area of the source-follower transistor).
As pixel 105 dimensions continue to decrease, it is becoming increasingly difficult even to reach an acceptable trade-off between image performance and noise performance. One advanced approach to addressing this trade-off is integration of so-called “square-gate” source followers, or the like. Examples of square-gate source followers are described and illustrated in U.S. patent application Ser. No. 17/141,141, titled “SQUARE-GATE SOURCE-FOLLOWER FOR CMOS IMAGE SENSOR PIXEL,” filed on Jan. 4, 2021, which is hereby incorporated by reference in its entirety. Square-gate source followers are configured in a manner that effectively increases (e.g., doubles) the gate width, thereby increasing the transconductance of the source-follower and reducing the RTS noise.
For the sake of added context,
The active layer 205 can be implemented using a silicon substrate, such as a portion of a silicon wafer. The active layer 205 includes a drain-doped region 210 separated from a first source-doped region 215a by a first current channel, and separated from a second source-doped region 215b by a second current channel. Each of the drain-doped region 210 and the source-doped regions 215 are denoted by dashed circles intended to represent the approximate locations of the respective regions. In some implementations, each of the drain-doped region 210 and the source-doped regions 215 are n-doped regions (e.g., wells) in a p-doped substrate, such that application of a voltage proximate to the current channels causes current to flow in parallel from the drain-doped region 210 to the two source-doped regions 215. Alternatively, each of the drain-doped region 210 and the source-doped regions 215 can be p-doped regions (e.g., wells) in an n-doped substrate, such that application of a voltage proximate to the current channels restricts current from flowing in the current channels between the drain-doped region 210 to the source-doped regions 215.
As used herein in context of current, the term “parallel” is intended to mean electrically (not necessarily geometrically) parallel. In particular, references to “parallel” current channels means that current from a single circuit node (e.g., the drain-doped region 210) splits along multiple current paths (e.g., to two separate source-doped regions 215) along independent paths, regardless of the geometric relationship between those paths. For example, the current channels in the illustrated SGSF transistor 200 provide parallel current paths between the drain and source regions of the transistor, even though they are geometrically collinear (not geometrically parallel to each other). Further, the term “current channels” is used herein to refer to a region through which current is intended to flow by design under particular operating conditions, even if current is not presently flowing in that region. For example, one of ordinary skill in the art will understand that references herein to the drain-doped region 210 being separated from source-doped regions 215 by current channels provides a clear description of the physical relationship between the drain-doped region 210 and the source-doped regions 215, even when the device is not operating and/or no current is otherwise flowing.
Embodiments of the square-gate layer 220 include at least two main-gate regions 222 that are coupled together to form the “square-gate”. The embodiments shown in
Regardless of the manner of coupling together the main-gate regions 222, embodiments can use a single gate contact 226 to control voltage to the entire square-gate layer 220 (i.e., at least to both main-gate regions 222). The drain-doped region 210 has a drain contact 212 electrically coupled with and disposed thereon. Each of the source-doped regions 215 has a respective source contact 217 electrically coupled with and disposed thereon. Each main-gate region 222 of the square-gate layer 220 is disposed above a respective current channel to a respective side of the drain-doped region 210 opposite each other. For example, the first main-gate region 222a is disposed above a first current channel between the drain-doped region 210 and the first source-doped region 215a, and the second main-gate region 222b is disposed above a second current channel between the drain-doped region 210 and the second source-doped region 215b. The two current channels effectively cause the drain current to split along the two current channels 225 and flow in opposite directions to the sources. In some implementations, the current channels are designed to be matched, such as by being equivalent in channel length, doping, etc., such that current will split substantially equally between the channels.
Each current channel has a channel length (L) 230 over which the current travels between the drain-doped region 210 and a respective source-doped region 215. Similarly, at least because of doping parameters and edge isolation structures, the active region of the active layer 205 has a definable width (W) 235. The channel length 230 and active region width 235 are closely related to the length and width, respectively of the main-gate region 222 disposed above each channel. As such, the description generally uses length 230 (or L 230) to refer both to the channel length of each current channel and to the physical length of each main-gate region 222, and the description generally uses width 235 (or W 235) to refer both to the active region width and to the physical width of each main-gate region 222. The length 230 and width 235 are controlled, at least in part, by pixel design parameters and manufacturing process constraints. For example, as noted above, the pixel footprint design balances allocated space between the photo-sensor block 110 and supporting components, including the source follower block 140 (which can be implemented by the SGSF transistor 200). The allocated space can typically define the maximum (or nominal) length and width of transistor components.
By having parallel matched current channels, the SGSF transistor 200 architecture doubles the active region width 235 without changing the physical width of the main-gate regions 222 (or of the overall source-follower transistor). As such, the SGSF transistor 200 manifests operationally as a source-follower transistor that is the same length L 230 and twice the width 235. It can be demonstrated that transconductance of source-follower transistors is proportional to W 235 and inversely proportional to L 230; or proportional to a ratio of W to L (i.e., to W divided by L). As such, doubling W with the same L can nominally double the transconductance of the transistor. For example, a transconductance relationship for a source-follower transistor can be described as follows:
where g_m is the transconductance, and I_D is the drain current (i.e., essentially the output of the transistor). Other parameters, such as C_ox (oxide capacitance), μ_eff (effective gain), m (body coefficient), and g_ox (oxide thickness) tend to be relatively constant and dependent on the manufacturing process and other such characteristics.
Increasing W 235 relative to L 230 (e.g., nominally doubling W 235) can provide a number of features. One such feature is that higher transconductance can support operation at higher frame rates of image acquisition. Another such feature arises from the transconductance being linearly proportional to the product of the drain current and the W/L ratio (as shown in the relationship above). As such, by increasing the W/L ratio, the same transconductance can be achieved with lower current, and thereby with lower power consumption. Other such features relate to noise performance. One noise performance-related feature is based on channel implant depth typically representing a trade-off between transconductance-related performance (e.g., efficiency) and noise-related performance. Increasing the W/L ratio can allow the same transconductance to be achieved with smaller surface carrier density (e.g., with deeper channel implanting), and thereby with less associated noise. Another noise performance-related feature relates to the shape of the square-gate, which can produce regions of overlap between the square-gate layer 220 and edge isolation structures 240 that are longer current paths than the primary current paths through the main-gate regions 222 and therefore tend to suppress current flow along the length-wise edges of the SGSF transistor 200. Because the length-wise edges can tend to have high electric field strengths that trap electrons and produce relatively high amounts of noise, suppressing current flow through those regions can reduce noise.
The schematic 300 clearly shows that the select block 150 is coupled between the source contact 217 and a bus 160. For example, the bus 160 is a column select bus with a bias current source 310. At least because of the direct coupling between the source contact 217 and the select block 150, conventional physical integrated circuit layouts place the select block 150 directly adjacent to the source follower transistor 140, typically disposed on a shared oxide diffusion region 310 and sharing a contact.
In some implementations, such a physical layout 400 can be for a standard 2-by-2 CIS pixel layout. In other implementations, the physical layout 400 can represent a portion of a standard 4-by-2 CIS pixel layout (e.g., another photo-sensor block 110 with four additional photodiodes 115 can be implemented below the lower portion of the layout 400, and all eight photodiodes 115 can share the gain block 120, reset block 130, select block 150, and SGSF transistor 200). Lengths, widths, and placement of component blocks are controlled at least by various design and manufacturing constraints. One such constraint defines a maximum total size of the physical layout, such that increasing the size of one component can force a reduction in the size of another component. For example, as described above, it can be desirable (e.g., for improving transconductance, noise performance, and/or other parameters) to increase the effective width of the source follower. Increasing the physical width of the source follower, as with a larger conventional planar-gate source follower, would force a trade-off with the size of the photodiodes 115, which can be undesirable. However, the SGSF transistor 200 increases (e.g., doubles) the effective width of the source follower without increasing the physical width by consuming more length to provide parallel matched current channels.
Still, the physical dimensions of the SGSF transistor 200 are constrained for various reasons. Conventional design constraints tend to limit the physical width of the source follower block 140 (e.g., the SGSF transistor 200) based on a desire to maximize the size of the photodiodes 115 (i.e., not to reduce their size in favor of a larger source follower). Conventional design constraints tend to limit the physical length of the source follower block 140 based on constraints relating to the oxide diffusion region 410b and/or contacts. For example, the placement of the select block 150 allows one of its contacts to be shared directly with the source contact 217b of the source follower block 140, and leaves the other of its contacts available for use as a read-out contact 420. To isolate the read-out contact 420 from adjacent components (e.g., the right-adjacent oxide diffusion region of the adjacent pixel, not shown), the oxide diffusion region 410b ends immediately to the right of the read-out contact 420, and a minimum length of space is left (i.e., without oxide diffusion, contacts, etc.). As such, it can be seen that the physical length of the source follower block 140 is effectively limited by the placement of the select block 150. In typical conventional designs, such a restriction of length is not considered to be a constraint, at least because, as described above, transconductance of the source follower block 140 tends to be inversely proportional to its length. Because conventional designs generally seek to maximize transconductance (e.g., to maximize conversion gain, frame rate, etc.), there is typically no design motivation to increase the length of the source follower block 140.
Still, as noted above, a primary source of noise experienced by the photodiodes 115 is RTS noise from the source follower, and the amount of the RTS noise relates to the total footprint (i.e., the length and width of the gate area) of the source follower. Increasing the total gate area can decrease the amount of noise. Integration of a conventional SGSF transistor 200 can allow the effective width to increase (e.g., double), thereby appreciably reducing noise relative to a similar-physical-width planar-type source follower. However, for some low-light applications, even very small amounts of noise can interfere with operation; even with a conventional SGSF transistor 200, the level of RTS noise can impact low-light performance levels.
Embodiments described herein provide techniques to increase the length of the source follower (e.g., the gate length of the SGSF transistor 200) to reduce noise for low-light applications. Such techniques split the select block 150 away from the source follower block 140, such that they do not share oxide diffusion region 410b, and can also reconfigure the SGSF transistor. Using such techniques, the gate length of the SGSF transistor can be appreciably increased, which can further reduce RTS noise. Notably, such an increase in gate length will also tend to decrease transconductance of the SGSF transistor. Such an impact to transconductance may be acceptable in low-light applications, which may be able to tolerate lower conversion gain, lower frame rate, etc.
As in the conventional layout 400 of
The reconfigured SGSF transistor 510 includes various features. One feature is that moving the select block 150 out of the lower oxide diffusion region 410b allows the gate length (illustrated by arrow 520) of the reconfigured SGSF transistor 510 can be appreciably longer. For example, using an example state-of-the-art manufacturing process to implement CIS pixels according to the illustrative physical layout 400 of
Another feature is that the reconfigured SGSF transistor 510 has a single source-doped region 215 with a single source contact 217 located in toward the center of the source follower block 140, and a single drain-doped region 210 with a single drain contact 212 at the outside of the source follower block 140. This is essentially the opposite of the conventional SGSF transistor 200 configuration illustrated in
Another feature is that reconfiguration of the source-doped region 215 and the drain-doped region 210 permits placement of multiple reconfigured SGSF transistors 510 directly adjacent to each other. As described above (e.g., in the circuit schematic 300 of
For the sake of illustration,
When multiple, adjacent reconfigured SGSF transistors 600 are implemented on a shared lower oxide diffusion region 410b, at least a portion of the reconfigured SGSF transistors 600 can share drain-doped regions 210 (and/or share drain contacts 212). For example, the first drain-doped region 210a shown as part of the reconfigured SGSF transistor 600 may also be a respective second drain-doped region 210b of another reconfigured SGSF transistor 600 (not shown) that is directly adjacent to the right of the illustrated reconfigured SGSF transistor 600 and sharing the same lower oxide diffusion region 410b; and/or the second drain-doped region 210b shown as part of the reconfigured SGSF transistor 600 may also be a respective first drain-doped region 210a of another reconfigured SGSF transistor 600 (not shown) that is directly adjacent to the left of the illustrated reconfigured SGSF transistor 600 and sharing the same lower oxide diffusion region 410b.
Returning to
It will be understood that, when an element or component is referred to herein as “connected to” or “coupled to” another element or component, it can be connected or coupled to the other element or component, or intervening elements or components may also be present. In contrast, when an element or component is referred to as being “directly connected to,” or “directly coupled to” another element or component, there are no intervening elements or components present between them. It will be understood that, although the terms “first,” “second,” “third,” etc. may be used herein to describe various elements, components, these elements, components, regions, should not be limited by these terms. These terms are only used to distinguish one element, component, from another element, component. Thus, a first element, component, discussed below could be termed a second element, component, without departing from the teachings of the present invention, As used herein, the terms “logic low,” “low state,” “low level,” “logic low level,” “low,” or “0” are used interchangeably. The terms “logic high,” “high state,” “high level,” “logic high level,” “high,” or “1” are used interchangeably.
As used herein, the terms “a”, “an” and “the” may include singular and plural references. It will be further understood that the terms “comprising”, “including”, having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term “consisting of” when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components. Furthermore, as used herein, the words “and/or” may refer to and encompass any possible combinations of one or more of the associated listed items.
While the present invention is described herein with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Rather, the purpose of the illustrative embodiments is to make the spirit of the present invention be better understood by those skilled in the art. In order not to obscure the scope of the invention, many details of well-known processes and manufacturing techniques are omitted. Various modifications of the illustrative embodiments, as well as other embodiments, will be apparent to those of skill in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications.
Furthermore, some of the features of the preferred embodiments of the present invention could be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles of the invention, and not in limitation thereof. Those of skill in the art will appreciate variations of the above-described embodiments that fall within the scope of the invention. As a result, the invention is not limited to the specific embodiments and illustrations discussed above, but by the following claims and their equivalents.
