Claims
- 1. A semiconductor integrated circuit device used as a testing element comprising:a static random access memory including N channel MOS transistors as transfer gate transistors, and complementary MOS circuits each composed of a P channel MOS transistor and an N channel MOS transistor, first multi-layered wirings connecting the N channel MOS transistors as transfer gate transistors, the P channel MOS transistor and the N channel MOS transistor of the complementary MOS circuits with each other, and opening holes communicating the multi-layered wirings with each other; and a group of a type of semiconductor integrated circuits each including a P channel MOS transistor and an N channel MOS transistor, second multi-layered wirings connecting the P channel MOS transistor and the N channel MOS transistor of each of said semiconductor integrated circuits with each other, and opening holes communicating the second multi-layered wirings with each other, wherein an area of a gate including a source region, a drain region and a channel region of each of the N channel MOS transistors of the transfer gate transistors and the P channel MOS transistor and the N channel MOS transistor of each of the complementary MOS circuits of the random access memory is greater than an average area of gates each including a source region, a drain region and a channel region of each of the P channel MOS transistors and the N channel MOS transistors of the semiconductor integrated circuits, wherein a length of each of the wirings of the random access memory is greater than an average length of the wirings of the semiconductor integrated circuits, and wherein the number of the opening holes of the random access memory is greater than an average number of the opening holes of the semiconductor integrated circuits.
- 2. A semiconductor integrated circuit device according to claim 1, wherein the static random access memory includes four of the N channel MOS transistors as transfer gate transistors and four of the complementary MOS circuits each composed of a P channel MOS transistor and an N channel MOS transistor.
- 3. A semiconductor integrated circuit device according to claim 1, wherein the static random access memory includes two of the N channel MOS transistors as transfer gate transistors and two of the complementary MOS circuits each composed of a P channel MOS transistor and an N channel MOS transistor.
- 4. A semiconductor integrated circuit device according to claim 2, wherein no metal wiring extends on gates of any of the MOS transistors.
- 5. A semiconductor integrated circuit device according to claim 3, wherein no metal wiring extends on gates of any of the MOS transistors.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-085012 |
Mar 1998 |
JP |
|
Parent Case Info
This is a division of application Ser. No. 09/265,876, filed Mar. 11, 1999 now U.S. Pat. No. 6,223,097 which is incorporated herein by reference.
US Referenced Citations (12)